[MC] Add MCInstrAnalysis::evaluateMemoryOperandAddress

[seiya]

Summary

Add a new method which tries to compute the target address referenced by an operand.

This patch supports x86_64 RIP-relative addressing for now.

It is necessary to print referenced symbol names in llvm-objdump.

[jhenderson]

Looks like you need to clang-format your changes?

[bcain]

llvm/include/llvm/MC/MCInstrAnalysis.h

162

It may make more sense for this to return an llvm::Optional<uint64_t>.

[MaskRay]

Are you planning to use it in llvm-objdump to symbolize instructions like: mov 0x206a3d(%rip),%rax # 207fe8 <__cxa_finalize@plt+0x2066a8>?

When you make a dependent llvm-objdump change, you may add the test somewhere under test/tools/llvm-objdump

[seiya]

llvm/include/llvm/MC/MCInstrAnalysis.h

162

It returns bool for consistency with evaluateBranch but I think Optional is better too. What do you think about the consistency with other method definitions? I don't have a strong opinion.

[seiya]

In D63847#1561882, @MaskRay wrote:

Are you planning to use it in llvm-objdump to symbolize instructions like: mov 0x206a3d(%rip),%rax # 207fe8 <__cxa_finalize@plt+0x2066a8>?

When you make a dependent llvm-objdump change, you may add the test somewhere under test/tools/llvm-objdump

Yes. The example you showed is exactly what I'm going to implement. I plan to submit a separate patch which add tests along with the implementation of the feature in llvm-objdump.

[seiya]

clang-formatted

[seiya]

Reverted some unrelated changes caused by clang-format.

[jhenderson]

llvm/include/llvm/MC/MCInstrAnalysis.h

162

Personally, I have no issue in this becoming Optional to improve things (or possibly Expected, depending on what you want to do on failure). A later change could change the signature of evaluateBranch.

llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

537

Nit: trailing full stop.

[seiya]

• Use Optional

[seiya]

llvm/include/llvm/MC/MCInstrAnalysis.h

162

That sounds good to me. I replaced bool with Optional.

[seiya]

Ping!

[seiya]

Ping

[jhenderson]

I've added a couple more reviewers for you @seiya, based on the code owners file. No idea if either of them will have a chance to give this a look, but hopefully somebody will.

[jgalenson]

Sorry, but I'm not familiar with x86.

[craig.topper]

llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

555

Should we check that getReg returns 0 for the segment register operand?

[seiya]

• Check that the segment register operand is not set.

[seiya]

llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

555

Yes we should. Thanks.

[craig.topper]

llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

546

"const MCInstrDesc &MCID" or "const MCInstr &Desc" would be better.

[seiya]

• Addressed a review comment.

[craig.topper]

LGTM

llvm/include/llvm/MC/MCInstrAnalysis.h

public:
   /// destination.
   virtual bool isOptimizableRegisterMove(const MCInst &MI,
                                          unsigned CPUID) const {
     return false;
   }
 
   /// Given a branch instruction try to get the address the branch
   /// targets. Return true on success, and the address in Target.
-  virtual bool
-  evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
+  virtual bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
+                              uint64_t &Target) const;
+
+  /// Given an instruction tries to get the address of a memory operand. Returns
+  /// true on success, and the address in Target.
+  virtual bool evaluateMemoryOperandAddress(const MCInst &Inst, uint64_t Addr,
+                                            uint64_t Size,
                                             uint64_t &Target) const;
 
   /// Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
   virtual std::vector<std::pair<uint64_t, uint64_t>>
   findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
                  uint64_t GotPltSectionVA, const Triple &TargetTriple) const {
     return {};
   }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_MC_MCINSTRANALYSIS_H

llvm/lib/MC/MCInstrAnalysis.cpp

 
 bool MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
                                      uint64_t Size, uint64_t &Target) const {
   if (Inst.getNumOperands() == 0 ||
       Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
     return false;
 
   int64_t Imm = Inst.getOperand(0).getImm();
-  Target = Addr+Size+Imm;
+  Target = Addr + Size + Imm;
   return true;
 }
+
+bool MCInstrAnalysis::evaluateMemoryOperandAddress(const MCInst &Inst,
+                                                   uint64_t Addr, uint64_t Size,
+                                                   uint64_t &Target) const {
+  return false;
+}

llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

 #include "X86GenSubtargetInfo.inc"
 
   bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
                             APInt &Mask) const override;
   std::vector<std::pair<uint64_t, uint64_t>>
   findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
                  uint64_t GotSectionVA,
                  const Triple &TargetTriple) const override;
+  bool evaluateMemoryOperandAddress(const MCInst &Inst, uint64_t Addr,
+                                    uint64_t Size,
+                                    uint64_t &Target) const override;
 };
 
 #define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
 #include "X86GenSubtargetInfo.inc"
 
 bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI,
                                               const MCInst &Inst,
                                               APInt &Mask) const {
std::vector<std::pair<uint64_t, uint64_t>> X86MCInstrAnalysis::findPltEntries(
     uint64_t GotPltSectionVA, const Triple &TargetTriple) const {
   switch (TargetTriple.getArch()) {
     case Triple::x86:
       return findX86PltEntries(PltSectionVA, PltContents, GotPltSectionVA);
     case Triple::x86_64:
       return findX86_64PltEntries(PltSectionVA, PltContents);
     default:
       return {};
     }
 }
 
+bool X86MCInstrAnalysis::evaluateMemoryOperandAddress(const MCInst &Inst,
+                                                      uint64_t Addr,
+                                                      uint64_t Size,
+                                                      uint64_t &Target) const {
+  MCInstrDesc Opcode = Info->get(Inst.getOpcode());
+  int MemOpStart = X86II::getMemoryOperandNo(Opcode.TSFlags);
+  if (MemOpStart == -1)
+    return false;
+  MemOpStart += X86II::getOperandBias(Opcode);
+
+  const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg);
+  const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg);
+  const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt);
+  const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp);
+  if (IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || !Disp.isImm())
+    return false;
+
+  // RIP-relative addressing
+  if (BaseReg.getReg() == X86::RIP) {
+    Target = Addr + Size + Disp.getImm();
+    return true;
+  }
+
+  return false;
+}
+
 } // end of namespace X86_MC
 
 } // end of namespace llvm
 
 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
   return new X86_MC::X86MCInstrAnalysis(Info);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeX86TargetMC() {
   for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
     // Register the MC asm info.
     RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
 
     // Register the MC register info.