[ARM] Permit auto-vectorization using MVE

[dmgreen]

Summary

Correctly report the number of registers available to the auto-vectorizer. Also allow FP auto-vectorization for MVE without -Ofast/-ffast-math, due to support for IEEE FP arithmetic and parity between scalar and vector FP behaviour.

Patch by David Sherwood.

[dmgreen]

This really depends on a lot of instruction selection being in place first.

[dmgreen]

OK. It's time. Lets do this.

[SjoerdMeijer]

OK. It's time. Lets do this.

Yep :-)

It's difficult to imagine, but maybe wait a day with committing this in case someone is unhappy or has doubts.

llvm/lib/Target/ARM/ARMTargetTransformInfo.h

public:
   bool shouldFavorBackedgeIndex(const Loop *L) const {
     if (L->getHeader()->getParent()->hasOptSize())
       return false;
     return ST->isMClass() && ST->isThumb2() && L->getNumBlocks() == 1;
   }
 
   /// Floating-point computation using ARMv8 AArch32 Advanced
   /// SIMD instructions remains unchanged from ARMv7. Only AArch64 SIMD
-  /// is IEEE-754 compliant, but it's not covered in this target.
+  /// and Arm MVE are IEEE-754 compliant.
   bool isFPVectorizationPotentiallyUnsafe() {
-    return !ST->isTargetDarwin();
+    return !ST->isTargetDarwin() && !ST->hasMVEFloatOps();
   }
 
   /// \name Scalar TTI Implementations
   /// @{
 
   int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
                             Type *Ty);
 
   using BaseT::getIntImmCost;
   int getIntImmCost(const APInt &Imm, Type *Ty);
 
   int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
 
   /// @}
 
   /// \name Vector TTI Implementations
   /// @{
 
   unsigned getNumberOfRegisters(bool Vector) {
     if (Vector) {
       if (ST->hasNEON())
         return 16;
+      if (ST->hasMVEIntegerOps())
+        return 8;
       return 0;
     }
 
     if (ST->isThumb1Only())
       return 8;
     return 13;
   }
 
   unsigned getRegisterBitWidth(bool Vector) const {
     if (Vector) {
       if (ST->hasNEON())
         return 128;
+      if (ST->hasMVEIntegerOps())
+        return 128;
       return 0;
     }
 
     return 32;
   }
 
   unsigned getMaxInterleaveFactor(unsigned VF) {
     return ST->getMaxInterleaveFactor();

llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll

 ; RUN: opt -mtriple armv7-linux-gnueabihf -loop-vectorize -S %s -debug-only=loop-vectorize -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=LINUX
 ; RUN: opt -mtriple armv8-linux-gnu -loop-vectorize -S %s -debug-only=loop-vectorize -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=LINUX
+; RUN: opt -mtriple armv8.1.m-none-eabi -mattr=+mve.fp -loop-vectorize -S %s -debug-only=loop-vectorize -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=MVE
 ; RUN: opt -mtriple armv7-unknwon-darwin -loop-vectorize -S %s -debug-only=loop-vectorize -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=DARWIN
 ; REQUIRES: asserts
 
 ; Testing the ability of the loop vectorizer to tell when SIMD is safe or not
 ; regarding IEEE 754 standard.
 ; On Linux, we only want the vectorizer to work when -ffast-math flag is set,
 ; because NEON is not IEEE compliant.
 ; Darwin, on the other hand, doesn't support subnormals, and all optimizations

 
 for.end:                                          ; preds = %for.end.loopexit, %entry
   ret void
 }
 
 ; Floating-point loops need fast-math to be vectorizeable
 ; LINUX: Checking a loop in "sumf"
 ; LINUX: Potentially unsafe FP op prevents vectorization
+; MVE: Checking a loop in "sumf"
+; MVE: We can vectorize this loop!
 ; DARWIN: Checking a loop in "sumf"
 ; DARWIN: We can vectorize this loop!
 define void @sumf(float* noalias nocapture readonly %A, float* noalias nocapture readonly %B, float* noalias nocapture %C, i32 %N) {
 entry:
   %cmp5 = icmp eq i32 %N, 0
   br i1 %cmp5, label %for.end, label %for.body.preheader
 
 for.body.preheader:                               ; preds = %entry

 for.end:                                          ; preds = %for.end.loopexit, %entry
   %Red.0.lcssa = phi i32 [ undef, %entry ], [ %add.lcssa, %for.end.loopexit ]
   ret i32 %Red.0.lcssa
 }
 
 ; Floating-point loops need fast-math to be vectorizeable
 ; LINUX: Checking a loop in "redf"
 ; LINUX: Potentially unsafe FP op prevents vectorization
+; MVE: Checking a loop in "redf"
+; MVE: We can vectorize this loop!
 ; DARWIN: Checking a loop in "redf"
 ; DARWIN: We can vectorize this loop!
 define float @redf(float* noalias nocapture readonly %a, float* noalias nocapture readonly %b, i32 %N) {
 entry:
   %cmp5 = icmp eq i32 %N, 0
   br i1 %cmp5, label %for.end, label %for.body.preheader
 
 for.body.preheader:                               ; preds = %entry