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Differential D63551

[GlobalISel] Accept multiple vregs for lowerCall's arguments
ClosedPublic

Authored by rovka on Jun 19 2019, 6:59 AM.

Details

Reviewers
aemerson
t.p.northover
aditya_nandakumar
dsanders
arsenm
igorb
aivchenk
Commits
rG43fb5ae50c53: [GlobalISel] Accept multiple vregs for lowerCall's args
rL364512: [GlobalISel] Accept multiple vregs for lowerCall's args
Summary

Change the interface of CallLowering::lowerCall to accept several
virtual registers for each argument, instead of just one. This is a
follow-up to D46018.

CallLowering::lowerReturn was similarly refactored in D49660 and
lowerFormalArguments in D63549.




With this change, we no longer pack the virtual registers generated for

aggregates into one big lump before delegating to the target. Therefore,

the target can decide itself whether it wants to handle them as separate

pieces or use one big register.



ARM and AArch64 have been updated to use the passed in virtual registers

directly, which means we no longer need to generate so many

merge/extract instructions.



NFCI for AMDGPU, Mips and X86.
Diff Detail
Repository 
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Event Timeline
rovka created this revision.Jun 19 2019, 6:59 AM
Herald added a project: Restricted Project.  ·  View Herald TranscriptJun 19 2019, 6:59 AM
Herald added subscribers: Petar.Avramovic, volkan, atanasyan and 7 others.  ·  View Herald Transcript
rovka added a child revision: D63552: [AArch64 GlobalISel] Cleanup CallLowering. NFCI.Jun 19 2019, 7:02 AM
rovka added a parent revision: D63550: [GlobalISel] Accept multiple vregs for lowerCall's result.
rovka retitled this revision from [GlobalISel] Accept multiple vregs for lowerCall's result to [GlobalISel] Accept multiple vregs for lowerCall's arguments.
rovka edited the summary of this revision. (Show Details)
arsenm accepted this revision.Jun 19 2019, 4:16 PM
This revision is now accepted and ready to land.Jun 19 2019, 4:16 PM
rovka updated this revision to Diff 205761.Jun 20 2019, 2:37 AM
Thanks for the review! More context for posterity though :)
aemerson added inline comments.Jun 20 2019, 11:36 AM
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp


1257 ↗(On Diff #205761)
Do we still need packRegs anywhere at all?
aemerson added a comment.Jun 20 2019, 11:38 AM
LGTM too if we remove the last packRegs use and delete the IRTranslator pack/unpackRegs() implementations.
rovka added a comment.Jun 24 2019, 1:37 AM


In D63551#1552409, @aemerson wrote:


LGTM too if we remove the last packRegs use and delete the IRTranslator pack/unpackRegs() implementations.





I was going to do that, but I'm not super familiar with the intrinsics code so I wanted to get feedback on the general idea first. I'll try to give it a shot this week. Thanks for all the reviews!
rovka added a comment.Jun 25 2019, 3:41 AM
Hi Amara,



Is something like this OK for intrinsics: https://reviews.llvm.org/differential/diff/206394/ ? It has the disadvantage that if we have an intrinsic with 2 aggregate args, it will be hard to tell where one of them ends and the next one begins. OTOH, I'm having trouble finding intrinsics with even one aggregate parameter, and in fact just using getOrCreateVReg there doesn't cause check-all to crash (nor the test-suite, nor selfhost at -O0 on AArch64).



Alternatively, we could preserve the old interface here and try to move pack/unpackRegs to utils, where we can use them from both the IRTranslator and CallLowering.



Either way, it would be nice to be able to add a test-case before changing this interface, but like I said I don't really know my way around intrinsics that well. Any suggestions?
aemerson added a comment.Jun 25 2019, 1:38 PM


In D63551#1557215, @rovka wrote:


Hi Amara,



Is something like this OK for intrinsics: https://reviews.llvm.org/differential/diff/206394/ ? It has the disadvantage that if we have an intrinsic with 2 aggregate args, it will be hard to tell where one of them ends and the next one begins. OTOH, I'm having trouble finding intrinsics with even one aggregate parameter, and in fact just using getOrCreateVReg there doesn't cause check-all to crash (nor the test-suite, nor selfhost at -O0 on AArch64).



Alternatively, we could preserve the old interface here and try to move pack/unpackRegs to utils, where we can use them from both the IRTranslator and CallLowering.



Either way, it would be nice to be able to add a test-case before changing this interface, but like I said I don't really know my way around intrinsics that well. Any suggestions?





You're probably right, I can't think of an intrinsic for a test case. I think we should actually fall back if getOrCreateVRegs() ever returns multiple vregs there, we can cross that bridge when we come to it (if ever).
Closed by commit rL364512: [GlobalISel] Accept multiple vregs for lowerCall's args (authored by rovka).  ·  Explain WhyJun 27 2019, 2:21 AM
This revision was automatically updated to reflect the committed changes.
Revision Contents
PathSize
llvm/
trunk/
include/
llvm/
CodeGen/
GlobalISel/
10 lines
lib/
CodeGen/
GlobalISel/
2 lines
10 lines
Target/
AArch64/
3 lines
ARM/
11 lines
X86/
4 lines
test/
CodeGen/
AArch64/
GlobalISel/
10 lines
9 lines
29 lines
ARM/
GlobalISel/
43 lines
Diff 206800
llvm/trunk/include/llvm/CodeGen/GlobalISel/CallLowering.h
Show First 20 Lines • Show All 256 Lines • ▼ Show 20 Linespublic:

  /// marshalling.
  /// marshalling.

  ///
  ///

  /// \p CI is the call/invoke instruction.
  /// \p CI is the call/invoke instruction.

  ///
  ///

  /// \p ResRegs are the registers where the call's return value should be
  /// \p ResRegs are the registers where the call's return value should be

  /// stored (or 0 if there is no return value). There will be one register for
  /// stored (or 0 if there is no return value). There will be one register for

  /// each non-aggregate type, as returned by \c computeValueLLTs.
  /// each non-aggregate type, as returned by \c computeValueLLTs.

  ///
  ///

  /// \p ArgRegs is a list of virtual registers containing each argument that
  /// \p ArgRegs is a list of lists of virtual registers containing each

  /// needs to be passed.
  /// argument that needs to be passed (argument \c i should be placed in \c

  /// ArgRegs[i]). For each argument, there will be one register for each

  /// non-aggregate type, as returned by \c computeValueLLTs.

  ///
  ///

  /// \p SwiftErrorVReg is non-zero if the call has a swifterror inout
  /// \p SwiftErrorVReg is non-zero if the call has a swifterror inout

  /// parameter, and contains the vreg that the swifterror should be copied into
  /// parameter, and contains the vreg that the swifterror should be copied into

  /// after the call.
  /// after the call.

  ///
  ///

  /// \p GetCalleeReg is a callback to materialize a register for the callee if
  /// \p GetCalleeReg is a callback to materialize a register for the callee if

  /// the target determines it cannot jump to the destination based purely on \p
  /// the target determines it cannot jump to the destination based purely on \p

  /// CI. This might be because \p CI is indirect, or because of the limited
  /// CI. This might be because \p CI is indirect, or because of the limited

  /// range of an immediate jump.
  /// range of an immediate jump.

  ///
  ///

  /// \return true if the lowering succeeded, false otherwise.
  /// \return true if the lowering succeeded, false otherwise.

  bool lowerCall(MachineIRBuilder &MIRBuilder, ImmutableCallSite CS,
  bool lowerCall(MachineIRBuilder &MIRBuilder, ImmutableCallSite CS,

                 ArrayRef<Register> ResRegs, ArrayRef<Register> ArgRegs,
                 ArrayRef<Register> ResRegs,

                 Register SwiftErrorVReg,
                 ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg,

                 std::function<unsigned()> GetCalleeReg) const;
                 std::function<unsigned()> GetCalleeReg) const;

};
};




} // end namespace llvm
} // end namespace llvm




#endif // LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
#endif // LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H

llvm/trunk/lib/CodeGen/GlobalISel/CallLowering.cpp
Show All 23 Lines
#define DEBUG_TYPE "call-lowering"
#define DEBUG_TYPE "call-lowering"




using namespace llvm;
using namespace llvm;




void CallLowering::anchor() {}
void CallLowering::anchor() {}




bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, ImmutableCallSite CS,
bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, ImmutableCallSite CS,

                             ArrayRef<Register> ResRegs,
                             ArrayRef<Register> ResRegs,

                             ArrayRef<Register> ArgRegs,
                             ArrayRef<ArrayRef<Register>> ArgRegs,

                             Register SwiftErrorVReg,
                             Register SwiftErrorVReg,

                             std::function<unsigned()> GetCalleeReg) const {
                             std::function<unsigned()> GetCalleeReg) const {

  auto &DL = CS.getParent()->getParent()->getParent()->getDataLayout();
  auto &DL = CS.getParent()->getParent()->getParent()->getDataLayout();




  // First step is to marshall all the function's parameters into the correct
  // First step is to marshall all the function's parameters into the correct

  // physregs and memory locations. Gather the sequence of argument types that
  // physregs and memory locations. Gather the sequence of argument types that

  // we'll pass to the assigner function.
  // we'll pass to the assigner function.

  SmallVector<ArgInfo, 8> OrigArgs;
  SmallVector<ArgInfo, 8> OrigArgs;

▲ Show 20 Lines • Show All 237 Lines • Show Last 20 Lines
llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
Show First 20 Lines • Show All 1,581 Lines • ▼ Show 20 Lines  if (F && F->isIntrinsic()) {

    ID = F->getIntrinsicID();
    ID = F->getIntrinsicID();

    if (TII && ID == Intrinsic::not_intrinsic)
    if (TII && ID == Intrinsic::not_intrinsic)

      ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));
      ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));

  }
  }




  if (!F || !F->isIntrinsic() || ID == Intrinsic::not_intrinsic) {
  if (!F || !F->isIntrinsic() || ID == Intrinsic::not_intrinsic) {

    ArrayRef<Register> Res = getOrCreateVRegs(CI);
    ArrayRef<Register> Res = getOrCreateVRegs(CI);




    SmallVector<Register, 8> Args;
    SmallVector<ArrayRef<Register>, 8> Args;

    Register SwiftErrorVReg;
    Register SwiftErrorVReg = 0;

    for (auto &Arg: CI.arg_operands()) {
    for (auto &Arg: CI.arg_operands()) {

      if (CLI->supportSwiftError() && isSwiftError(Arg)) {
      if (CLI->supportSwiftError() && isSwiftError(Arg)) {

        LLT Ty = getLLTForType(*Arg->getType(), *DL);
        LLT Ty = getLLTForType(*Arg->getType(), *DL);

        Register InVReg = MRI->createGenericVirtualRegister(Ty);
        Register InVReg = MRI->createGenericVirtualRegister(Ty);

        MIRBuilder.buildCopy(InVReg, SwiftError.getOrCreateVRegUseAt(
        MIRBuilder.buildCopy(InVReg, SwiftError.getOrCreateVRegUseAt(

                                         &CI, &MIRBuilder.getMBB(), Arg));
                                         &CI, &MIRBuilder.getMBB(), Arg));

        Args.push_back(InVReg);
        Args.push_back(InVReg);

        SwiftErrorVReg =
        SwiftErrorVReg =

            SwiftError.getOrCreateVRegDefAt(&CI, &MIRBuilder.getMBB(), Arg);
            SwiftError.getOrCreateVRegDefAt(&CI, &MIRBuilder.getMBB(), Arg);

        continue;
        continue;

      }
      }

      Args.push_back(packRegs(*Arg, MIRBuilder));
      Args.push_back(getOrCreateVRegs(*Arg));

    }
    }




    MF->getFrameInfo().setHasCalls(true);
    MF->getFrameInfo().setHasCalls(true);

    bool Success =
    bool Success =

        CLI->lowerCall(MIRBuilder, &CI, Res, Args, SwiftErrorVReg,
        CLI->lowerCall(MIRBuilder, &CI, Res, Args, SwiftErrorVReg,

                       [&]() { return getOrCreateVReg(*CI.getCalledValue()); });
                       [&]() { return getOrCreateVReg(*CI.getCalledValue()); });




    return Success;
    return Success;

▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Linesbool IRTranslator::translateInvoke(const User &U,

  // Emit the actual call, bracketed by EH_LABELs so that the MF knows about
  // Emit the actual call, bracketed by EH_LABELs so that the MF knows about

  // the region covered by the try.
  // the region covered by the try.

  MCSymbol *BeginSymbol = Context.createTempSymbol();
  MCSymbol *BeginSymbol = Context.createTempSymbol();

  MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
  MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);




  ArrayRef<Register> Res;
  ArrayRef<Register> Res;

  if (!I.getType()->isVoidTy())
  if (!I.getType()->isVoidTy())

    Res = getOrCreateVRegs(I);
    Res = getOrCreateVRegs(I);

  SmallVector<Register, 8> Args;
  SmallVector<ArrayRef<Register>, 8> Args;

  Register SwiftErrorVReg = 0;
  Register SwiftErrorVReg = 0;

  for (auto &Arg : I.arg_operands()) {
  for (auto &Arg : I.arg_operands()) {

    if (CLI->supportSwiftError() && isSwiftError(Arg)) {
    if (CLI->supportSwiftError() && isSwiftError(Arg)) {

      LLT Ty = getLLTForType(*Arg->getType(), *DL);
      LLT Ty = getLLTForType(*Arg->getType(), *DL);

      Register InVReg = MRI->createGenericVirtualRegister(Ty);
      Register InVReg = MRI->createGenericVirtualRegister(Ty);

      MIRBuilder.buildCopy(InVReg, SwiftError.getOrCreateVRegUseAt(
      MIRBuilder.buildCopy(InVReg, SwiftError.getOrCreateVRegUseAt(

                                       &I, &MIRBuilder.getMBB(), Arg));
                                       &I, &MIRBuilder.getMBB(), Arg));

      Args.push_back(InVReg);
      Args.push_back(InVReg);

      SwiftErrorVReg =
      SwiftErrorVReg =

          SwiftError.getOrCreateVRegDefAt(&I, &MIRBuilder.getMBB(), Arg);
          SwiftError.getOrCreateVRegDefAt(&I, &MIRBuilder.getMBB(), Arg);

      continue;
      continue;

    }
    }




    Args.push_back(packRegs(*Arg, MIRBuilder));
    Args.push_back(getOrCreateVRegs(*Arg));

  }
  }




  if (!CLI->lowerCall(MIRBuilder, &I, Res, Args, SwiftErrorVReg,
  if (!CLI->lowerCall(MIRBuilder, &I, Res, Args, SwiftErrorVReg,

                      [&]() { return getOrCreateVReg(*I.getCalledValue()); }))
                      [&]() { return getOrCreateVReg(*I.getCalledValue()); }))

    return false;
    return false;




  MCSymbol *EndSymbol = Context.createTempSymbol();
  MCSymbol *EndSymbol = Context.createTempSymbol();

  MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);
  MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);

▲ Show 20 Lines • Show All 676 Lines • Show Last 20 Lines
llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
Show First 20 Lines • Show All 435 Lines • ▼ Show 20 Linesbool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,

                                    Register SwiftErrorVReg) const {
                                    Register SwiftErrorVReg) const {

  MachineFunction &MF = MIRBuilder.getMF();
  MachineFunction &MF = MIRBuilder.getMF();

  const Function &F = MF.getFunction();
  const Function &F = MF.getFunction();

  MachineRegisterInfo &MRI = MF.getRegInfo();
  MachineRegisterInfo &MRI = MF.getRegInfo();

  auto &DL = F.getParent()->getDataLayout();
  auto &DL = F.getParent()->getDataLayout();




  SmallVector<ArgInfo, 8> SplitArgs;
  SmallVector<ArgInfo, 8> SplitArgs;

  for (auto &OrigArg : OrigArgs) {
  for (auto &OrigArg : OrigArgs) {

    assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet");

    splitToValueTypes(OrigArg, SplitArgs, DL, MRI, CallConv,
    splitToValueTypes(OrigArg, SplitArgs, DL, MRI, CallConv,

                      [&](Register Reg, uint64_t Offset) {
                      [&](Register Reg, uint64_t Offset) {

                        MIRBuilder.buildExtract(Reg, OrigArg.Regs[0], Offset);
                        llvm_unreachable("Call params should already be split");

                      });
                      });

    // AAPCS requires that we zero-extend i1 to 8 bits by the caller.
    // AAPCS requires that we zero-extend i1 to 8 bits by the caller.

    if (OrigArg.Ty->isIntegerTy(1))
    if (OrigArg.Ty->isIntegerTy(1))

      SplitArgs.back().Flags.setZExt();
      SplitArgs.back().Flags.setZExt();

  }
  }




  // Find out which ABI gets to decide where things go.
  // Find out which ABI gets to decide where things go.

  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();

▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines
llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp
Show First 20 Lines • Show All 590 Lines • ▼ Show 20 Lines    if (!isSupportedType(DL, TLI, Arg.Ty))

      return false;
      return false;




    if (!Arg.IsFixed)
    if (!Arg.IsFixed)

      IsVarArg = true;
      IsVarArg = true;




    if (Arg.Flags.isByVal())
    if (Arg.Flags.isByVal())

      return false;
      return false;




    assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
    splitToValueTypes(Arg, ArgInfos, MF, [&](Register Reg) {


      llvm_unreachable("Function args should already be split");

    SmallVector<Register, 8> Regs;
    });

    splitToValueTypes(Arg, ArgInfos, MF,

                      [&](unsigned Reg) { Regs.push_back(Reg); });



    if (Regs.size() > 1)

      MIRBuilder.buildUnmerge(Regs, Arg.Regs[0]);

  }
  }




  auto ArgAssignFn = TLI.CCAssignFnForCall(CallConv, IsVarArg);
  auto ArgAssignFn = TLI.CCAssignFnForCall(CallConv, IsVarArg);

  OutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn);
  OutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn);

  if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler))
  if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler))

    return false;
    return false;




  // Now we can add the actual call instruction to the correct basic block.
  // Now we can add the actual call instruction to the correct basic block.

Show All 28 Lines
llvm/trunk/lib/Target/X86/X86CallLowering.cpp
Show First 20 Lines • Show All 403 Lines • ▼ Show 20 Linesbool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,




  SmallVector<ArgInfo, 8> SplitArgs;
  SmallVector<ArgInfo, 8> SplitArgs;

  for (const auto &OrigArg : OrigArgs) {
  for (const auto &OrigArg : OrigArgs) {




    // TODO: handle not simple cases.
    // TODO: handle not simple cases.

    if (OrigArg.Flags.isByVal())
    if (OrigArg.Flags.isByVal())

      return false;
      return false;




    assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet");
    if (OrigArg.Regs.size() > 1)

      return false;



    if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
    if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,

                           [&](ArrayRef<Register> Regs) {
                           [&](ArrayRef<Register> Regs) {

                             MIRBuilder.buildUnmerge(Regs, OrigArg.Regs[0]);
                             MIRBuilder.buildUnmerge(Regs, OrigArg.Regs[0]);

                           }))
                           }))

      return false;
      return false;

  }
  }

  // Do the actual argument marshalling.
  // Do the actual argument marshalling.

  OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86);
  OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86);

▲ Show 20 Lines • Show All 66 Lines • Show Last 20 Lines
llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=irtranslator -enable-cse-in-irtranslator=1 -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=irtranslator -enable-cse-in-irtranslator=1 -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s




; CHECK-LABEL: name: test_split_struct
; CHECK-LABEL: name: test_split_struct

; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0

; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)
; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)

; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 8

; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST]](s64)
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST]](s64)

; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8 from %ir.ptr + 8)
; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8 from %ir.ptr + 8)




; CHECK: [[IMPDEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF

; CHECK: [[INS1:%[0-9]+]]:_(s128) = G_INSERT [[IMPDEF]], [[LO]](s64), 0

; CHECK: [[INS2:%[0-9]+]]:_(s128) = G_INSERT [[INS1]], [[HI]](s64), 64

; CHECK: [[EXTLO:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 0

; CHECK: [[EXTHI:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 64



; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp

; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0

; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST2]](s64)
; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST2]](s64)

; CHECK: G_STORE [[EXTLO]](s64), [[GEP2]](p0) :: (store 8 into stack, align 1)
; CHECK: G_STORE [[LO]](s64), [[GEP2]](p0) :: (store 8 into stack, align 1)

; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp

; CHECK: [[CST3:%[0-9]+]]:_(s64) = COPY [[CST]]
; CHECK: [[CST3:%[0-9]+]]:_(s64) = COPY [[CST]]

; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST3]](s64)
; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST3]](s64)

; CHECK: G_STORE [[EXTHI]](s64), [[GEP3]](p0) :: (store 8 into stack + 8, align 1)
; CHECK: G_STORE [[HI]](s64), [[GEP3]](p0) :: (store 8 into stack + 8, align 1)

define void @test_split_struct([2 x i64]* %ptr) {
define void @test_split_struct([2 x i64]* %ptr) {

  %struct = load [2 x i64], [2 x i64]* %ptr
  %struct = load [2 x i64], [2 x i64]* %ptr

  call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3,
  call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3,

                               i64 4, i64 5, i64 6,
                               i64 4, i64 5, i64 6,

                               [2 x i64] %struct)
                               [2 x i64] %struct)

  ret void
  ret void

}
}




declare void @take_split_struct([2 x i64]* %ptr, i64, i64, i64,
declare void @take_split_struct([2 x i64]* %ptr, i64, i64, i64,

                               i64, i64, i64,
                               i64, i64, i64,

                               [2 x i64] %in) ;
                               [2 x i64] %in) ;

llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Linesdefine void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) {

  ret void
  ret void

}
}




; CHECK-LABEL: name: test_split_struct
; CHECK-LABEL: name: test_split_struct

; CHECK: [[LD1:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)
; CHECK: [[LD1:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)

; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 8

; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP %0, [[CST]](s64)
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP %0, [[CST]](s64)

; CHECK: [[LD2:%[0-9]+]]:_(s64) = G_LOAD %3(p0) :: (load 8 from %ir.ptr + 8)
; CHECK: [[LD2:%[0-9]+]]:_(s64) = G_LOAD %3(p0) :: (load 8 from %ir.ptr + 8)

; CHECK: [[IMPDEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF

; CHECK: [[INS1:%[0-9]+]]:_(s128) = G_INSERT [[IMPDEF]], [[LD1]](s64), 0

; CHECK: [[INS2:%[0-9]+]]:_(s128) = G_INSERT [[INS1]], [[LD2]](s64), 64

; CHECK:  [[EXT1:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 0

; CHECK: [[EXT2:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 64




; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp

; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0

; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]](s64)
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]](s64)

; CHECK: G_STORE [[EXT1]](s64), [[ADDR]](p0) :: (store 8 into stack, align 1)
; CHECK: G_STORE [[LD1]](s64), [[ADDR]](p0) :: (store 8 into stack, align 1)




; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp

; CHECK: [[OFF:%[0-9]+]]:_(s64) = COPY [[CST]]
; CHECK: [[OFF:%[0-9]+]]:_(s64) = COPY [[CST]]

; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]

; CHECK: G_STORE [[EXT2]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 1)
; CHECK: G_STORE [[LD2]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 1)

define void @test_split_struct([2 x i64]* %ptr) {
define void @test_split_struct([2 x i64]* %ptr) {

  %struct = load [2 x i64], [2 x i64]* %ptr
  %struct = load [2 x i64], [2 x i64]* %ptr

  call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3,
  call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3,

                               i64 4, i64 5, i64 6,
                               i64 4, i64 5, i64 6,

                               [2 x i64] %struct)
                               [2 x i64] %struct)

  ret void
  ret void

}
}




Show All 16 Lines
llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll
Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Lines
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP %0, [[CST1]](s64)
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP %0, [[CST1]](s64)

; CHECK: [[LD2:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load 8 from %ir.addr + 8)
; CHECK: [[LD2:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load 8 from %ir.addr + 8)

; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16

; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP %0, [[CST2]](s64)
; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP %0, [[CST2]](s64)

; CHECK: [[LD3:%[0-9]+]]:_(s64) = G_LOAD [[GEP2]](p0) :: (load 8 from %ir.addr + 16)
; CHECK: [[LD3:%[0-9]+]]:_(s64) = G_LOAD [[GEP2]](p0) :: (load 8 from %ir.addr + 16)

; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24

; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64)
; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64)

; CHECK: [[LD4:%[0-9]+]]:_(s64) = G_LOAD [[GEP3]](p0) :: (load 8 from %ir.addr + 24)
; CHECK: [[LD4:%[0-9]+]]:_(s64) = G_LOAD [[GEP3]](p0) :: (load 8 from %ir.addr + 24)

; CHECK: [[IMPDEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF


; CHECK: [[INS1:%[0-9]+]]:_(s256) = G_INSERT [[IMPDEF]], [[LD1]](s64), 0
; CHECK: $x0 = COPY [[LD1]](s64)

; CHECK: [[INS2:%[0-9]+]]:_(s256) = G_INSERT [[INS1]], [[LD2]](s64), 64
; CHECK: $x1 = COPY [[LD2]](s64)

; CHECK: [[INS3:%[0-9]+]]:_(s256) = G_INSERT [[INS2]], [[LD3]](s64), 128
; CHECK: $x2 = COPY [[LD3]](s64)

; CHECK: [[ARG:%[0-9]+]]:_(s256) = G_INSERT [[INS3]], [[LD4]](s64), 192
; CHECK: $x3 = COPY [[LD4]](s64)

; CHECK: [[E0:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 0

; CHECK: [[E1:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 64

; CHECK: [[E2:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 128

; CHECK: [[E3:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 192



; CHECK: $x0 = COPY [[E0]](s64)

; CHECK: $x1 = COPY [[E1]](s64)

; CHECK: $x2 = COPY [[E2]](s64)

; CHECK: $x3 = COPY [[E3]](s64)

; CHECK: BL @arr_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1, implicit-def $x2, implicit-def $x3
; CHECK: BL @arr_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1, implicit-def $x2, implicit-def $x3

; CHECK: [[E0:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[E0:%[0-9]+]]:_(s64) = COPY $x0

; CHECK: [[E1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[E1:%[0-9]+]]:_(s64) = COPY $x1

; CHECK: [[E2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: [[E2:%[0-9]+]]:_(s64) = COPY $x2

; CHECK: [[E3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK: [[E3:%[0-9]+]]:_(s64) = COPY $x3

; CHECK: $x0 = COPY [[E1]]
; CHECK: $x0 = COPY [[E1]]

declare [4 x i64] @arr_callee([4 x i64])
declare [4 x i64] @arr_callee([4 x i64])

define i64 @test_arr_call([4 x i64]* %addr) {
define i64 @test_arr_call([4 x i64]* %addr) {

▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines



; CHECK-LABEL: name: test_split_struct
; CHECK-LABEL: name: test_split_struct

; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0

; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)
; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)

; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 8

; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST]](s64)
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST]](s64)

; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8 from %ir.ptr + 8)
; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8 from %ir.ptr + 8)




; CHECK: [[IMPDEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF

; CHECK: [[INS1:%[0-9]+]]:_(s128) = G_INSERT [[IMPDEF]], [[LO]](s64), 0

; CHECK: [[INS2:%[0-9]+]]:_(s128) = G_INSERT [[INS1]], [[HI]](s64), 64

; CHECK: [[EXTLO:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 0

; CHECK: [[EXTHI:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 64



; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp

; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0

; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST2]](s64)
; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST2]](s64)

; CHECK: G_STORE [[EXTLO]](s64), [[GEP2]](p0) :: (store 8 into stack, align 1)
; CHECK: G_STORE [[LO]](s64), [[GEP2]](p0) :: (store 8 into stack, align 1)

; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp

; CHECK: [[CST3:%[0-9]+]]:_(s64) = COPY [[CST]]
; CHECK: [[CST3:%[0-9]+]]:_(s64) = COPY [[CST]]

; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST3]](s64)
; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST3]](s64)

; CHECK: G_STORE [[EXTHI]](s64), [[GEP3]](p0) :: (store 8 into stack + 8, align 1)
; CHECK: G_STORE [[HI]](s64), [[GEP3]](p0) :: (store 8 into stack + 8, align 1)

define void @test_split_struct([2 x i64]* %ptr) {
define void @test_split_struct([2 x i64]* %ptr) {

  %struct = load [2 x i64], [2 x i64]* %ptr
  %struct = load [2 x i64], [2 x i64]* %ptr

  call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3,
  call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3,

                               i64 4, i64 5, i64 6,
                               i64 4, i64 5, i64 6,

                               [2 x i64] %struct)
                               [2 x i64] %struct)

  ret void
  ret void

}
}




Show All 16 Lines
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
Show First 20 Lines • Show All 196 Lines • ▼ Show 20 Lines



declare arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32])
declare arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32])




define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) {
define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) {

; CHECK-LABEL: name: test_tiny_int_arrays
; CHECK-LABEL: name: test_tiny_int_arrays

; CHECK: liveins: $r0, $r1
; CHECK: liveins: $r0, $r1

; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0

; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1

; CHECK: [[IMPDEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF

; CHECK: [[INS1:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF]], [[R0]](s32), 0

; CHECK: [[INS2:%[0-9]+]]:_(s64) = G_INSERT [[INS1]], [[R1]](s32), 32

; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp

; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS2]](s64)

; CHECK: $r0 = COPY [[R0]]
; CHECK: $r0 = COPY [[R0]]

; CHECK: $r1 = COPY [[R1]]
; CHECK: $r1 = COPY [[R1]]

; ARM: BL @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
; ARM: BL @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1

; THUMB: tBL 14, $noreg, @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
; THUMB: tBL 14, $noreg, @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1

; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0

; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1

; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2

; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp

Show All 14 Lines



define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %arr1) {
define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %arr1) {

; CHECK-LABEL: name: test_multiple_int_arrays
; CHECK-LABEL: name: test_multiple_int_arrays

; CHECK: liveins: $r0, $r1
; CHECK: liveins: $r0, $r1

; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0

; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1

; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2

; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $r3
; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $r3

; CHECK: [[IMPDEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF

; CHECK: [[INS1:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF]], [[R0]](s32), 0

; CHECK: [[INS2:%[0-9]+]]:_(s64) = G_INSERT [[INS1]], [[R1]](s32), 32

; CHECK: [[IMPDEF2:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF

; CHECK: [[INS3:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF2]], [[R2]](s32), 0

; CHECK: [[INS4:%[0-9]+]]:_(s64) = G_INSERT [[INS3]], [[R3]](s32), 32

; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp

; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS2]](s64)

; CHECK: [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS4]](s64)

; CHECK: $r0 = COPY [[R0]]
; CHECK: $r0 = COPY [[R0]]

; CHECK: $r1 = COPY [[R1]]
; CHECK: $r1 = COPY [[R1]]

; CHECK: $r2 = COPY [[R2]]
; CHECK: $r2 = COPY [[R2]]

; CHECK: $r3 = COPY [[R3]]
; CHECK: $r3 = COPY [[R3]]

; ARM: BL @multiple_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3
; ARM: BL @multiple_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3

; THUMB: tBL 14, $noreg, @multiple_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3
; THUMB: tBL 14, $noreg, @multiple_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3

; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp

; ARM: BX_RET 14, $noreg
; ARM: BX_RET 14, $noreg

Show All 16 Lines
; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0

; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1

; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r2

; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY $r3
; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY $r3

; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]

; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]

; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]

; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]

; CHECK: [[IMPDEF:%[0-9]+]]:_(s640) = G_IMPLICIT_DEF

; CHECK: [[INS1:%[0-9]+]]:_(s640) = G_INSERT [[IMPDEF]], [[R0]](s32), 0

; CHECK: [[INS:%[0-9]+]]:_(s640) = G_INSERT {{.*}}, [[LAST_STACK_ELEMENT]](s32), 608

; CHECK: ADJCALLSTACKDOWN 64, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: ADJCALLSTACKDOWN 64, 0, 14, $noreg, implicit-def $sp, implicit $sp

; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS]](s640)

; CHECK: $r0 = COPY [[R0]]
; CHECK: $r0 = COPY [[R0]]

; CHECK: $r1 = COPY [[R1]]
; CHECK: $r1 = COPY [[R1]]

; CHECK: $r2 = COPY [[R2]]
; CHECK: $r2 = COPY [[R2]]

; CHECK: $r3 = COPY [[R3]]
; CHECK: $r3 = COPY [[R3]]

; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp

; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)
; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)

; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4
; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4

Show All 25 Lines
; LITTLE: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_0]](s32), [[ARR0_1]](s32)
; LITTLE: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_0]](s32), [[ARR0_1]](s32)

; BIG: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_1]](s32), [[ARR0_0]](s32)
; BIG: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_1]](s32), [[ARR0_0]](s32)

; CHECK: [[ARR1_0:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[ARR1_0:%[0-9]+]]:_(s32) = COPY $r2

; CHECK: [[ARR1_1:%[0-9]+]]:_(s32) = COPY $r3
; CHECK: [[ARR1_1:%[0-9]+]]:_(s32) = COPY $r3

; LITTLE: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_0]](s32), [[ARR1_1]](s32)
; LITTLE: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_0]](s32), [[ARR1_1]](s32)

; BIG: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32)
; BIG: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32)

; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]]
; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]]

; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]]
; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]]

; CHECK: [[IMPDEF:%[0-9]+]]:_(s192) = G_IMPLICIT_DEF

; CHECK: [[INS1:%[0-9]+]]:_(s192) = G_INSERT [[IMPDEF]], [[ARR0]](s64), 0

; CHECK: [[INS2:%[0-9]+]]:_(s192) = G_INSERT [[INS1]], [[ARR1]](s64), 64

; CHECK: [[INS3:%[0-9]+]]:_(s192) = G_INSERT [[INS2]], [[ARR2]](s64), 128

; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp

; CHECK: [[ARR0:%[0-9]+]]:_(s64), [[ARR1:%[0-9]+]]:_(s64), [[ARR2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[INS3]](s192)

; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64)
; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64)

; LITTLE: $r0 = COPY [[ARR0_0]](s32)
; LITTLE: $r0 = COPY [[ARR0_0]](s32)

; LITTLE: $r1 = COPY [[ARR0_1]](s32)
; LITTLE: $r1 = COPY [[ARR0_1]](s32)

; BIG: $r0 = COPY [[ARR0_1]](s32)
; BIG: $r0 = COPY [[ARR0_1]](s32)

; BIG: $r1 = COPY [[ARR0_0]](s32)
; BIG: $r1 = COPY [[ARR0_0]](s32)

; CHECK: [[ARR1_0:%[0-9]+]]:_(s32), [[ARR1_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR1]](s64)
; CHECK: [[ARR1_0:%[0-9]+]]:_(s32), [[ARR1_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR1]](s64)

; LITTLE: $r2 = COPY [[ARR1_0]](s32)
; LITTLE: $r2 = COPY [[ARR1_0]](s32)

; LITTLE: $r3 = COPY [[ARR1_1]](s32)
; LITTLE: $r3 = COPY [[ARR1_1]](s32)

Show All 36 Lines
; CHECK: [[Z0_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z0_ID]]
; CHECK: [[Z0_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z0_ID]]

; CHECK: [[Z0:%[0-9]+]]:_(s64) = G_LOAD [[Z0_FI]]{{.*}}load 8
; CHECK: [[Z0:%[0-9]+]]:_(s64) = G_LOAD [[Z0_FI]]{{.*}}load 8

; CHECK: [[Z1_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z1_ID]]
; CHECK: [[Z1_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z1_ID]]

; CHECK: [[Z1:%[0-9]+]]:_(s64) = G_LOAD [[Z1_FI]]{{.*}}load 8
; CHECK: [[Z1:%[0-9]+]]:_(s64) = G_LOAD [[Z1_FI]]{{.*}}load 8

; CHECK: [[Z2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z2_ID]]
; CHECK: [[Z2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z2_ID]]

; CHECK: [[Z2:%[0-9]+]]:_(s64) = G_LOAD [[Z2_FI]]{{.*}}load 8
; CHECK: [[Z2:%[0-9]+]]:_(s64) = G_LOAD [[Z2_FI]]{{.*}}load 8

; CHECK: [[Z3_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z3_ID]]
; CHECK: [[Z3_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z3_ID]]

; CHECK: [[Z3:%[0-9]+]]:_(s64) = G_LOAD [[Z3_FI]]{{.*}}load 8
; CHECK: [[Z3:%[0-9]+]]:_(s64) = G_LOAD [[Z3_FI]]{{.*}}load 8

; CHECK: [[IMPDEF:%[0-9]+]]:_(s192) = G_IMPLICIT_DEF

; CHECK: [[INS1:%[0-9]+]]:_(s192) = G_INSERT [[IMPDEF]], [[X0]](s64), 0

; CHECK: [[INS2:%[0-9]+]]:_(s192) = G_INSERT [[INS1]], [[X1]](s64), 64

; CHECK: [[INS3:%[0-9]+]]:_(s192) = G_INSERT [[INS2]], [[X2]](s64), 128

; CHECK: [[IMPDEF2:%[0-9]+]]:_(s96) = G_IMPLICIT_DEF

; CHECK: [[INS4:%[0-9]+]]:_(s96) = G_INSERT [[IMPDEF2]], [[Y0]](s32), 0

; CHECK: [[INS5:%[0-9]+]]:_(s96) = G_INSERT [[INS4]], [[Y1]](s32), 32

; CHECK: [[INS6:%[0-9]+]]:_(s96) = G_INSERT [[INS5]], [[Y2]](s32), 64

; CHECK: [[IMPDEF3:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF

; CHECK: [[INS7:%[0-9]+]]:_(s256) = G_INSERT [[IMPDEF3]], [[Z0]](s64), 0

; CHECK: [[INS8:%[0-9]+]]:_(s256) = G_INSERT [[INS7]], [[Z1]](s64), 64

; CHECK: [[INS9:%[0-9]+]]:_(s256) = G_INSERT [[INS8]], [[Z2]](s64), 128

; CHECK: [[INS10:%[0-9]+]]:_(s256) = G_INSERT [[INS9]], [[Z3]](s64), 192

; CHECK: ADJCALLSTACKDOWN 32, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: ADJCALLSTACKDOWN 32, 0, 14, $noreg, implicit-def $sp, implicit $sp

; CHECK: [[X0:%[0-9]+]]:_(s64), [[X1:%[0-9]+]]:_(s64), [[X2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[INS3]](s192)

; CHECK: [[Y0:%[0-9]+]]:_(s32), [[Y1:%[0-9]+]]:_(s32), [[Y2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS6]](s96)

; CHECK: [[Z0:%[0-9]+]]:_(s64), [[Z1:%[0-9]+]]:_(s64), [[Z2:%[0-9]+]]:_(s64), [[Z3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[INS10]](s256)

; CHECK: $d0 = COPY [[X0]](s64)
; CHECK: $d0 = COPY [[X0]](s64)

; CHECK: $d1 = COPY [[X1]](s64)
; CHECK: $d1 = COPY [[X1]](s64)

; CHECK: $d2 = COPY [[X2]](s64)
; CHECK: $d2 = COPY [[X2]](s64)

; CHECK: $s6 = COPY [[Y0]](s32)
; CHECK: $s6 = COPY [[Y0]](s32)

; CHECK: $s7 = COPY [[Y1]](s32)
; CHECK: $s7 = COPY [[Y1]](s32)

; CHECK: $s8 = COPY [[Y2]](s32)
; CHECK: $s8 = COPY [[Y2]](s32)

; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp

; CHECK: [[Z0_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[Z0_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0

; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1

; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r2

; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY $r3
; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY $r3

; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]

; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]

; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]

; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]

; CHECK: [[INS:%[0-9]+]]:_(s768) = G_INSERT {{.*}}, [[LAST_STACK_ELEMENT]](s32), 736

; CHECK: ADJCALLSTACKDOWN 80, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: ADJCALLSTACKDOWN 80, 0, 14, $noreg, implicit-def $sp, implicit $sp

; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS]](s768)

; CHECK: $r0 = COPY [[R0]]
; CHECK: $r0 = COPY [[R0]]

; CHECK: $r1 = COPY [[R1]]
; CHECK: $r1 = COPY [[R1]]

; CHECK: $r2 = COPY [[R2]]
; CHECK: $r2 = COPY [[R2]]

; CHECK: $r3 = COPY [[R3]]
; CHECK: $r3 = COPY [[R3]]

; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp

; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)
; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)

; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4
; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4

Show All 19 Lines



declare arm_aapcscc {i32, i32} @structs_target({i32, i32})
declare arm_aapcscc {i32, i32} @structs_target({i32, i32})




define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) {
define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) {

; CHECK-LABEL: test_structs
; CHECK-LABEL: test_structs

; CHECK: liveins: $r0, $r1
; CHECK: liveins: $r0, $r1

; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0

; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1

; CHECK: [[IMPDEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF

; CHECK: [[INS1:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF]], [[X0]](s32), 0

; CHECK: [[INS2:%[0-9]+]]:_(s64) = G_INSERT [[INS1]], [[X1]](s32), 32

; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp

; CHECK: [[X0:%[0-9]+]]:_(s32), [[X1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS2]](s64)

; CHECK-DAG: $r0 = COPY [[X0]](s32)
; CHECK-DAG: $r0 = COPY [[X0]](s32)

; CHECK-DAG: $r1 = COPY [[X1]](s32)
; CHECK-DAG: $r1 = COPY [[X1]](s32)

; ARM: BL @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
; ARM: BL @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1

; THUMB: tBL 14, $noreg, @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
; THUMB: tBL 14, $noreg, @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1

; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0

; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1

; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp

; CHECK: $r0 = COPY [[R0]](s32)
; CHECK: $r0 = COPY [[R0]](s32)

; CHECK: $r1 = COPY [[R1]](s32)
; CHECK: $r1 = COPY [[R1]](s32)

; ARM: BX_RET 14, $noreg, implicit $r0, implicit $r1
; ARM: BX_RET 14, $noreg, implicit $r0, implicit $r1

; THUMB: tBX_RET 14, $noreg, implicit $r0, implicit $r1
; THUMB: tBX_RET 14, $noreg, implicit $r0, implicit $r1

  %r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x)
  %r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x)

  ret {i32, i32} %r
  ret {i32, i32} %r

}
}