[AMDGPU] Fix for branch offset hardware workaround

[rtaylor]

Summary

This fixes a hardware bug that makes a branch offset of 0x3f unsafe.
This replaces the 32 bit branch with offset 0x3f to a 64 bit
instruction that includes the same 32 bit branch and the encoding
for a s_nop 0 to follow. The relaxer than modifies the offsets
accordingly.

Change-Id: I10b7aed99d651f8159401b01bb421f105fa6288e

[arsenm]

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

56–57 ↗

(On Diff #205334)

I would much rather avoid the proliferation of junk opcodes for this. Can you use a bundle or another way to add an independent nop instruction?

test/MC/AMDGPU/offsetbug.s

18–20 ↗

(On Diff #205334)

Can you use trivial instructions for sizes? I don't trust the size of most instructions to stay the same

82–83 ↗

(On Diff #205334)

Formatting

[arsenm]

lib/Target/AMDGPU/SOPInstructions.td

1011–1018 ↗

(On Diff #205334)

If the opcodes end up unavoidable, the class should be fixed to generate the branch and the dummy at the same time, rather than requiring repeating each definition with the opcode value

[rtaylor]

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

56–57 ↗

(On Diff #205334)

I'm not sure that's possible, relaxInstruction is return the MCInst Res but I can't say for sure as I've never worked with bundles and I'm not sure how the compiler treats them. I agree though that this would be more ideal than having new 64 bit instructions.

lib/Target/AMDGPU/SOPInstructions.td

1011–1018 ↗

(On Diff #205334)

I can have a look at doing this.

test/MC/AMDGPU/offsetbug.s

18–20 ↗

(On Diff #205334)

Yes, I can. I can make them nops.

82–83 ↗

(On Diff #205334)

Ah, missed this, thanks.

[rtaylor]

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

56–57 ↗

(On Diff #205334)

This would require a bundle to have a specific opcode, which from what I can see they do not.

[arsenm]

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

56–57 ↗

(On Diff #205334)

I'm not sure what you mean. There's one BUNDLE opcode, and then instructions following I are marked as in the bundle

[rampitec]

Can we have a disasm test? I want to see that we do not mess with decoding.

[rtaylor]

In D63494#1548719, @rampitec wrote:

Can we have a disasm test? I want to see that we do not mess with decoding.

Something other than the -disassemble checks?

[rampitec]

In D63494#1548974, @rtaylor wrote:

In D63494#1548719, @rampitec wrote:

Can we have a disasm test? I want to see that we do not mess with decoding.

Something other than the -disassemble checks?

Ah, missed it. Thanks, this is sufficient.

[rtaylor]

In D63494#1548986, @rampitec wrote:

In D63494#1548974, @rtaylor wrote:

In D63494#1548719, @rampitec wrote:

Can we have a disasm test? I want to see that we do not mess with decoding.

Something other than the -disassemble checks?

Ah, missed it. Thanks, this is sufficient.

Np. Ok, thanks.

[arsenm]

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

64 ↗

(On Diff #205334)

These names aren't good. I would prefer a sufficient like _pad_s_nop or something. 64 could mean many different things

[rampitec]

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

113 ↗

(On Diff #205334)

I'd suggest using a multiclass to define and InstrMapping instead of switches.

[rtaylor]

Changes per suggestions

[rtaylor]

lib/Target/AMDGPU/SOPInstructions.td

1011–1018 ↗

(On Diff #205334)

I don't think _Real is the best naming since there isn't a corresponding Pseudo but I had no clue what to call this multiclass so if anyone has a suggestion, I'm all ears.

[rampitec]

lib/Target/AMDGPU/SOPInstructions.td

972 ↗

(On Diff #205638)

SOPP_With_Relaxation maybe?

974 ↗

(On Diff #205638)

Can yo use InstrMapping mapping here to avoid switches?

[arsenm]

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

61 ↗

(On Diff #205638)

I would lowercase the suffix. The general naming convention its HARDWARE_NAME_compiler_defined_variant

[arsenm]

test/MC/AMDGPU/offsetbug.s

1–7 ↗

(On Diff #205638)

Can you split the test into separate files? I think there should be one function that needs 1 relaxation, another where the relaxation of one triggers the relaxation of the other, and another that triggers this twice

[rtaylor]

lib/Target/AMDGPU/SOPInstructions.td

974 ↗

(On Diff #205638)

Do you feel that this is worth it in this case? Seems overly complicated for a very specific use case but if it's the standard to go in this direction than ok.

[rampitec]

lib/Target/AMDGPU/SOPInstructions.td

1011–1018 ↗

(On Diff #205334)

_With_Relaxation?

974 ↗

(On Diff #205638)

You just get rid of one switch, so it is not that big deal now.

[rtaylor]

lib/Target/AMDGPU/SOPInstructions.td

974 ↗

(On Diff #205638)

That's ok, I've pretty much done it.

[rtaylor]

Suggested changes: Added InstrMapping. Three test files. Lower-cased suffixes for MI defs. Changed multiclass suffix.

[rampitec]

lib/Target/AMDGPU/SIInstrInfo.td

2316 ↗

(On Diff #205887)

I must be missing something, but how does it work? You are passing the same asm string into the both versions. What do you map to what then?

test/MC/AMDGPU/offsetbug_once.s

9 ↗

(On Diff #205887)

Indent.

test/MC/AMDGPU/offsetbug_one_and_one.s

78 ↗

(On Diff #205887)

Indent.

test/MC/AMDGPU/offsetbug_twice.s

112 ↗

(On Diff #205887)

And indent ;)

[rtaylor]

Fixed idents.

[rtaylor]

lib/Target/AMDGPU/SIInstrInfo.td

2316 ↗

(On Diff #205887)

The asm string is the same for both, the s_nop is added in at encoding. I'm using the Size field, 4 maps to 8.

This is quite similar to how VOP is doing in during getVOPe32 and get VOPe64, the difference is that they also use a VOP3 flag but it's not needed here. Here, if you notice I am just adding the s_nop in class SOPP64e.

[rampitec]

LGTM, except one indent.

lib/Target/AMDGPU/SIInstrInfo.td

2316 ↗

(On Diff #205887)

Got it, thanks!

test/MC/AMDGPU/offsetbug_once.s

9 ↗

(On Diff #205911)

Another indent.

[arsenm]

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

10 ↗

(On Diff #205911)

This is a layering violation

73–76 ↗

(On Diff #205911)

return test();

[arsenm]

lib/Target/AMDGPU/SOPInstructions.td

943–945 ↗

(On Diff #205911)

I don't understand how this gets you a nop?

948 ↗

(On Diff #205911)

SOPP_w_nop or something? The current naming sounds like an actually different encoding (same with SOPPe64)

[rampitec]

lib/Target/AMDGPU/SOPInstructions.td

943–945 ↗

(On Diff #205911)

I guess s_nop opcode is 0, simm is 0 and SOPP encoding is 0x17f.
Maybe it would be more readable to write something like:

let Inst{63-55} = S_NOP.Inst{31-23}; // encoding
let Inst{54-48} = S_NOP.Inst{22-16}; // opcode

[rtaylor]

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

10 ↗

(On Diff #205911)

Where would you like the InstrMapping to go? The others are here.

[rtaylor]

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

10 ↗

(On Diff #205911)

I suppose I could put it into Utils/AMDGPUBaseInfo.h which is already included in AMDGPUAsmBackend.cpp.... though that seems at first glance to also be a layering violation. Maybe it would be better if this was a mapping table, it would fit into AMDGPUBaseInfo.h but I think InstrMapping is more fitting.

73–76 ↗

(On Diff #205911)

Not sure what you mean here though the else is useless, so I'll remove that and just return false.

lib/Target/AMDGPU/SOPInstructions.td

943–945 ↗

(On Diff #205911)

Yes, the opcode for s_nop is 0. The value I'm using is 0 and the encoding I had is the same as everywhere else but I can see how this makes it more understandable... maybe a simple comment here would help? I fixed this but it just makes tablegen less readable honestly, since now the S_NOP def has to go after the SOPP class but before the SOPP_w_nop encoding, so it's all alone among classes. Am I missing something? Prototyping would work but again, make everything less readable.

948 ↗

(On Diff #205911)

Sure, that's fine.

test/MC/AMDGPU/offsetbug_once.s

9 ↗

(On Diff #205911)

Thanks.

[rtaylor]

Fixed suggestions

[arsenm]

LGTM

llvm/trunk/lib/Target/AMDGPU/AMDGPU.td

 >;
 
 def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
   "HasFlatSegmentOffsetBug",
   "true",
   "GFX10 bug, inst_offset ignored in flat segment"
 >;
 
+def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
+  "HasOffset3fBug",
+  "true",
+  "Branch offset of 3f hardware bug"
+>;
+
 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
   "ldsbankcount"#Value,
   "LDSBankCount",
   !cast<string>(Value),
   "The number of LDS banks per compute unit."
 >;
 
 def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
def FeatureGroup {
   list<SubtargetFeature> GFX10_1_Bugs = [
     FeatureVcmpxPermlaneHazard,
     FeatureVMEMtoScalarWriteHazard,
     FeatureSMEMtoVectorWriteHazard,
     FeatureInstFwdPrefetchBug,
     FeatureVcmpxExecWARHazard,
     FeatureLdsBranchVmemWARHazard,
     FeatureNSAtoVMEMBug,
+    FeatureOffset3fBug,
     FeatureFlatSegmentOffsetBug
    ];
 }
 
 def FeatureISAVersion10_1_0 : FeatureSet<
   !listconcat(FeatureGroup.GFX10_1_Bugs,
     [FeatureGFX10,
      FeatureLDSBankCount32,
def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
   AssemblerPredicate<"FeatureDot2Insts">;
 
 def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
   AssemblerPredicate<"FeatureDot5Insts">;
 
 def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
   AssemblerPredicate<"FeatureDot6Insts">;
 
+def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
+  AssemblerPredicate<"FeatureOffset3fBug">;
+
 def EnableLateCFGStructurize : Predicate<
   "EnableLateStructurizeCFG">;
 
 // Include AMDGPU TD files
 include "SISchedule.td"
 include "GCNProcessors.td"
 include "AMDGPUInstrInfo.td"
 include "AMDGPURegisterInfo.td"
 include "AMDGPURegisterBanks.td"
 include "AMDGPUInstructions.td"
 include "SIInstrInfo.td"
 include "AMDGPUCallingConv.td"
 include "AMDGPUSearchableTables.td"

llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h

protected:
 
   bool HasVcmpxPermlaneHazard;
   bool HasVMEMtoScalarWriteHazard;
   bool HasSMEMtoVectorWriteHazard;
   bool HasInstFwdPrefetchBug;
   bool HasVcmpxExecWARHazard;
   bool HasLdsBranchVmemWARHazard;
   bool HasNSAtoVMEMBug;
+  bool HasOffset3fBug;
   bool HasFlatSegmentOffsetBug;
 
   // Dummy feature to use for assembler in tablegen.
   bool FeatureDisable;
 
   SelectionDAGTargetInfo TSInfo;
 private:
   SIInstrInfo InstrInfo;
public:
   bool hasDPP8() const {
     return HasDPP8;
   }
 
   bool hasR128A16() const {
     return HasR128A16;
   }
 
+  bool hasOffset3fBug() const {
+    return HasOffset3fBug;
+  }
+
   bool hasNSAEncoding() const {
     return HasNSAEncoding;
   }
 
   bool hasMadF16() const;
 
   bool enableSIScheduler() const {
     return EnableSIScheduler;

llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
 
     HasVcmpxPermlaneHazard(false),
     HasVMEMtoScalarWriteHazard(false),
     HasSMEMtoVectorWriteHazard(false),
     HasInstFwdPrefetchBug(false),
     HasVcmpxExecWARHazard(false),
     HasLdsBranchVmemWARHazard(false),
     HasNSAtoVMEMBug(false),
+    HasOffset3fBug(false),
     HasFlatSegmentOffsetBug(false),
 
     FeatureDisable(false),
     InstrInfo(initializeSubtargetDependencies(TT, GPU, FS)),
     TLInfo(TM, *this),
     FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0) {
   CallLoweringInfo.reset(new AMDGPUCallLowering(*getTargetLowering()));
   Legalizer.reset(new AMDGPULegalizerInfo(*this, TM));

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

public:
   unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
 
   void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                   const MCValue &Target, MutableArrayRef<char> Data,
                   uint64_t Value, bool IsResolved,
                   const MCSubtargetInfo *STI) const override;
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
-                            const MCAsmLayout &Layout) const override {
-    return false;
-  }
+                            const MCAsmLayout &Layout) const override;
+
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
-                        MCInst &Res) const override {
-    llvm_unreachable("Not implemented");
-  }
+                        MCInst &Res) const override;
+
   bool mayNeedRelaxation(const MCInst &Inst,
-                         const MCSubtargetInfo &STI) const override {
-    return false;
-  }
+                         const MCSubtargetInfo &STI) const override;
 
   unsigned getMinimumNopSize() const override;
   bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
 };
 
 } //End anonymous namespace
 
+void AMDGPUAsmBackend::relaxInstruction(const MCInst &Inst,
+                                        const MCSubtargetInfo &STI,
+                                        MCInst &Res) const {
+  unsigned RelaxedOpcode = AMDGPU::getSOPPWithRelaxation(Inst.getOpcode());
+  Res.setOpcode(RelaxedOpcode);
+  Res.addOperand(Inst.getOperand(0));
+  return;
+}
+
+bool AMDGPUAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
+                                            uint64_t Value,
+                                            const MCRelaxableFragment *DF,
+                                            const MCAsmLayout &Layout) const {
+  // if the branch target has an offset of x3f this needs to be relaxed to
+  // add a s_nop 0 immediately after branch to effectively increment offset
+  // for hardware workaround in gfx1010
+  return (((int64_t(Value)/4)-1) == 0x3f);
+}
+
+bool AMDGPUAsmBackend::mayNeedRelaxation(const MCInst &Inst,
+                       const MCSubtargetInfo &STI) const {
+  if (!STI.getFeatureBits()[AMDGPU::FeatureOffset3fBug])
+    return false;
+
+  if (AMDGPU::getSOPPWithRelaxation(Inst.getOpcode()) >= 0)
+    return true;
+
+  return false;
+}
+
 static unsigned getFixupKindNumBytes(unsigned Kind) {
   switch (Kind) {
   case AMDGPU::fixup_si_sopp_br:
     return 2;
   case FK_SecRel_1:
   case FK_Data_1:
     return 1;
   case FK_SecRel_2:

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

 def getVCMPXNoSDstOp : InstrMapping {
   let FilterClass = "VCMPXNoSDstTable";
   let RowFields = ["NoSDstOp"];
   let ColFields = ["HasSDst"];
   let KeyCol = ["1"];
   let ValueCols = [["0"]];
 }
 
+// Maps a SOPP to a SOPP with S_NOP
+def getSOPPWithRelaxation : InstrMapping {
+  let FilterClass = "Base_SOPP";
+  let RowFields = ["AsmString"];
+  let ColFields = ["Size"];
+  let KeyCol = ["4"];
+  let ValueCols = [["8"]];
+}
+
 include "SIInstructions.td"
 
 include "DSInstructions.td"
 include "MIMGInstructions.td"

llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td

def S_SET_GPR_IDX_ON : SOPC <0x11,
   let FixedSize = 1;
 }
 }
 
 //===----------------------------------------------------------------------===//
 // SOPP Instructions
 //===----------------------------------------------------------------------===//
 
+class Base_SOPP <string asm> {
+  string AsmString = asm;
+}
+
 class SOPPe <bits<7> op> : Enc32 {
   bits <16> simm16;
 
   let Inst{15-0} = simm16;
   let Inst{22-16} = op;
   let Inst{31-23} = 0x17f; // encoding
 }
 
 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
-  InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
+  InstSI <(outs), ins, asm, pattern >, SOPPe <op>, Base_SOPP <asm> {
 
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let SALU = 1;
   let SOPP = 1;
   let Size = 4;
   let SchedRW = [WriteSALU];
 
   let UseNamedOperandTable = 1;
 }
 
-
 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
 
+class SOPP_w_nop_e <bits<7> op> : Enc64 {
+  bits <16> simm16;
+
+  let Inst{15-0} = simm16;
+  let Inst{22-16} = op;
+  let Inst{31-23} = 0x17f; // encoding
+  let Inst{47-32} = 0x0;
+  let Inst{54-48} = S_NOP.Inst{22-16}; // opcode
+  let Inst{63-55} = S_NOP.Inst{31-23}; // encoding
+}
+
+class SOPP_w_nop <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
+  InstSI <(outs), ins, asm, pattern >, SOPP_w_nop_e <op>, Base_SOPP <asm> {
+
+  let mayLoad = 0;
+  let mayStore = 0;
+  let hasSideEffects = 0;
+  let SALU = 1;
+  let SOPP = 1;
+  let Size = 8;
+  let SchedRW = [WriteSALU];
+
+  let UseNamedOperandTable = 1;
+}
+
+multiclass SOPP_With_Relaxation <bits<7> op, dag ins, string asm, list<dag> pattern = []> {
+  def "" : SOPP <op, ins, asm, pattern>;
+  def _pad_s_nop : SOPP_w_nop <op, ins, asm, pattern>;
+}
+
 let isTerminator = 1 in {
 
 def S_ENDPGM : SOPP <0x00000001, (ins EndpgmImm:$simm16), "s_endpgm$simm16"> {
   let isBarrier = 1;
   let isReturn = 1;
 }
 
 def S_ENDPGM_SAVED : SOPP <0x0000001B, (ins), "s_endpgm_saved"> {

 let SubtargetPredicate = isGFX10Plus in {
   let isBarrier = 1, isReturn = 1, simm16 = 0 in {
     def S_CODE_END :
       SOPP<0x01f, (ins), "s_code_end">;
   } // End isBarrier = 1, isReturn = 1, simm16 = 0
 } // End SubtargetPredicate = isGFX10Plus
 
 let isBranch = 1, SchedRW = [WriteBranch] in {
-def S_BRANCH : SOPP <
+let isBarrier = 1 in {
+defm S_BRANCH : SOPP_With_Relaxation <
   0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16",
-  [(br bb:$simm16)]> {
-  let isBarrier = 1;
+  [(br bb:$simm16)]>;
 }
 
 let Uses = [SCC] in {
-def S_CBRANCH_SCC0 : SOPP <
+defm S_CBRANCH_SCC0 : SOPP_With_Relaxation <
   0x00000004, (ins sopp_brtarget:$simm16),
   "s_cbranch_scc0 $simm16"
 >;
-def S_CBRANCH_SCC1 : SOPP <
+defm S_CBRANCH_SCC1 : SOPP_With_Relaxation <
   0x00000005, (ins sopp_brtarget:$simm16),
   "s_cbranch_scc1 $simm16"
 >;
 } // End Uses = [SCC]
 
 let Uses = [VCC] in {
-def S_CBRANCH_VCCZ : SOPP <
+defm S_CBRANCH_VCCZ : SOPP_With_Relaxation <
   0x00000006, (ins sopp_brtarget:$simm16),
   "s_cbranch_vccz $simm16"
 >;
-def S_CBRANCH_VCCNZ : SOPP <
+defm S_CBRANCH_VCCNZ : SOPP_With_Relaxation <
   0x00000007, (ins sopp_brtarget:$simm16),
   "s_cbranch_vccnz $simm16"
 >;
 } // End Uses = [VCC]
 
 let Uses = [EXEC] in {
-def S_CBRANCH_EXECZ : SOPP <
+defm S_CBRANCH_EXECZ : SOPP_With_Relaxation <
   0x00000008, (ins sopp_brtarget:$simm16),
   "s_cbranch_execz $simm16"
 >;
-def S_CBRANCH_EXECNZ : SOPP <
+defm S_CBRANCH_EXECNZ : SOPP_With_Relaxation <
   0x00000009, (ins sopp_brtarget:$simm16),
   "s_cbranch_execnz $simm16"
 >;
 } // End Uses = [EXEC]
 
-def S_CBRANCH_CDBGSYS : SOPP <
+defm S_CBRANCH_CDBGSYS : SOPP_With_Relaxation <
   0x00000017, (ins sopp_brtarget:$simm16),
   "s_cbranch_cdbgsys $simm16"
 >;
 
-def S_CBRANCH_CDBGSYS_AND_USER : SOPP <
+defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_With_Relaxation <
   0x0000001A, (ins sopp_brtarget:$simm16),
   "s_cbranch_cdbgsys_and_user $simm16"
 >;
 
-def S_CBRANCH_CDBGSYS_OR_USER : SOPP <
+defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_With_Relaxation <
   0x00000019, (ins sopp_brtarget:$simm16),
   "s_cbranch_cdbgsys_or_user $simm16"
 >;
 
-def S_CBRANCH_CDBGUSER : SOPP <
+defm S_CBRANCH_CDBGUSER : SOPP_With_Relaxation <
   0x00000018, (ins sopp_brtarget:$simm16),
   "s_cbranch_cdbguser $simm16"
 >;
 
 } // End isBranch = 1
 } // End isTerminator = 1
 
 let hasSideEffects = 1 in {

llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
                           Optional<bool> EnableWavefrontSize32 = None);
 
 } // end namespace IsaInfo
 
 LLVM_READONLY
 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
 
+LLVM_READONLY
+int getSOPPWithRelaxation(uint16_t Opcode);
+
 struct MIMGBaseOpcodeInfo {
   MIMGBaseOpcode BaseOpcode;
   bool Store;
   bool Atomic;
   bool AtomicX2;
   bool Sampler;
   bool Gather4;
 

llvm/trunk/test/MC/AMDGPU/offsetbug_once.s

+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -disassemble -mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
+  s_getpc_b64 s[0:1]
+  s_cbranch_vccnz BB0_1
+// GFX10: s_cbranch_vccnz BB0_1           ; encoding: [A,A,0x87,0xbf]
+// GFX10-NEXT: ;   fixup A - offset: 0, value: BB0_1, kind: fixup_si_sopp_br
+// BIN: s_cbranch_vccnz BB0_1 // 000000000004: BF870040
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+BB0_1:
+  s_nop 0
+  s_endpgm

llvm/trunk/test/MC/AMDGPU/offsetbug_one_and_one.s

+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -disassemble -mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
+  s_getpc_b64 s[0:1]
+  s_cbranch_vccnz BB0_1
+// GFX10: s_cbranch_vccnz BB0_1           ; encoding: [A,A,0x87,0xbf]
+// GFX10-NEXT: ;   fixup A - offset: 0, value: BB0_1, kind: fixup_si_sopp_br
+// BIN: s_cbranch_vccnz BB0_1 // 000000000004: BF870041
+  s_cbranch_execz BB0_3
+// GFX10: s_cbranch_execz BB0_3           ; encoding: [A,A,0x88,0xbf]
+// GFX10-NEXT: ;   fixup A - offset: 0, value: BB0_3, kind: fixup_si_sopp_br
+// BIN: s_cbranch_execz BB0_3 // 00000000000C: BF880040
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+BB0_1:
+  s_nop 0
+BB0_3:
+  s_nop 0
+  s_endpgm

llvm/trunk/test/MC/AMDGPU/offsetbug_twice.s

+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -disassemble -mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
+  s_getpc_b64 s[0:1]
+  s_cbranch_vccnz BB0_2
+// GFX10: s_cbranch_vccnz BB0_2           ; encoding: [A,A,0x87,0xbf]
+// GFX10-NEXT: ;   fixup A - offset: 0, value: BB0_2, kind: fixup_si_sopp_br
+// BIN: s_cbranch_vccnz BB0_2 // 000000000004: BF870061
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  v_nop
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_cbranch_vccnz BB0_1
+// GFX10: s_cbranch_vccnz BB0_1           ; encoding: [A,A,0x87,0xbf]
+// GFX10-NEXT: ;   fixup A - offset: 0, value: BB0_1, kind: fixup_si_sopp_br
+// BIN: s_cbranch_vccnz BB0_1 // 000000000064: BF870041
+  s_nop 0
+  s_cbranch_execz BB0_3
+// GFX10: s_cbranch_execz BB0_3           ; encoding: [A,A,0x88,0xbf]
+// GFX10-NEXT: ;   fixup A - offset: 0, value: BB0_3, kind: fixup_si_sopp_br
+// BIN: s_cbranch_execz BB0_3 // 00000000006C: BF880040
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_nop 0
+BB0_1:
+  s_nop 0
+BB0_3:
+  s_nop 0
+  s_nop 0
+  s_nop 0
+  s_cbranch_vccnz BB0_2
+// GFX10: s_cbranch_vccnz BB0_2           ; encoding: [A,A,0x87,0xbf]
+// GFX10-NEXT: ;   fixup A - offset: 0, value: BB0_2, kind: fixup_si_sopp_br
+// BIN: s_cbranch_vccnz BB0_2 // 00000000017C: BF870003
+  s_nop 0
+  s_nop 0
+  s_nop 0
+BB0_2:
+  s_nop 0
+  s_nop 0
+  s_endpgm