WIP: AMDGPU: Use fixup for local linkage functions

[dp]

I contemplate if adding a 'proxy' instruction like s_add_u64 would help.
Code emitter would expand it into s_add+s_addc and handle relocations.
Assembly output would look like this:

s_add_u64 s[0:1], s[2:3], func
func:
  ...

encoding: [0x02,0xff,0x00,0x80,A,A,A,A,0x03,0xff,0x01,0x82,B,B,B,B]
          ;   fixup A - offset: 4, value: func, kind: FK_PCRel_4
          ;   fixup B - offset: 12, value: func, kind: fixup_si_pcrel_hi32
          ; <MCInst #10668 S_ADD_U64_gfx10
          ;  <MCOperand Reg:1832>
          ;  <MCOperand Reg:1833>
          ;  <MCOperand Expr:(func)>>

The code after relocation would be:

s_add_u32 s0, s2, 12              // 000000000028: 8000FF02 0000000C
s_addc_u32 s1, s3, 0              // 000000000030: 8201FF03 00000000
0000000000000038 func:
...

Advantages:

• AMDGPUMCExpr.* are not needed;
• no needsPCRel changes;
• cleaner relocation handling;
• cleaner codegen logic.

Disadvantages:

• some hacks in SIMCCodeEmitter for proxy replacement.

Would this be useful?

[arsenm]

I don’t want to use a pseudo instruction for this. We don’t need just add. We at least need sub, and there will be other possible users in the future

[hliao]

lib/Target/AMDGPU/AMDGPUMCInstLower.cpp

156

Why not use MCBinaryExpr::createAShr to shift that high bits into low bits directly? We don't need invent a new target fixup.

[arsenm]

lib/Target/AMDGPU/AMDGPUMCInstLower.cpp

156

That might work. Do we need an explicit truncate from 64-bit to 32-bit operator though?

lib/Target/AMDGPU/AMDGPUMCInstLower.cpp

 //
 //===----------------------------------------------------------------------===//
 //
 
 #include "AMDGPUAsmPrinter.h"
 #include "AMDGPUSubtarget.h"
 #include "AMDGPUTargetMachine.h"
 #include "MCTargetDesc/AMDGPUInstPrinter.h"
+#include "MCTargetDesc/AMDGPUMCExpr.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "R600AsmPrinter.h"
 #include "SIInstrInfo.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/GlobalVariable.h"
bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
   }
   case MachineOperand::MO_GlobalAddress: {
     const GlobalValue *GV = MO.getGlobal();
     SmallString<128> SymbolName;
     AP.getNameWithPrefix(SymbolName, GV);
     MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
     const MCExpr *SymExpr =
       MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx);
-    const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr,
-      MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
+    const MCExpr *Expr = MCBinaryExpr::createAdd(
+      SymExpr, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
+
+    if (MO.getTargetFlags() == SIInstrInfo::MO_PCREL32_HI)
+      Expr = AMDGPUMCExpr::create(AMDGPUMCExpr::VK_AMDGPU_PCREL_HI32, Expr, Ctx);
+
     MCOp = MCOperand::createExpr(Expr);
     return true;
   }
   case MachineOperand::MO_ExternalSymbol: {
     MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
     Sym->setExternal(true);
     const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
     MCOp = MCOperand::createExpr(Expr);

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

static unsigned getFixupKindNumBytes(unsigned Kind) {
   case FK_Data_1:
     return 1;
   case FK_SecRel_2:
   case FK_Data_2:
     return 2;
   case FK_SecRel_4:
   case FK_Data_4:
   case FK_PCRel_4:
+  case AMDGPU::fixup_si_pcrel_hi32:
     return 4;
   case FK_SecRel_8:
   case FK_Data_8:
     return 8;
   default:
     llvm_unreachable("Unknown fixup kind!");
   }
 }
 
 static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
                                  MCContext *Ctx) {
   int64_t SignedValue = static_cast<int64_t>(Value);
 
   switch (static_cast<unsigned>(Fixup.getKind())) {
   case AMDGPU::fixup_si_sopp_br: {
     int64_t BrImm = (SignedValue - 4) / 4;
 
     if (Ctx && !isInt<16>(BrImm))
       Ctx->reportError(Fixup.getLoc(), "branch size exceeds simm16");
 
     return BrImm;
   }
+  case AMDGPU::fixup_si_pcrel_hi32: {
+    return Value >> 32;
+  }
   case FK_Data_1:
   case FK_Data_2:
   case FK_Data_4:
   case FK_Data_8:
   case FK_PCRel_4:
   case FK_SecRel_4:
     return Value;
   default:
for (unsigned i = 0; i != NumBytes; ++i)
     Data[Offset + i] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff);
 }
 
 const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
                                                        MCFixupKind Kind) const {
   const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
     // name                   offset bits  flags
     { "fixup_si_sopp_br",     0,     16,   MCFixupKindInfo::FKF_IsPCRel },
+    { "fixup_si_pcrel_hi32",  0,     32,   MCFixupKindInfo::FKF_IsPCRel }
   };
 
   if (Kind < FirstTargetFixupKind)
     return MCAsmBackend::getFixupKindInfo(Kind);
 
   return Infos[Kind - FirstTargetFixupKind];
 }
 

lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp

 //===- AMDGPUELFObjectWriter.cpp - AMDGPU ELF Writer ----------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUMCTargetDesc.h"
+#include "AMDGPUFixupKinds.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCFixup.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/MCValue.h"
 #include "llvm/Support/ErrorHandling.h"
unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
   case MCSymbolRefExpr::VK_AMDGPU_REL32_LO:
     return ELF::R_AMDGPU_REL32_LO;
   case MCSymbolRefExpr::VK_AMDGPU_REL32_HI:
     return ELF::R_AMDGPU_REL32_HI;
   case MCSymbolRefExpr::VK_AMDGPU_REL64:
     return ELF::R_AMDGPU_REL64;
   }
 
-  switch (Fixup.getKind()) {
+  switch ((unsigned)Fixup.getKind()) {
   default: break;
   case FK_PCRel_4:
+  case AMDGPU::fixup_si_pcrel_hi32:
     return ELF::R_AMDGPU_REL32;
   case FK_Data_4:
   case FK_SecRel_4:
     return ELF::R_AMDGPU_ABS32;
   case FK_Data_8:
     return ELF::R_AMDGPU_ABS64;
   }
 

lib/Target/AMDGPU/MCTargetDesc/AMDGPUFixupKinds.h

 #include "llvm/MC/MCFixup.h"
 
 namespace llvm {
 namespace AMDGPU {
 enum Fixups {
   /// 16-bit PC relative fixup for SOPP branch instructions.
   fixup_si_sopp_br = FirstTargetFixupKind,
 
+  // Extract the high 32-bits of a 64-bit PC relative value.
+  fixup_si_pcrel_hi32,
+
   // Marker
   LastTargetFixupKind,
   NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
 };
 }
 }
 
 #endif

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h

+//===-- AMDGPUMCExpr.h - AMDGPU specific MC expression classes --*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_LANAIMCEXPR_H
+#define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_LANAIMCEXPR_H
+
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCValue.h"
+
+namespace llvm {
+
+class AMDGPUMCExpr : public MCTargetExpr {
+public:
+  enum VariantKind {
+    VK_AMDGPU_None,
+    VK_AMDGPU_PCREL_HI32
+  };
+
+protected:
+  explicit AMDGPUMCExpr(VariantKind Kind, const MCExpr *Expr)
+    : Kind(Kind), Expr(Expr) {}
+
+  ~AMDGPUMCExpr() = default;
+
+private:
+  const VariantKind Kind;
+  const MCExpr *Expr;
+
+public:
+  static const AMDGPUMCExpr *create(VariantKind Kind, const MCExpr *Expr,
+                                    MCContext &Ctx);
+
+  // Returns the kind of this expression.
+  VariantKind getKind() const { return Kind; }
+
+  // Returns the child of this expression.
+  const MCExpr *getSubExpr() const { return Expr; }
+
+  void printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const override;
+  void visitUsedExpr(MCStreamer &Streamer) const override;
+
+  bool evaluateAsRelocatableImpl(MCValue &Res,
+                                 const MCAsmLayout *Layout,
+                                 const MCFixup *Fixup) const override;
+
+  MCFragment *findAssociatedFragment() const override {
+    llvm_unreachable("not implemented");
+  }
+
+  void fixELFSymbolsInTLSFixups(MCAssembler &) const override {
+    // No TLS symbols to handle
+  }
+};
+
+
+} // end namespace llvm
+
+#endif

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp

+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPUMCExpr.h"
+#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCStreamer.h"
+using namespace llvm;
+
+
+const AMDGPUMCExpr *AMDGPUMCExpr::create(VariantKind Kind, const MCExpr *Expr,
+                                         MCContext &Ctx) {
+  return new (Ctx) AMDGPUMCExpr(Kind, Expr);
+}
+
+void AMDGPUMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
+  if (Kind == VK_AMDGPU_None) {
+    Expr->print(OS, MAI);
+    return;
+  }
+
+  switch (Kind) {
+  case VK_AMDGPU_PCREL_HI32:
+    OS << "hi32";
+    break;
+  default:
+    llvm_unreachable("Invalid kind!");
+  }
+
+  OS << '(';
+  const MCExpr *Expr = getSubExpr();
+  Expr->print(OS, MAI);
+  OS << ')';
+}
+
+void AMDGPUMCExpr::visitUsedExpr(MCStreamer &Streamer) const {
+  Streamer.visitUsedExpr(*getSubExpr());
+}
+
+bool AMDGPUMCExpr::evaluateAsRelocatableImpl(MCValue &Res,
+                                             const MCAsmLayout *Layout,
+                                             const MCFixup *Fixup) const {
+  if (!getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup))
+    return false;
+
+  Res =
+    MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(), getKind());
+
+  return true;
+}

lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMAMDGPUDesc
   AMDGPUAsmBackend.cpp
   AMDGPUELFObjectWriter.cpp
   AMDGPUELFStreamer.cpp
   AMDGPUInstPrinter.cpp
   AMDGPUMCAsmInfo.cpp
   AMDGPUMCCodeEmitter.cpp
+  AMDGPUMCExpr.cpp
   AMDGPUMCTargetDesc.cpp
   AMDGPUTargetStreamer.cpp
   R600MCCodeEmitter.cpp
   R600MCTargetDesc.cpp
   SIMCCodeEmitter.cpp
 )
 
 add_dependencies(LLVMAMDGPUDesc LLVMAMDGPUUtils)

lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

 /// The SI code emitter produces machine code that can be executed
 /// directly on the GPU device.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPU.h"
 #include "MCTargetDesc/AMDGPUFixupKinds.h"
 #include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
+#include "MCTargetDesc/AMDGPUMCExpr.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "SIDefines.h"
 #include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCFixup.h"
 #include "llvm/MC/MCInst.h"
SIMCCodeEmitter::getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
   if (Reg != AMDGPU::VCC) {
     RegEnc |= MRI.getEncodingValue(Reg);
     RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
     RegEnc |= SDWA9EncValues::VOPC_DST_VCC_MASK;
   }
   return RegEnc;
 }
 
-static bool needsPCRel(const MCExpr *Expr) {
+static bool needsPCRel(const MCExpr *Expr, bool &IsHi) {
   switch (Expr->getKind()) {
-  case MCExpr::SymbolRef:
+  case MCExpr::SymbolRef: {
     return true;
+  }
   case MCExpr::Binary: {
     auto *BE = cast<MCBinaryExpr>(Expr);
     if (BE->getOpcode() == MCBinaryExpr::Sub)
       return false;
-    return needsPCRel(BE->getLHS()) || needsPCRel(BE->getRHS());
+    return needsPCRel(BE->getLHS(), IsHi) || needsPCRel(BE->getRHS(), IsHi);
   }
   case MCExpr::Unary:
-    return needsPCRel(cast<MCUnaryExpr>(Expr)->getSubExpr());
-  case MCExpr::Target:
+    return needsPCRel(cast<MCUnaryExpr>(Expr)->getSubExpr(), IsHi);
+  case MCExpr::Target: {
+    assert(cast<AMDGPUMCExpr>(Expr)->getKind() == AMDGPUMCExpr::VK_AMDGPU_PCREL_HI32);
+    IsHi = true;
+    return true;
+  }
   case MCExpr::Constant:
     return false;
   }
   llvm_unreachable("invalid kind");
 }
 
 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
                                             const MCOperand &MO,
if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) {
     //
     //    s_add_u32 s2, s2, (extern_const_addrspace+16
     //
     // And expecting a PCRel should instead produce
     //
     // .Ltmp1:
     //   s_add_u32 s2, s2, (extern_const_addrspace+16)-.Ltmp1
     MCFixupKind Kind;
-    if (needsPCRel(MO.getExpr()))
-      Kind = FK_PCRel_4;
-    else
+    bool IsHi = false;
+
+    if (needsPCRel(MO.getExpr(), IsHi)) {
+      Kind = IsHi ? (MCFixupKind)AMDGPU::fixup_si_pcrel_hi32 : FK_PCRel_4;
+    } else
       Kind = FK_Data_4;
 
     const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
     uint32_t Offset = Desc.getSize();
     assert(Offset == 4 || Offset == 8);
 
     Fixups.push_back(
       MCFixup::create(Offset, MO.getExpr(), Kind, MI.getLoc()));

lib/Target/AMDGPU/SIISelLowering.cpp

unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
   }
 
   // break, if_break, else_break are all only used as inputs to loop, not
   // directly as branch conditions.
   return 0;
 }
 
 bool SITargetLowering::shouldEmitFixup(const GlobalValue *GV) const {
+  if (GV->getValueType()->isFunctionTy() && GV->hasLocalLinkage())
+    return true;
+
   const Triple &TT = getTargetMachine().getTargetTriple();
   return (GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
           GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
          AMDGPU::shouldEmitConstantsToTextSection(TT);
 }
 
 bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {
   // FIXME: Either avoid relying on address space here or change the default
if (GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
       GSD->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS)
     return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
 
   SDLoc DL(GSD);
   EVT PtrVT = Op.getValueType();
 
   // FIXME: Should not make address space based decisions here.
   if (shouldEmitFixup(GV))
-    return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT);
+    return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT,
+                                   SIInstrInfo::MO_PCREL32_LO);
   else if (shouldEmitPCReloc(GV))
     return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT,
-                                   SIInstrInfo::MO_REL32);
+                                   SIInstrInfo::MO_REL32_LO);
 
   SDValue GOTAddr = buildPCRelGlobalAddress(DAG, GV, DL, 0, PtrVT,
-                                            SIInstrInfo::MO_GOTPCREL32);
+                                            SIInstrInfo::MO_GOTPCREL32_LO);
 
   Type *Ty = PtrVT.getTypeForEVT(*DAG.getContext());
   PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
   const DataLayout &DataLayout = DAG.getDataLayout();
   unsigned Align = DataLayout.getABITypeAlignment(PtrTy);
   MachinePointerInfo PtrInfo
     = MachinePointerInfo::getGOT(DAG.getMachineFunction());
 

lib/Target/AMDGPU/SIInstrInfo.h

protected:
   bool swapSourceModifiers(MachineInstr &MI,
                            MachineOperand &Src0, unsigned Src0OpName,
                            MachineOperand &Src1, unsigned Src1OpName) const;
 
   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
                                        unsigned OpIdx0,
                                        unsigned OpIdx1) const override;
 
  public:
   enum TargetOperandFlags {
-    MO_MASK = 0x7,
+    MO_MASK = 0xf,
 
     MO_NONE = 0,
+
+    // PC relative, lo, hi.
+    MO_PCREL32_LO = 1,
+    MO_PCREL32_HI = 2,
+
     // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
-    MO_GOTPCREL = 1,
+    MO_GOTPCREL = 3,
+
     // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
-    MO_GOTPCREL32 = 2,
-    MO_GOTPCREL32_LO = 2,
+    MO_GOTPCREL32 = 4,
+    MO_GOTPCREL32_LO = 5,
+
     // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
-    MO_GOTPCREL32_HI = 3,
+    MO_GOTPCREL32_HI = 6,
+
+
     // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
-    MO_REL32 = 4,
-    MO_REL32_LO = 4,
+    MO_REL32 = 7,
+    MO_REL32_LO = 7,
+
     // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
-    MO_REL32_HI = 5,
+    MO_REL32_HI = 8,
 
-    MO_LONG_BRANCH_FORWARD = 6,
-    MO_LONG_BRANCH_BACKWARD = 7
+    MO_LONG_BRANCH_FORWARD = 9,
+    MO_LONG_BRANCH_BACKWARD = 10
   };
 
   explicit SIInstrInfo(const GCNSubtarget &ST);
 
   const SIRegisterInfo &getRegisterInfo() const {
     return RI;
   }
 

lib/Target/AMDGPU/SIInstrInfo.cpp

case AMDGPU::SI_PC_ADD_REL_OFFSET: {
     // Add 32-bit offset from this instruction to the start of the
     // constant data.
     Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo)
                        .addReg(RegLo)
                        .add(MI.getOperand(1)));
 
     MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi)
                                   .addReg(RegHi);
-    if (MI.getOperand(2).getTargetFlags() == SIInstrInfo::MO_NONE)
-      MIB.addImm(0);
-    else
-      MIB.add(MI.getOperand(2));
 
     Bundler.append(MIB);
     finalizeBundle(MBB, Bundler.begin());
 
     MI.eraseFromParent();
     break;
   }
   case AMDGPU::ENTER_WWM: {

test/CodeGen/AMDGPU/function-call-relocs.ll

-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -show-mc-encoding < %s | FileCheck -enable-var-scope -check-prefix=ASM %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -filetype=obj < %s |  llvm-objdump -triple amdgcn--amdhsa -mcpu=fiji -d - | FileCheck -enable-var-scope -check-prefix=DIS %s
 
 declare void @func(i32 addrspace(1)* %out)
 
-declare protected void @protected_func(i32 addrspace(1)* %out)
+declare protected void @protected_func(i32 addrspace(1)*)
 
-declare hidden void @hidden_func(i32 addrspace(1)* %out)
+declare hidden void @hidden_func(i32 addrspace(1)*)
 
-; CHECK-LABEL: call_func:
-; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; CHECK: s_add_u32 s[[GOT_ADDR_LO:[0-9]+]], s[[PC_LO]], func@gotpcrel32@lo+4
-; CHECK: s_addc_u32 s[[GOT_ADDR_HI:[0-9]+]], s[[PC_HI]], func@gotpcrel32@hi+4
-; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOT_ADDR_LO]]:[[GOT_ADDR_HI]]{{\]}}, 0x0
-; CHECK: s_swappc_b64 s{{\[}}{{[0-9]+:[0-9]+}}{{\]}}, s{{\[}}[[ADDR_LO]]:[[ADDR_HI]]{{\]}}
+; DIS: 0000000000000000 internal_func:
+define internal void @internal_func(i32 addrspace(1)* %out) {
+  ret void
+}
+
+; DIS: 0000000000000100 call_internal_func:
+
+; DIS: s_getpc_b64 s[8:9]                  // 000000000120: BE881C00
+; DIS-NEXT: s_add_u32 s8, s8, 0xfffffedc   // 000000000124: 8008FF08 FFFFFEDC
+; DIS-NEXT: s_addc_u32 s9, s9, -1          // 00000000012C: 8209FF09 FFFFFFFF
+
+; ASM-LABEL: call_internal_func:
+; ASM: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; ASM: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], internal_func+4  ; encoding: [0x08,0xff,0x08,0x80,A,A,A,A]
+; ASM-NEXT:                                                        ;   fixup A - offset: 4, value: internal_func+4, kind: FK_PCRel_4
+; ASM: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], hi32(internal_func+4) ; encoding: [0x09,0xff,0x09,0x82,A,A,A,A]
+; ASM-NEXT:                                                              ;   fixup A - offset: 4, value: hi32(internal_func+4), kind: fixup_si_pcrel_hi32
+
+; ASM: s_swappc_b64 s{{\[}}{{[0-9]+:[0-9]+}}{{\]}}, s{{\[}}[[ADDR_LO]]:[[ADDR_HI]]{{\]}}
+define amdgpu_kernel void @call_internal_func(i32 addrspace(1)* %out) {
+  call void @internal_func(i32 addrspace(1)* %out)
+  ret void
+}
+
+; ASM-LABEL: call_func:
+; ASM: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; ASM: s_add_u32 s[[GOT_ADDR_LO:[0-9]+]], s[[PC_LO]], func@gotpcrel32@lo+4
+; ASM: s_addc_u32 s[[GOT_ADDR_HI:[0-9]+]], s[[PC_HI]], func@gotpcrel32@hi+4
+; ASM: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOT_ADDR_LO]]:[[GOT_ADDR_HI]]{{\]}}, 0x0
+; ASM: s_swappc_b64 s{{\[}}{{[0-9]+:[0-9]+}}{{\]}}, s{{\[}}[[ADDR_LO]]:[[ADDR_HI]]{{\]}}
 define amdgpu_kernel void @call_func(i32 addrspace(1)* %out) {
   call void @func(i32 addrspace(1)* %out)
   ret void
 }
 
-; CHECK-LABEL: call_protected_func:
-; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], protected_func@rel32@lo+4
-; CHECK: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], protected_func@rel32@hi+4
-; CHECK: s_swappc_b64 s{{\[}}{{[0-9]+:[0-9]+}}{{\]}}, s{{\[}}[[ADDR_LO]]:[[ADDR_HI]]{{\]}}
+; ASM-LABEL: call_protected_func:
+; ASM: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; ASM: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], protected_func@rel32@lo+4
+; ASM: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], protected_func@rel32@hi+4
+; ASM: s_swappc_b64 s{{\[}}{{[0-9]+:[0-9]+}}{{\]}}, s{{\[}}[[ADDR_LO]]:[[ADDR_HI]]{{\]}}
 define amdgpu_kernel void @call_protected_func(i32 addrspace(1)* %out) {
   call void @protected_func(i32 addrspace(1)* %out)
   ret void
 }
 
-; CHECK-LABEL: call_hidden_func:
-; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], hidden_func@rel32@lo+4
-; CHECK: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], hidden_func@rel32@hi+4
-; CHECK: s_swappc_b64 s{{\[}}{{[0-9]+:[0-9]+}}{{\]}}, s{{\[}}[[ADDR_LO]]:[[ADDR_HI]]{{\]}}
+; ASM-LABEL: call_hidden_func:
+; ASM: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; ASM: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], hidden_func@rel32@lo+4
+; ASM: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], hidden_func@rel32@hi+4
+; ASM: s_swappc_b64 s{{\[}}{{[0-9]+:[0-9]+}}{{\]}}, s{{\[}}[[ADDR_LO]]:[[ADDR_HI]]{{\]}}
 define amdgpu_kernel void @call_hidden_func(i32 addrspace(1)* %out) {
   call void @hidden_func(i32 addrspace(1)* %out)
   ret void
 }
 
 declare i64 @funci()
 
-; CHECK-LABEL: tail_call_func:
-; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; CHECK: s_add_u32 s[[GOT_ADDR_LO:[0-9]+]], s[[PC_LO]], funci@gotpcrel32@lo+4
-; CHECK: s_addc_u32 s[[GOT_ADDR_HI:[0-9]+]], s[[PC_HI]], funci@gotpcrel32@hi+4
-; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOT_ADDR_LO]]:[[GOT_ADDR_HI]]{{\]}}, 0x0
-; CHECK: s_setpc_b64 s{{\[}}[[ADDR_LO]]:[[ADDR_HI]]{{\]}}
+; ASM-LABEL: tail_call_func:
+; ASM: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; ASM: s_add_u32 s[[GOT_ADDR_LO:[0-9]+]], s[[PC_LO]], funci@gotpcrel32@lo+4
+; ASM: s_addc_u32 s[[GOT_ADDR_HI:[0-9]+]], s[[PC_HI]], funci@gotpcrel32@hi+4
+; ASM: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOT_ADDR_LO]]:[[GOT_ADDR_HI]]{{\]}}, 0x0
+; ASM: s_setpc_b64 s{{\[}}[[ADDR_LO]]:[[ADDR_HI]]{{\]}}
 define i64 @tail_call_func() {
   %ret = tail call i64 @funci()
   ret i64 %ret
 }

test/CodeGen/AMDGPU/global-constant.ll

 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOHSA %s
 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA %s
 
 @private1 = private unnamed_addr addrspace(4) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0]
 @private2 = private unnamed_addr addrspace(4) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0]
 @available_externally = available_externally addrspace(4) global [256 x i32] zeroinitializer
 
 ; GCN-LABEL: {{^}}private_test:
 ; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
 
 ; Non-HSA OSes use fixup into .text section.
-; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1
-; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], 0
+; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1+4{{$}}
+; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], hi32(private1+4){{$}}
 
 ; HSA OSes use relocations.
 ; HSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1@rel32@lo+4
 ; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1@rel32@hi+4
 
 ; GCN: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
 
 ; Non-HSA OSes use fixup into .text section.
-; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2
-; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], 0
+; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2+4{{$}}
+; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], hi32(private2+4){{$}}
 
 ; HSA OSes use relocations.
 ; HSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2@rel32@lo+4
 ; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2@rel32@hi+4
 
 define amdgpu_kernel void @private_test(i32 %index, float addrspace(1)* %out) {
   %ptr = getelementptr [4 x float], [4 x float] addrspace(4) * @private1, i32 0, i32 %index
   %val = load float, float addrspace(4)* %ptr