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Differential D62345

[MachineScheduler] checkResourceLimit boundary condition update
ClosedPublic

Authored by jsji on May 23 2019, 2:15 PM.

Details

Reviewers
atrick
hfinkel
MatzeB
fhahn
jonpa
stefanp
javed.absar
niravd
Commits
rG7aafdef62711: [MachineScheduler] checkResourceLimit boundary condition update
rL362805: [MachineScheduler] checkResourceLimit boundary condition update
Summary

When we call checkResourceLimit in bumpCycle or bumpNode, and we
know the resource count has just reached the limit (the equations
are equal). We should return true to mark that we are resource
limited for next schedule, or else we might continue to schedule
in favor of latency for 1 more schedule and create a schedule that
actually overbook the resource.

When we call checkResourceLimit to estimate the resource limit before
scheduling, we don't need to return true even if the equations are
equal, as it shouldn't limit the schedule for it .

Diff Detail

Repository
rL LLVM

Event Timeline

jsji created this revision.May 23 2019, 2:15 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 23 2019, 2:15 PM
Herald added a subscriber: hiraditya. · View Herald Transcript
javed.absar added a comment.May 24 2019, 6:06 AM

Would this end up prioritising 'resourcelimited' too much? Looks like there can be performance differences between before and after this change - any numbers / thoughts on that?

llvm/lib/CodeGen/MachineScheduler.cpp
1841 ↗(On Diff #201063)

maybe reword 'equations are equal' to something more contextual ....

1845 ↗(On Diff #201063)

repeated computation

jsji marked 2 inline comments as done.EditedMay 24 2019, 6:20 AM
In D62345#1515781, @javed.absar wrote:

Would this end up prioritising 'resourcelimited' too much? Looks like there can be performance differences between before and after this change - any numbers / thoughts on that?

I think we just avoid disregarding 'resourcelimited' at certain situation, shouldn't be prioritising it too much.
I am working on gathering some performance data .

llvm/lib/CodeGen/MachineScheduler.cpp
1841 ↗(On Diff #201063)

Sure. How about "we just reach the resource limit"? Or any suggestion?

1845 ↗(On Diff #201063)

Thought build compiler should be able to optimize it. But yes, I can do it something like:

int ResCntFactor = (int)(Count - (Latency * LFactor));
if (AfterSchedNode)
    return ResCntFactor >= (int)LFactor;
else
    return ResCntFactor > (int)LFactor;
jsji updated this revision to Diff 202051.May 29 2019, 1:58 PM

Fix comment & repeated computation. Performance run still ongoing.

jsji added a comment.May 30 2019, 7:32 PM
In D62345#1515781, @javed.absar wrote:

Would this end up prioritising 'resourcelimited' too much? Looks like there can be performance differences between before and after this change - any numbers / thoughts on that?

The SPEC2k17 performance test on P9 system shows GEOMEAN 0.3% improvement,
with 1 biggest deg -0.50%, 2 biggest improvement +1.64%, +1.52%, others are within +-0.4%.

@javed.absar

jsji added a comment.Jun 6 2019, 7:15 PM

Ping.. Any more comments and feedback @javed.absar . Thanks.

javed.absar accepted this revision.Jun 7 2019, 1:47 AM

LGTM. Sorry for the delay

This revision is now accepted and ready to land.Jun 7 2019, 1:47 AM
jsji updated this revision to Diff 203556.Jun 7 2019, 7:42 AM

Thanks Javed! Rebased to ToT before committing.

Closed by commit rL362805: [MachineScheduler] checkResourceLimit boundary condition update (authored by jsji). · Explain WhyJun 7 2019, 7:51 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
16 lines
test/
CodeGen/
PowerPC/
4 lines
6 lines
2 lines
16 lines
16 lines

Diff 203558

llvm/trunk/lib/CodeGen/MachineScheduler.cpp

Show First 20 Lines • Show All 1,831 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
static const unsigned InvalidCycle = ~0U; static const unsigned InvalidCycle = ~0U;
SchedBoundary::~SchedBoundary() { delete HazardRec; } SchedBoundary::~SchedBoundary() { delete HazardRec; }
/// Given a Count of resource usage and a Latency value, return true if a /// Given a Count of resource usage and a Latency value, return true if a
/// SchedBoundary becomes resource limited. /// SchedBoundary becomes resource limited.
/// If we are checking after scheduling a node, we should return true when
/// we just reach the resource limit.
static bool checkResourceLimit(unsigned LFactor, unsigned Count, static bool checkResourceLimit(unsigned LFactor, unsigned Count,
unsigned Latency) { unsigned Latency, bool AfterSchedNode) {
return (int)(Count - (Latency * LFactor)) > (int)LFactor; int ResCntFactor = (int)(Count - (Latency * LFactor));
if (AfterSchedNode)
return ResCntFactor >= (int)LFactor;
else
return ResCntFactor > (int)LFactor;
} }
void SchedBoundary::reset() { void SchedBoundary::reset() {
// A new HazardRec is created for each DAG and owned by SchedBoundary. // A new HazardRec is created for each DAG and owned by SchedBoundary.
// Destroying and reconstructing it is very expensive though. So keep // Destroying and reconstructing it is very expensive though. So keep
// invalid, placeholder HazardRecs. // invalid, placeholder HazardRecs.
if (HazardRec && HazardRec->isEnabled()) { if (HazardRec && HazardRec->isEnabled()) {
delete HazardRec; delete HazardRec;
▲ Show 20 Lines • Show All 278 Lines • ▼ Show 20 Lines for (; CurrCycle != NextCycle; ++CurrCycle) {
HazardRec->AdvanceCycle(); HazardRec->AdvanceCycle();
else else
HazardRec->RecedeCycle(); HazardRec->RecedeCycle();
} }
} }
CheckPending = true; CheckPending = true;
IsResourceLimited = IsResourceLimited =
checkResourceLimit(SchedModel->getLatencyFactor(), getCriticalCount(), checkResourceLimit(SchedModel->getLatencyFactor(), getCriticalCount(),
getScheduledLatency()); getScheduledLatency(), true);
LLVM_DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName() LLVM_DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName()
<< '\n'); << '\n');
} }
void SchedBoundary::incExecutedResources(unsigned PIdx, unsigned Count) { void SchedBoundary::incExecutedResources(unsigned PIdx, unsigned Count) {
ExecutedResCounts[PIdx] += Count; ExecutedResCounts[PIdx] += Count;
if (ExecutedResCounts[PIdx] > MaxExecutedResCount) if (ExecutedResCounts[PIdx] > MaxExecutedResCount)
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Linesvoid SchedBoundary::bumpNode(SUnit *SU) {
// If we stall for any reason, bump the cycle. // If we stall for any reason, bump the cycle.
if (NextCycle > CurrCycle) if (NextCycle > CurrCycle)
bumpCycle(NextCycle); bumpCycle(NextCycle);
else else
// After updating ZoneCritResIdx and ExpectedLatency, check if we're // After updating ZoneCritResIdx and ExpectedLatency, check if we're
// resource limited. If a stall occurred, bumpCycle does this. // resource limited. If a stall occurred, bumpCycle does this.
IsResourceLimited = IsResourceLimited =
checkResourceLimit(SchedModel->getLatencyFactor(), getCriticalCount(), checkResourceLimit(SchedModel->getLatencyFactor(), getCriticalCount(),
getScheduledLatency()); getScheduledLatency(), true);
// Update CurrMOps after calling bumpCycle to handle stalls, since bumpCycle // Update CurrMOps after calling bumpCycle to handle stalls, since bumpCycle
// resets CurrMOps. Loop to handle instructions with more MOps than issue in // resets CurrMOps. Loop to handle instructions with more MOps than issue in
// one cycle. Since we commonly reach the max MOps here, opportunistically // one cycle. Since we commonly reach the max MOps here, opportunistically
// bump the cycle to avoid uselessly checking everything in the readyQ. // bump the cycle to avoid uselessly checking everything in the readyQ.
CurrMOps += IncMOps; CurrMOps += IncMOps;
// Bump the cycle count for issue group constraints. // Bump the cycle count for issue group constraints.
▲ Show 20 Lines • Show All 202 Lines • ▼ Show 20 Linesvoid GenericSchedulerBase::setPolicy(CandPolicy &Policy, bool IsPostRA,
bool OtherResLimited = false; bool OtherResLimited = false;
unsigned RemLatency = 0; unsigned RemLatency = 0;
bool RemLatencyComputed = false; bool RemLatencyComputed = false;
if (SchedModel->hasInstrSchedModel() && OtherCount != 0) { if (SchedModel->hasInstrSchedModel() && OtherCount != 0) {
RemLatency = computeRemLatency(CurrZone); RemLatency = computeRemLatency(CurrZone);
RemLatencyComputed = true; RemLatencyComputed = true;
OtherResLimited = checkResourceLimit(SchedModel->getLatencyFactor(), OtherResLimited = checkResourceLimit(SchedModel->getLatencyFactor(),
OtherCount, RemLatency); OtherCount, RemLatency, false);
} }
// Schedule aggressively for latency in PostRA mode. We don't check for // Schedule aggressively for latency in PostRA mode. We don't check for
// acyclic latency during PostRA, and highly out-of-order processors will // acyclic latency during PostRA, and highly out-of-order processors will
// skip PostRA scheduling. // skip PostRA scheduling.
if (!OtherResLimited && if (!OtherResLimited &&
(IsPostRA || shouldReduceLatency(Policy, CurrZone, !RemLatencyComputed, (IsPostRA || shouldReduceLatency(Policy, CurrZone, !RemLatencyComputed,
RemLatency))) { RemLatency))) {
▲ Show 20 Lines • Show All 1,219 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/build-vector-tests.ll

Show First 20 Lines • Show All 2,018 Lines • ▼ Show 20 Lines
; P9BE-NEXT: xvcvdpsxws v3, vs0 ; P9BE-NEXT: xvcvdpsxws v3, vs0
; P9BE-NEXT: vmrgew v2, v3, v2 ; P9BE-NEXT: vmrgew v2, v3, v2
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffMemConsDConvdtoi: ; P9LE-LABEL: fromDiffMemConsDConvdtoi:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lfd f0, 24(r3) ; P9LE-NEXT: lfd f0, 24(r3)
; P9LE-NEXT: lfd f2, 8(r3) ; P9LE-NEXT: lfd f2, 8(r3)
; P9LE-NEXT: lfd f1, 16(r3)
; P9LE-NEXT: xxmrghd vs0, vs2, vs0 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
; P9LE-NEXT: lfd f1, 16(r3)
; P9LE-NEXT: lfd f3, 0(r3) ; P9LE-NEXT: lfd f3, 0(r3)
; P9LE-NEXT: xvcvdpsxws v2, vs0 ; P9LE-NEXT: xvcvdpsxws v2, vs0
; P9LE-NEXT: xxmrghd vs0, vs3, vs1 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
; P9LE-NEXT: xvcvdpsxws v3, vs0 ; P9LE-NEXT: xvcvdpsxws v3, vs0
; P9LE-NEXT: vmrgew v2, v3, v2 ; P9LE-NEXT: vmrgew v2, v3, v2
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffMemConsDConvdtoi: ; P8BE-LABEL: fromDiffMemConsDConvdtoi:
▲ Show 20 Lines • Show All 1,566 Lines • ▼ Show 20 Lines
; P9BE-NEXT: xvcvdpuxws v3, vs0 ; P9BE-NEXT: xvcvdpuxws v3, vs0
; P9BE-NEXT: vmrgew v2, v3, v2 ; P9BE-NEXT: vmrgew v2, v3, v2
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffMemConsDConvdtoui: ; P9LE-LABEL: fromDiffMemConsDConvdtoui:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lfd f0, 24(r3) ; P9LE-NEXT: lfd f0, 24(r3)
; P9LE-NEXT: lfd f2, 8(r3) ; P9LE-NEXT: lfd f2, 8(r3)
; P9LE-NEXT: lfd f1, 16(r3)
; P9LE-NEXT: xxmrghd vs0, vs2, vs0 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
; P9LE-NEXT: lfd f1, 16(r3)
; P9LE-NEXT: lfd f3, 0(r3) ; P9LE-NEXT: lfd f3, 0(r3)
; P9LE-NEXT: xvcvdpuxws v2, vs0 ; P9LE-NEXT: xvcvdpuxws v2, vs0
; P9LE-NEXT: xxmrghd vs0, vs3, vs1 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
; P9LE-NEXT: xvcvdpuxws v3, vs0 ; P9LE-NEXT: xvcvdpuxws v3, vs0
; P9LE-NEXT: vmrgew v2, v3, v2 ; P9LE-NEXT: vmrgew v2, v3, v2
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffMemConsDConvdtoui: ; P8BE-LABEL: fromDiffMemConsDConvdtoui:
▲ Show 20 Lines • Show All 2,772 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/csr-save-restore-order.ll

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-PWR9-NEXT: .cfi_offset v26, -384 ; CHECK-PWR9-NEXT: .cfi_offset v26, -384
; CHECK-PWR9-NEXT: .cfi_offset v27, -368 ; CHECK-PWR9-NEXT: .cfi_offset v27, -368
; CHECK-PWR9-NEXT: .cfi_offset v28, -352 ; CHECK-PWR9-NEXT: .cfi_offset v28, -352
; CHECK-PWR9-NEXT: .cfi_offset v29, -336 ; CHECK-PWR9-NEXT: .cfi_offset v29, -336
; CHECK-PWR9-NEXT: .cfi_offset v30, -320 ; CHECK-PWR9-NEXT: .cfi_offset v30, -320
; CHECK-PWR9-NEXT: .cfi_offset v31, -304 ; CHECK-PWR9-NEXT: .cfi_offset v31, -304
; CHECK-PWR9-NEXT: std r14, 240(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r14, 240(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r15, 248(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r15, 248(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r16, 256(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: stxv v20, 48(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v20, 48(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: stxv v21, 64(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v21, 64(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: std r16, 256(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: stxv v22, 80(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v22, 80(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: std r17, 264(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r17, 264(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: stxv v23, 96(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v23, 96(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: std r18, 272(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r18, 272(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r19, 280(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r19, 280(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: stxv v24, 112(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v24, 112(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: std r20, 288(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r20, 288(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: stxv v25, 128(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v25, 128(r1) # 16-byte Folded Spill
Show All 36 Lines
; CHECK-PWR9-NEXT: std r3, 32(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r3, 32(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: #APP ; CHECK-PWR9-NEXT: #APP
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: #NO_APP ; CHECK-PWR9-NEXT: #NO_APP
; CHECK-PWR9-NEXT: ld r3, 40(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r3, 40(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r4, 32(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r4, 32(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v31, 224(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v31, 224(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v30, 208(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v30, 208(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v29, 192(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: add r3, r4, r3 ; CHECK-PWR9-NEXT: add r3, r4, r3
; CHECK-PWR9-NEXT: lxv v29, 192(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v28, 176(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v28, 176(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v27, 160(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v27, 160(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v26, 144(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v26, 144(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v25, 128(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v25, 128(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v24, 112(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v24, 112(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v23, 96(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v23, 96(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v22, 80(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v22, 80(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v21, 64(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v21, 64(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v20, 48(r1) # 16-byte Folded Reload ; CHECK-PWR9-NEXT: lxv v20, 48(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f31, 520(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lfd f31, 520(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f30, 512(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lfd f30, 512(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f29, 504(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lfd f29, 504(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f28, 496(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lfd f28, 496(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f27, 488(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lfd f27, 488(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f26, 480(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r31, 376(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r31, 376(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r30, 368(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r30, 368(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r29, 360(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r29, 360(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r28, 352(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r28, 352(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f26, 480(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r27, 344(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r27, 344(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r26, 336(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r26, 336(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r25, 328(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r25, 328(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f25, 472(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lfd f25, 472(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r24, 320(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r24, 320(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r23, 312(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r23, 312(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r22, 304(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r22, 304(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f24, 464(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lfd f24, 464(r1) # 8-byte Folded Reload
Show All 25 Lines

llvm/trunk/test/CodeGen/PowerPC/f128-passByValue.ll

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; Up to 12 qualified floating-point arguments can be passed in v2-v13. ; Up to 12 qualified floating-point arguments can be passed in v2-v13.
; Function to test passing 13 float128 parameters. ; Function to test passing 13 float128 parameters.
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @maxVecParam(fp128 %p1, fp128 %p2, fp128 %p3, fp128 %p4, fp128 %p5, define fp128 @maxVecParam(fp128 %p1, fp128 %p2, fp128 %p3, fp128 %p4, fp128 %p5,
; CHECK-LABEL: maxVecParam: ; CHECK-LABEL: maxVecParam:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: lxv v[[REG0:[0-9]+]], 224(r1)
; CHECK-NEXT: xsaddqp v2, v2, v4 ; CHECK-NEXT: xsaddqp v2, v2, v4
; CHECK-NEXT: xsaddqp v2, v2, v5 ; CHECK-NEXT: xsaddqp v2, v2, v5
; CHECK-NEXT: xsaddqp v2, v2, v6 ; CHECK-NEXT: xsaddqp v2, v2, v6
; CHECK-NEXT: xsaddqp v2, v2, v7 ; CHECK-NEXT: xsaddqp v2, v2, v7
; CHECK-NEXT: xsaddqp v2, v2, v8 ; CHECK-NEXT: xsaddqp v2, v2, v8
; CHECK-NEXT: xsaddqp v2, v2, v9 ; CHECK-NEXT: xsaddqp v2, v2, v9
; CHECK-NEXT: xsaddqp v2, v2, v10 ; CHECK-NEXT: xsaddqp v2, v2, v10
; CHECK-NEXT: xsaddqp v2, v2, v11 ; CHECK-NEXT: xsaddqp v2, v2, v11
; CHECK-NEXT: xsaddqp v2, v2, v12 ; CHECK-NEXT: xsaddqp v2, v2, v12
; CHECK-NEXT: xsaddqp v2, v2, v13 ; CHECK-NEXT: xsaddqp v2, v2, v13
; CHECK-NEXT: lxv v[[REG0:[0-9]+]], 224(r1)
; CHECK-NEXT: xssubqp v2, v2, v[[REG0]] ; CHECK-NEXT: xssubqp v2, v2, v[[REG0]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
fp128 %p6, fp128 %p7, fp128 %p8, fp128 %p9, fp128 %p10, fp128 %p6, fp128 %p7, fp128 %p8, fp128 %p9, fp128 %p10,
fp128 %p11, fp128 %p12, fp128 %p13) { fp128 %p11, fp128 %p12, fp128 %p13) {
entry: entry:
%add = fadd fp128 %p1, %p2 %add = fadd fp128 %p1, %p2
%add1 = fadd fp128 %add, %p3 %add1 = fadd fp128 %add, %p3
%add2 = fadd fp128 %add1, %p4 %add2 = fadd fp128 %add1, %p4
▲ Show 20 Lines • Show All 162 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/vec_conv_fp_to_i_8byte_elts.ll

Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 112(r4) ; CHECK-P9-NEXT: lxv vs0, 112(r4)
; CHECK-P9-NEXT: lxv vs1, 96(r4) ; CHECK-P9-NEXT: lxv vs1, 96(r4)
; CHECK-P9-NEXT: lxv vs2, 80(r4) ; CHECK-P9-NEXT: lxv vs2, 80(r4)
; CHECK-P9-NEXT: lxv vs3, 64(r4) ; CHECK-P9-NEXT: lxv vs3, 64(r4)
; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
; CHECK-P9-NEXT: lxv vs4, 48(r4) ; CHECK-P9-NEXT: lxv vs4, 48(r4)
; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
; CHECK-P9-NEXT: lxv vs5, 32(r4) ; CHECK-P9-NEXT: lxv vs5, 32(r4)
; CHECK-P9-NEXT: lxv vs6, 16(r4) ; CHECK-P9-NEXT: lxv vs6, 16(r4)
; CHECK-P9-NEXT: lxv vs7, 0(r4) ; CHECK-P9-NEXT: lxv vs7, 0(r4)
; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7 ; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7
; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6 ; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6
; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5 ; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5
; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3 ; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2 ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
; CHECK-P9-NEXT: stxv vs0, 112(r3) ; CHECK-P9-NEXT: stxv vs0, 112(r3)
; CHECK-P9-NEXT: stxv vs1, 96(r3) ; CHECK-P9-NEXT: stxv vs1, 96(r3)
; CHECK-P9-NEXT: stxv vs2, 80(r3) ; CHECK-P9-NEXT: stxv vs2, 80(r3)
; CHECK-P9-NEXT: stxv vs3, 64(r3) ; CHECK-P9-NEXT: stxv vs3, 64(r3)
; CHECK-P9-NEXT: stxv vs4, 48(r3) ; CHECK-P9-NEXT: stxv vs4, 48(r3)
; CHECK-P9-NEXT: stxv vs5, 32(r3) ; CHECK-P9-NEXT: stxv vs5, 32(r3)
; CHECK-P9-NEXT: stxv vs6, 16(r3) ; CHECK-P9-NEXT: stxv vs6, 16(r3)
; CHECK-P9-NEXT: stxv vs7, 0(r3) ; CHECK-P9-NEXT: stxv vs7, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 112(r4) ; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: lxv vs1, 96(r4) ; CHECK-BE-NEXT: lxv vs1, 96(r4)
; CHECK-BE-NEXT: lxv vs2, 80(r4) ; CHECK-BE-NEXT: lxv vs2, 80(r4)
; CHECK-BE-NEXT: lxv vs3, 64(r4) ; CHECK-BE-NEXT: lxv vs3, 64(r4)
; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3
; CHECK-BE-NEXT: lxv vs4, 48(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4
; CHECK-BE-NEXT: lxv vs5, 32(r4) ; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: lxv vs6, 16(r4) ; CHECK-BE-NEXT: lxv vs6, 16(r4)
; CHECK-BE-NEXT: lxv vs7, 0(r4) ; CHECK-BE-NEXT: lxv vs7, 0(r4)
; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7 ; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7
; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6 ; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6
; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5 ; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5
; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3 ; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4
; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2 ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
; CHECK-BE-NEXT: stxv vs0, 112(r3) ; CHECK-BE-NEXT: stxv vs0, 112(r3)
; CHECK-BE-NEXT: stxv vs1, 96(r3) ; CHECK-BE-NEXT: stxv vs1, 96(r3)
; CHECK-BE-NEXT: stxv vs2, 80(r3) ; CHECK-BE-NEXT: stxv vs2, 80(r3)
; CHECK-BE-NEXT: stxv vs3, 64(r3) ; CHECK-BE-NEXT: stxv vs3, 64(r3)
; CHECK-BE-NEXT: stxv vs4, 48(r3) ; CHECK-BE-NEXT: stxv vs4, 48(r3)
▲ Show 20 Lines • Show All 161 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 112(r4) ; CHECK-P9-NEXT: lxv vs0, 112(r4)
; CHECK-P9-NEXT: lxv vs1, 96(r4) ; CHECK-P9-NEXT: lxv vs1, 96(r4)
; CHECK-P9-NEXT: lxv vs2, 80(r4) ; CHECK-P9-NEXT: lxv vs2, 80(r4)
; CHECK-P9-NEXT: lxv vs3, 64(r4) ; CHECK-P9-NEXT: lxv vs3, 64(r4)
; CHECK-P9-NEXT: xvcvdpsxds vs3, vs3
; CHECK-P9-NEXT: lxv vs4, 48(r4) ; CHECK-P9-NEXT: lxv vs4, 48(r4)
; CHECK-P9-NEXT: xvcvdpsxds vs4, vs4
; CHECK-P9-NEXT: lxv vs5, 32(r4) ; CHECK-P9-NEXT: lxv vs5, 32(r4)
; CHECK-P9-NEXT: lxv vs6, 16(r4) ; CHECK-P9-NEXT: lxv vs6, 16(r4)
; CHECK-P9-NEXT: lxv vs7, 0(r4) ; CHECK-P9-NEXT: lxv vs7, 0(r4)
; CHECK-P9-NEXT: xvcvdpsxds vs7, vs7 ; CHECK-P9-NEXT: xvcvdpsxds vs7, vs7
; CHECK-P9-NEXT: xvcvdpsxds vs6, vs6 ; CHECK-P9-NEXT: xvcvdpsxds vs6, vs6
; CHECK-P9-NEXT: xvcvdpsxds vs5, vs5 ; CHECK-P9-NEXT: xvcvdpsxds vs5, vs5
; CHECK-P9-NEXT: xvcvdpsxds vs3, vs3 ; CHECK-P9-NEXT: xvcvdpsxds vs4, vs4
; CHECK-P9-NEXT: xvcvdpsxds vs2, vs2 ; CHECK-P9-NEXT: xvcvdpsxds vs2, vs2
; CHECK-P9-NEXT: xvcvdpsxds vs1, vs1 ; CHECK-P9-NEXT: xvcvdpsxds vs1, vs1
; CHECK-P9-NEXT: xvcvdpsxds vs0, vs0 ; CHECK-P9-NEXT: xvcvdpsxds vs0, vs0
; CHECK-P9-NEXT: stxv vs0, 112(r3) ; CHECK-P9-NEXT: stxv vs0, 112(r3)
; CHECK-P9-NEXT: stxv vs1, 96(r3) ; CHECK-P9-NEXT: stxv vs1, 96(r3)
; CHECK-P9-NEXT: stxv vs2, 80(r3) ; CHECK-P9-NEXT: stxv vs2, 80(r3)
; CHECK-P9-NEXT: stxv vs3, 64(r3) ; CHECK-P9-NEXT: stxv vs3, 64(r3)
; CHECK-P9-NEXT: stxv vs4, 48(r3) ; CHECK-P9-NEXT: stxv vs4, 48(r3)
; CHECK-P9-NEXT: stxv vs5, 32(r3) ; CHECK-P9-NEXT: stxv vs5, 32(r3)
; CHECK-P9-NEXT: stxv vs6, 16(r3) ; CHECK-P9-NEXT: stxv vs6, 16(r3)
; CHECK-P9-NEXT: stxv vs7, 0(r3) ; CHECK-P9-NEXT: stxv vs7, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 112(r4) ; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: lxv vs1, 96(r4) ; CHECK-BE-NEXT: lxv vs1, 96(r4)
; CHECK-BE-NEXT: lxv vs2, 80(r4) ; CHECK-BE-NEXT: lxv vs2, 80(r4)
; CHECK-BE-NEXT: lxv vs3, 64(r4) ; CHECK-BE-NEXT: lxv vs3, 64(r4)
; CHECK-BE-NEXT: xvcvdpsxds vs3, vs3
; CHECK-BE-NEXT: lxv vs4, 48(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: xvcvdpsxds vs4, vs4
; CHECK-BE-NEXT: lxv vs5, 32(r4) ; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: lxv vs6, 16(r4) ; CHECK-BE-NEXT: lxv vs6, 16(r4)
; CHECK-BE-NEXT: lxv vs7, 0(r4) ; CHECK-BE-NEXT: lxv vs7, 0(r4)
; CHECK-BE-NEXT: xvcvdpsxds vs7, vs7 ; CHECK-BE-NEXT: xvcvdpsxds vs7, vs7
; CHECK-BE-NEXT: xvcvdpsxds vs6, vs6 ; CHECK-BE-NEXT: xvcvdpsxds vs6, vs6
; CHECK-BE-NEXT: xvcvdpsxds vs5, vs5 ; CHECK-BE-NEXT: xvcvdpsxds vs5, vs5
; CHECK-BE-NEXT: xvcvdpsxds vs3, vs3 ; CHECK-BE-NEXT: xvcvdpsxds vs4, vs4
; CHECK-BE-NEXT: xvcvdpsxds vs2, vs2 ; CHECK-BE-NEXT: xvcvdpsxds vs2, vs2
; CHECK-BE-NEXT: xvcvdpsxds vs1, vs1 ; CHECK-BE-NEXT: xvcvdpsxds vs1, vs1
; CHECK-BE-NEXT: xvcvdpsxds vs0, vs0 ; CHECK-BE-NEXT: xvcvdpsxds vs0, vs0
; CHECK-BE-NEXT: stxv vs0, 112(r3) ; CHECK-BE-NEXT: stxv vs0, 112(r3)
; CHECK-BE-NEXT: stxv vs1, 96(r3) ; CHECK-BE-NEXT: stxv vs1, 96(r3)
; CHECK-BE-NEXT: stxv vs2, 80(r3) ; CHECK-BE-NEXT: stxv vs2, 80(r3)
; CHECK-BE-NEXT: stxv vs3, 64(r3) ; CHECK-BE-NEXT: stxv vs3, 64(r3)
; CHECK-BE-NEXT: stxv vs4, 48(r3) ; CHECK-BE-NEXT: stxv vs4, 48(r3)
Show All 10 Lines

llvm/trunk/test/CodeGen/PowerPC/vec_conv_i_to_fp_8byte_elts.ll

Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 112(r4) ; CHECK-P9-NEXT: lxv v2, 112(r4)
; CHECK-P9-NEXT: lxv v3, 96(r4) ; CHECK-P9-NEXT: lxv v3, 96(r4)
; CHECK-P9-NEXT: lxv v4, 80(r4) ; CHECK-P9-NEXT: lxv v4, 80(r4)
; CHECK-P9-NEXT: lxv v5, 64(r4) ; CHECK-P9-NEXT: lxv v5, 64(r4)
; CHECK-P9-NEXT: xvcvuxddp vs4, v5
; CHECK-P9-NEXT: lxv v0, 48(r4) ; CHECK-P9-NEXT: lxv v0, 48(r4)
; CHECK-P9-NEXT: xvcvuxddp vs3, v0
; CHECK-P9-NEXT: lxv v1, 32(r4) ; CHECK-P9-NEXT: lxv v1, 32(r4)
; CHECK-P9-NEXT: lxv v6, 16(r4) ; CHECK-P9-NEXT: lxv v6, 16(r4)
; CHECK-P9-NEXT: lxv v7, 0(r4) ; CHECK-P9-NEXT: lxv v7, 0(r4)
; CHECK-P9-NEXT: xvcvuxddp vs0, v7 ; CHECK-P9-NEXT: xvcvuxddp vs0, v7
; CHECK-P9-NEXT: xvcvuxddp vs1, v6 ; CHECK-P9-NEXT: xvcvuxddp vs1, v6
; CHECK-P9-NEXT: xvcvuxddp vs2, v1 ; CHECK-P9-NEXT: xvcvuxddp vs2, v1
; CHECK-P9-NEXT: xvcvuxddp vs4, v5 ; CHECK-P9-NEXT: xvcvuxddp vs3, v0
; CHECK-P9-NEXT: xvcvuxddp vs5, v4 ; CHECK-P9-NEXT: xvcvuxddp vs5, v4
; CHECK-P9-NEXT: xvcvuxddp vs6, v3 ; CHECK-P9-NEXT: xvcvuxddp vs6, v3
; CHECK-P9-NEXT: xvcvuxddp vs7, v2 ; CHECK-P9-NEXT: xvcvuxddp vs7, v2
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: stxv vs5, 80(r3)
; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: stxv vs4, 64(r3)
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 112(r4) ; CHECK-BE-NEXT: lxv v2, 112(r4)
; CHECK-BE-NEXT: lxv v3, 96(r4) ; CHECK-BE-NEXT: lxv v3, 96(r4)
; CHECK-BE-NEXT: lxv v4, 80(r4) ; CHECK-BE-NEXT: lxv v4, 80(r4)
; CHECK-BE-NEXT: lxv v5, 64(r4) ; CHECK-BE-NEXT: lxv v5, 64(r4)
; CHECK-BE-NEXT: xvcvuxddp vs4, v5
; CHECK-BE-NEXT: lxv v0, 48(r4) ; CHECK-BE-NEXT: lxv v0, 48(r4)
; CHECK-BE-NEXT: xvcvuxddp vs3, v0
; CHECK-BE-NEXT: lxv v1, 32(r4) ; CHECK-BE-NEXT: lxv v1, 32(r4)
; CHECK-BE-NEXT: lxv v6, 16(r4) ; CHECK-BE-NEXT: lxv v6, 16(r4)
; CHECK-BE-NEXT: lxv v7, 0(r4) ; CHECK-BE-NEXT: lxv v7, 0(r4)
; CHECK-BE-NEXT: xvcvuxddp vs0, v7 ; CHECK-BE-NEXT: xvcvuxddp vs0, v7
; CHECK-BE-NEXT: xvcvuxddp vs1, v6 ; CHECK-BE-NEXT: xvcvuxddp vs1, v6
; CHECK-BE-NEXT: xvcvuxddp vs2, v1 ; CHECK-BE-NEXT: xvcvuxddp vs2, v1
; CHECK-BE-NEXT: xvcvuxddp vs4, v5 ; CHECK-BE-NEXT: xvcvuxddp vs3, v0
; CHECK-BE-NEXT: xvcvuxddp vs5, v4 ; CHECK-BE-NEXT: xvcvuxddp vs5, v4
; CHECK-BE-NEXT: xvcvuxddp vs6, v3 ; CHECK-BE-NEXT: xvcvuxddp vs6, v3
; CHECK-BE-NEXT: xvcvuxddp vs7, v2 ; CHECK-BE-NEXT: xvcvuxddp vs7, v2
; CHECK-BE-NEXT: stxv vs7, 112(r3) ; CHECK-BE-NEXT: stxv vs7, 112(r3)
; CHECK-BE-NEXT: stxv vs6, 96(r3) ; CHECK-BE-NEXT: stxv vs6, 96(r3)
; CHECK-BE-NEXT: stxv vs5, 80(r3) ; CHECK-BE-NEXT: stxv vs5, 80(r3)
; CHECK-BE-NEXT: stxv vs4, 64(r3) ; CHECK-BE-NEXT: stxv vs4, 64(r3)
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
▲ Show 20 Lines • Show All 161 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 112(r4) ; CHECK-P9-NEXT: lxv v2, 112(r4)
; CHECK-P9-NEXT: lxv v3, 96(r4) ; CHECK-P9-NEXT: lxv v3, 96(r4)
; CHECK-P9-NEXT: lxv v4, 80(r4) ; CHECK-P9-NEXT: lxv v4, 80(r4)
; CHECK-P9-NEXT: lxv v5, 64(r4) ; CHECK-P9-NEXT: lxv v5, 64(r4)
; CHECK-P9-NEXT: xvcvsxddp vs4, v5
; CHECK-P9-NEXT: lxv v0, 48(r4) ; CHECK-P9-NEXT: lxv v0, 48(r4)
; CHECK-P9-NEXT: xvcvsxddp vs3, v0
; CHECK-P9-NEXT: lxv v1, 32(r4) ; CHECK-P9-NEXT: lxv v1, 32(r4)
; CHECK-P9-NEXT: lxv v6, 16(r4) ; CHECK-P9-NEXT: lxv v6, 16(r4)
; CHECK-P9-NEXT: lxv v7, 0(r4) ; CHECK-P9-NEXT: lxv v7, 0(r4)
; CHECK-P9-NEXT: xvcvsxddp vs0, v7 ; CHECK-P9-NEXT: xvcvsxddp vs0, v7
; CHECK-P9-NEXT: xvcvsxddp vs1, v6 ; CHECK-P9-NEXT: xvcvsxddp vs1, v6
; CHECK-P9-NEXT: xvcvsxddp vs2, v1 ; CHECK-P9-NEXT: xvcvsxddp vs2, v1
; CHECK-P9-NEXT: xvcvsxddp vs4, v5 ; CHECK-P9-NEXT: xvcvsxddp vs3, v0
; CHECK-P9-NEXT: xvcvsxddp vs5, v4 ; CHECK-P9-NEXT: xvcvsxddp vs5, v4
; CHECK-P9-NEXT: xvcvsxddp vs6, v3 ; CHECK-P9-NEXT: xvcvsxddp vs6, v3
; CHECK-P9-NEXT: xvcvsxddp vs7, v2 ; CHECK-P9-NEXT: xvcvsxddp vs7, v2
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: stxv vs5, 80(r3)
; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: stxv vs4, 64(r3)
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 112(r4) ; CHECK-BE-NEXT: lxv v2, 112(r4)
; CHECK-BE-NEXT: lxv v3, 96(r4) ; CHECK-BE-NEXT: lxv v3, 96(r4)
; CHECK-BE-NEXT: lxv v4, 80(r4) ; CHECK-BE-NEXT: lxv v4, 80(r4)
; CHECK-BE-NEXT: lxv v5, 64(r4) ; CHECK-BE-NEXT: lxv v5, 64(r4)
; CHECK-BE-NEXT: xvcvsxddp vs4, v5
; CHECK-BE-NEXT: lxv v0, 48(r4) ; CHECK-BE-NEXT: lxv v0, 48(r4)
; CHECK-BE-NEXT: xvcvsxddp vs3, v0
; CHECK-BE-NEXT: lxv v1, 32(r4) ; CHECK-BE-NEXT: lxv v1, 32(r4)
; CHECK-BE-NEXT: lxv v6, 16(r4) ; CHECK-BE-NEXT: lxv v6, 16(r4)
; CHECK-BE-NEXT: lxv v7, 0(r4) ; CHECK-BE-NEXT: lxv v7, 0(r4)
; CHECK-BE-NEXT: xvcvsxddp vs0, v7 ; CHECK-BE-NEXT: xvcvsxddp vs0, v7
; CHECK-BE-NEXT: xvcvsxddp vs1, v6 ; CHECK-BE-NEXT: xvcvsxddp vs1, v6
; CHECK-BE-NEXT: xvcvsxddp vs2, v1 ; CHECK-BE-NEXT: xvcvsxddp vs2, v1
; CHECK-BE-NEXT: xvcvsxddp vs4, v5 ; CHECK-BE-NEXT: xvcvsxddp vs3, v0
; CHECK-BE-NEXT: xvcvsxddp vs5, v4 ; CHECK-BE-NEXT: xvcvsxddp vs5, v4
; CHECK-BE-NEXT: xvcvsxddp vs6, v3 ; CHECK-BE-NEXT: xvcvsxddp vs6, v3
; CHECK-BE-NEXT: xvcvsxddp vs7, v2 ; CHECK-BE-NEXT: xvcvsxddp vs7, v2
; CHECK-BE-NEXT: stxv vs7, 112(r3) ; CHECK-BE-NEXT: stxv vs7, 112(r3)
; CHECK-BE-NEXT: stxv vs6, 96(r3) ; CHECK-BE-NEXT: stxv vs6, 96(r3)
; CHECK-BE-NEXT: stxv vs5, 80(r3) ; CHECK-BE-NEXT: stxv vs5, 80(r3)
; CHECK-BE-NEXT: stxv vs4, 64(r3) ; CHECK-BE-NEXT: stxv vs4, 64(r3)
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
Show All 10 Lines