This is an archive of the discontinued LLVM Phabricator instance.

Differential D61262

[AArch64] Implement MC support for Scalable Vector Extension 2 (SVE2)
AbandonedPublic

Authored by c-rhodes on Apr 29 2019, 7:26 AM.

Details

Reviewers
sdesmalen
SjoerdMeijer
olista01
Summary

This patch adds MC support for the entire Arm SVE2 instruction set, along with
flag changes enabling the feature.

All new instructions are defined in the existing AArch64SVEInstrInfo.td and
SVEInstrFormats.td TableGen files, with the latter containing the more generic
multiclasses.

The majority of instructions are enabled with the sve2 feature flag, although
there are 4 additional architecture features enabling other instructions, these
are: sve2-aes, sve2-sm4, sve2-sha3, and bitperm.

For more information please refer to the ISA spec available at:
https://developer.arm.com/docs/ddi0602/latest

Diff Detail

Event Timeline

c-rhodes created this revision.Apr 29 2019, 7:26 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 29 2019, 7:26 AM
Herald added subscribers: kristina, kristof.beyls, tschuett, javed.absar. · View Herald Transcript
SjoerdMeijer added a comment.Apr 29 2019, 7:54 AM

This is a really big patch! :-) I think reviewing and committing this would be lot easier if you split this patch up (split it up per instruction or instruction group).

sdesmalen added a comment.Apr 30 2019, 1:32 AM

@SjoerdMeijer Yes the patch is indeed quite substantial in size :) In contrast to the original SVE MC patches though, these changes are only new TableGen instruction definitions and encoding classes, corresponding (dis)assembler tests and a few flags. For example, there aren't any code changes to e.g. implement/parse new operand types.

We weren't sure if anyone would actually be interested in reviewing the encodings in detail and figured it may be more of a reference we could point to for those in the LLVM community that follow the work on AArch64's Scalable Vector Extensions and are interested in the instructions added in SVE2. Perhaps that would have been worth a comment in the summary/description :)

The encodings have been quite extensively tested and independently verified.

If you still think there is an argument to split up the patch for reviewing purposes, naturally we'd be happy to do so!

SjoerdMeijer added a subscriber: t.p.northover.Apr 30 2019, 1:52 AM

Oh, I am definitely not interested in checking encodings. Machines are indeed much better in that.

But glancing over the patches would still be useful I think, i.e. the perhaps non-trivial tablegen parts. I think the patches that at least need to be split up are the parts that deal with the TargetParser, AsmParser, etc. With SVE, we still had quite some comments, even though they were mostly minor, but still. But at the moment I can't even look at the code, the patch is too big. And then yes, you can probably start committing all the tablegen discriptions in one go, like you did with SVE.

Perhaps good to get some opinions from @olista01 and @t.p.northover on this too.

javed.absar added inline comments.Apr 30 2019, 2:45 AM
lib/Target/AArch64/AArch64SchedExynosM1.td
27

Instead of repeating this list everywhere you can at top level :

class AArch64UnsupportedF { list<Predicate> F; }
def SVEUnsupported F : AArch64UnsupportedF {

let F = [HasSVE, HasSVE2, ... ];

}

and then in each AArch64SchedX.td ::
list<Predicate> UnsupportedFeatures = SVEUnsupported.F;

TableGen curently does not have globals otherwise it would be simpler, but this idiom works

c-rhodes added a comment.Apr 30 2019, 4:01 AM
lib/Target/AArch64/AArch64SchedExynosM1.td
27

That's neat!

I presume top-level is AArch64.td, I'm happy to make the change there

c-rhodes added a comment.Apr 30 2019, 8:27 AM
In D61262#1483818, @SjoerdMeijer wrote:

But glancing over the patches would still be useful I think, i.e. the perhaps non-trivial tablegen parts. I think the patches that at least need to be split up are the parts that deal with the TargetParser, AsmParser, etc.

The changes to the TargetParser, AsmParser and schedulers are adding new feature support, I think that constitutes one patch and I can split that out.

With SVE, we still had quite some comments, even though they were mostly minor, but still. But at the moment I can't even look at the code, the patch is too big. And then yes, you can probably start committing all the tablegen discriptions in one go, like you did with SVE.

If I split the above into a separate patch the remaining changes will be TableGen descriptions adding new instructions, along with tests. I understand this will still be a huge patch to review so I could break it down by encoding group (~26) as you suggest if that will make things easier.

SjoerdMeijer added a comment.Apr 30 2019, 8:41 AM

I don't have strong opinions on this:

If I split the above into a separate patch the remaining changes will be TableGen descriptions adding new instructions, along with tests. I understand this will still be a huge patch to review so I could break it down by encoding group (~26) as you suggest if that will make things easier.

This could still be one big bang commit, it's mostly tests (and encodings) and I assume too that people will believe this. But yes, this would be helpful I think:

The changes to the TargetParser, AsmParser and schedulers are adding new feature support, I think that constitutes one patch and I can split that out.

Yes, from a closer look, I think too that this is a separate patch. Perhaps the only one, indeed, but it was a bit difficult to see :-)

c-rhodes added a comment.May 3 2019, 8:40 AM

The changes to the TargetParser, AsmParser and schedulers are adding new feature support, I think that constitutes one patch and I can split that out.

Yes, from a closer look, I think too that this is a separate patch. Perhaps the only one, indeed, but it was a bit difficult to see :-)

I have split this into smaller patches, the first patch adding SVE2 feature support can be found here:
https://reviews.llvm.org/D61513

First couple of patches adding instructions:
https://reviews.llvm.org/D61514
https://reviews.llvm.org/D61515

c-rhodes marked an inline comment as done.May 3 2019, 8:45 AM
c-rhodes added inline comments.
lib/Target/AArch64/AArch64SchedExynosM1.td
27

@javed.absar I've split this patch up and implemented your suggestion in this revision: https://reviews.llvm.org/D61513

c-rhodes abandoned this revision.Jun 3 2019, 3:42 AM

This was split up into smaller patches, all have now been merged. Abandoning this revision.

Revision Contents

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Diff 197105

include/llvm/Support/AArch64TargetParser.h

Context not available.
AEK_SSBS = 1 << 20, AEK_SSBS = 1 << 20,
AEK_SB = 1 << 21, AEK_SB = 1 << 21,
AEK_PREDRES = 1 << 22, AEK_PREDRES = 1 << 22,
AEK_SVE2 = 1 << 23,
AEK_SVE2AES = 1 << 24,
AEK_SVE2SM4 = 1 << 25,
AEK_SVE2SHA3 = 1 << 26,
AEK_BITPERM = 1 << 27,
}; };
enum class ArchKind { enum class ArchKind {
Context not available.

include/llvm/Support/AArch64TargetParser.def

Context not available.
#define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) #define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)
#endif #endif
// FIXME: This would be nicer were it tablegen // FIXME: This would be nicer were it tablegen
AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, nullptr, nullptr) AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, nullptr, nullptr)
AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE, nullptr, nullptr) AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE, nullptr, nullptr)
AARCH64_ARCH_EXT_NAME("crc", AArch64::AEK_CRC, "+crc", "-crc") AARCH64_ARCH_EXT_NAME("crc", AArch64::AEK_CRC, "+crc", "-crc")
AARCH64_ARCH_EXT_NAME("lse", AArch64::AEK_LSE, "+lse", "-lse") AARCH64_ARCH_EXT_NAME("lse", AArch64::AEK_LSE, "+lse", "-lse")
AARCH64_ARCH_EXT_NAME("rdm", AArch64::AEK_RDM, "+rdm", "-rdm") AARCH64_ARCH_EXT_NAME("rdm", AArch64::AEK_RDM, "+rdm", "-rdm")
AARCH64_ARCH_EXT_NAME("crypto", AArch64::AEK_CRYPTO, "+crypto","-crypto") AARCH64_ARCH_EXT_NAME("crypto", AArch64::AEK_CRYPTO, "+crypto","-crypto")
AARCH64_ARCH_EXT_NAME("sm4", AArch64::AEK_SM4, "+sm4", "-sm4") AARCH64_ARCH_EXT_NAME("sm4", AArch64::AEK_SM4, "+sm4", "-sm4")
AARCH64_ARCH_EXT_NAME("sha3", AArch64::AEK_SHA3, "+sha3", "-sha3") AARCH64_ARCH_EXT_NAME("sha3", AArch64::AEK_SHA3, "+sha3", "-sha3")
AARCH64_ARCH_EXT_NAME("sha2", AArch64::AEK_SHA2, "+sha2", "-sha2") AARCH64_ARCH_EXT_NAME("sha2", AArch64::AEK_SHA2, "+sha2", "-sha2")
AARCH64_ARCH_EXT_NAME("aes", AArch64::AEK_AES, "+aes", "-aes") AARCH64_ARCH_EXT_NAME("aes", AArch64::AEK_AES, "+aes", "-aes")
AARCH64_ARCH_EXT_NAME("dotprod", AArch64::AEK_DOTPROD, "+dotprod","-dotprod") AARCH64_ARCH_EXT_NAME("dotprod", AArch64::AEK_DOTPROD, "+dotprod","-dotprod")
AARCH64_ARCH_EXT_NAME("fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8") AARCH64_ARCH_EXT_NAME("fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8")
AARCH64_ARCH_EXT_NAME("simd", AArch64::AEK_SIMD, "+neon", "-neon") AARCH64_ARCH_EXT_NAME("simd", AArch64::AEK_SIMD, "+neon", "-neon")
AARCH64_ARCH_EXT_NAME("fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16") AARCH64_ARCH_EXT_NAME("fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16")
AARCH64_ARCH_EXT_NAME("fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml") AARCH64_ARCH_EXT_NAME("fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml")
AARCH64_ARCH_EXT_NAME("profile", AArch64::AEK_PROFILE, "+spe", "-spe") AARCH64_ARCH_EXT_NAME("profile", AArch64::AEK_PROFILE, "+spe", "-spe")
AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras") AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras")
AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve") AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve")
AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc") AARCH64_ARCH_EXT_NAME("sve2", AArch64::AEK_SVE2, "+sve2", "-sve2")
AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand") AARCH64_ARCH_EXT_NAME("sve2-aes", AArch64::AEK_SVE2AES, "+sve2-aes", "-sve2-aes")
AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte") AARCH64_ARCH_EXT_NAME("sve2-sm4", AArch64::AEK_SVE2SM4, "+sve2-sm4", "-sve2-sm4")
AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs") AARCH64_ARCH_EXT_NAME("sve2-sha3", AArch64::AEK_SVE2SHA3, "+sve2-sha3", "-sve2-sha3")
AARCH64_ARCH_EXT_NAME("sb", AArch64::AEK_SB, "+sb", "-sb") AARCH64_ARCH_EXT_NAME("bitperm", AArch64::AEK_BITPERM, "+bitperm", "-bitperm")
AARCH64_ARCH_EXT_NAME("predres", AArch64::AEK_PREDRES, "+predres", "-predres") AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc")
AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand")
AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte")
AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs")
AARCH64_ARCH_EXT_NAME("sb", AArch64::AEK_SB, "+sb", "-sb")
AARCH64_ARCH_EXT_NAME("predres", AArch64::AEK_PREDRES, "+predres", "-predres")
#undef AARCH64_ARCH_EXT_NAME #undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME #ifndef AARCH64_CPU_NAME
Context not available.

include/llvm/Support/ARMTargetParser.h

Context not available.
AEK_AES = 1 << 16, AEK_AES = 1 << 16,
AEK_FP16FML = 1 << 17, AEK_FP16FML = 1 << 17,
AEK_SB = 1 << 18, AEK_SB = 1 << 18,
AEK_SVE2 = 1 << 19,
AEK_SVE2AES = 1 << 20,
AEK_SVE2SM4 = 1 << 21,
AEK_SVE2SHA3 = 1 << 22,
AEK_BITPERM = 1 << 23,
// Unsupported extensions. // Unsupported extensions.
AEK_OS = 0x8000000, AEK_OS = 0x8000000,
AEK_IWMMXT = 0x10000000, AEK_IWMMXT = 0x10000000,
Context not available.

lib/Support/AArch64TargetParser.cpp

Context not available.
Features.push_back("+rdm"); Features.push_back("+rdm");
if (Extensions & AEK_SVE) if (Extensions & AEK_SVE)
Features.push_back("+sve"); Features.push_back("+sve");
if (Extensions & AEK_SVE2)
Features.push_back("+sve2");
if (Extensions & AEK_SVE2AES)
Features.push_back("+sve2-aes");
if (Extensions & AEK_SVE2SM4)
Features.push_back("+sve2-sm4");
if (Extensions & AEK_SVE2SHA3)
Features.push_back("+sve2-sha3");
if (Extensions & AEK_BITPERM)
Features.push_back("+bitperm");
if (Extensions & AEK_RCPC) if (Extensions & AEK_RCPC)
Features.push_back("+rcpc"); Features.push_back("+rcpc");
Context not available.

lib/Target/AArch64/AArch64.td

Context not available.
def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
"Enable Scalable Vector Extension (SVE) instructions">; "Enable Scalable Vector Extension (SVE) instructions">;
def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true",
"Enable Scalable Vector Extension 2 (SVE2) instructions", [FeatureSVE]>;
def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true",
"Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>;
def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true",
"Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true",
"Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>;
def FeatureSVE2BitPerm : SubtargetFeature<"bitperm", "HasSVE2BitPerm", "true",
"Enable bit permutation SVE2 instructions", [FeatureSVE2]>;
def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
"Has zero-cycle register moves">; "Has zero-cycle register moves">;
def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true", def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
Context not available.

lib/Target/AArch64/AArch64InstrInfo.td

Context not available.
"fuse-aes">; "fuse-aes">;
def HasSVE : Predicate<"Subtarget->hasSVE()">, def HasSVE : Predicate<"Subtarget->hasSVE()">,
AssemblerPredicate<"FeatureSVE", "sve">; AssemblerPredicate<"FeatureSVE", "sve">;
def HasSVE2 : Predicate<"Subtarget->hasSVE2()">,
AssemblerPredicate<"FeatureSVE2", "sve2">;
def HasSVE2AES : Predicate<"Subtarget->hasSVE2AES()">,
AssemblerPredicate<"FeatureSVE2AES", "sve2-aes">;
def HasSVE2SM4 : Predicate<"Subtarget->hasSVE2SM4()">,
AssemblerPredicate<"FeatureSVE2SM4", "sve2-sm4">;
def HasSVE2SHA3 : Predicate<"Subtarget->hasSVE2SHA3()">,
AssemblerPredicate<"FeatureSVE2SHA3", "sve2-sha3">;
def HasSVE2BitPerm : Predicate<"Subtarget->hasSVE2()">,
AssemblerPredicate<"FeatureSVE2BitPerm", "bitperm">;
def HasRCPC : Predicate<"Subtarget->hasRCPC()">, def HasRCPC : Predicate<"Subtarget->hasRCPC()">,
AssemblerPredicate<"FeatureRCPC", "rcpc">; AssemblerPredicate<"FeatureRCPC", "rcpc">;
def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">, def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">,
Context not available.

lib/Target/AArch64/AArch64SVEInstrInfo.td

Context not available.
defm LSL_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b11, "lsl">; defm LSL_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b11, "lsl">;
// Predicated shifts // Predicated shifts
defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b000, "asr">; defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0000, "asr">;
defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b001, "lsr">; defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0001, "lsr">;
defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b011, "lsl">; defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0011, "lsl">;
defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b100, "asrd">; defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b0100, "asrd">;
defm ASR_ZPmZ : sve_int_bin_pred_shift<0b000, "asr">; defm ASR_ZPmZ : sve_int_bin_pred_shift<0b000, "asr">;
defm LSR_ZPmZ : sve_int_bin_pred_shift<0b001, "lsr">; defm LSR_ZPmZ : sve_int_bin_pred_shift<0b001, "lsr">;
Context not available.
def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn", def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
(FCMGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>; (FCMGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
} }
let Predicates = [HasSVE2] in {
// SVE2 integer multiply-add (indexed)
defm MLA_ZZZI : sve_int_mla_by_indexed_elem<0b01, 0b0, "mla">;
defm MLS_ZZZI : sve_int_mla_by_indexed_elem<0b01, 0b1, "mls">;
// SVE2 saturating multiply-add high (indexed)
defm SQRDMLAH_ZZZI : sve_int_mla_by_indexed_elem<0b10, 0b0, "sqrdmlah">;
defm SQRDMLSH_ZZZI : sve_int_mla_by_indexed_elem<0b10, 0b1, "sqrdmlsh">;
// SVE2 saturating multiply-add high (vectors, unpredicated)
defm SQRDMLAH_ZZZ : sve_int_mla<0b0, "sqrdmlah">;
defm SQRDMLSH_ZZZ : sve_int_mla<0b1, "sqrdmlsh">;
// SVE2 integer multiply (indexed)
defm MUL_ZZZI : sve_int_mul_by_indexed_elem<0b1110, "mul">;
// SVE2 saturating multiply high (indexed)
defm SQDMULH_ZZZI : sve_int_mul_by_indexed_elem<0b1100, "sqdmulh">;
defm SQRDMULH_ZZZI : sve_int_mul_by_indexed_elem<0b1101, "sqrdmulh">;
// SVE2 signed saturating doubling multiply high (unpredicated)
defm SQDMULH_ZZZ : sve_int_mul<0b100, "sqdmulh">;
defm SQRDMULH_ZZZ : sve_int_mul<0b101, "sqrdmulh">;
// SVE2 integer multiply vectors (unpredicated)
defm MUL_ZZZ : sve_int_mul<0b000, "mul">;
defm SMULH_ZZZ : sve_int_mul<0b010, "smulh">;
defm UMULH_ZZZ : sve_int_mul<0b011, "umulh">;
def PMUL_ZZZ_B : sve_int_mul<0b00, 0b001, "pmul", ZPR8>;
// SVE2 complex integer dot product (indexed)
defm CDOT_ZZZI : sve_cintx_dot_by_indexed_elem<"cdot">;
// SVE2 complex integer dot product
defm CDOT_ZZZ : sve_cintx_dot<"cdot">;
// SVE2 complex integer multiply-add (indexed)
defm CMLA_ZZZI : sve_cmla_by_indexed_elem<0b0, "cmla">;
// SVE2 complex saturating multiply-add (indexed)
defm SQRDCMLAH_ZZZI : sve_cmla_by_indexed_elem<0b1, "sqrdcmlah">;
// SVE2 complex integer multiply-add
defm CMLA_ZZZ : sve_int_cmla<0b0, "cmla">;
defm SQRDCMLAH_ZZZ : sve_int_cmla<0b1, "sqrdcmlah">;
// SVE2 integer multiply long (indexed)
defm SMULLB_ZZZI : sve_int_mul_long_by_indexed_elem<0b000, "smullb">;
defm SMULLT_ZZZI : sve_int_mul_long_by_indexed_elem<0b001, "smullt">;
defm UMULLB_ZZZI : sve_int_mul_long_by_indexed_elem<0b010, "umullb">;
defm UMULLT_ZZZI : sve_int_mul_long_by_indexed_elem<0b011, "umullt">;
// SVE2 saturating multiply (indexed)
defm SQDMULLB_ZZZI : sve_int_mul_long_by_indexed_elem<0b100, "sqdmullb">;
defm SQDMULLT_ZZZI : sve_int_mul_long_by_indexed_elem<0b101, "sqdmullt">;
// SVE2 integer multiply-add long (indexed)
defm SMLALB_ZZZI : sve_int_mla_long_by_indexed_elem<0b1000, "smlalb">;
defm SMLALT_ZZZI : sve_int_mla_long_by_indexed_elem<0b1001, "smlalt">;
defm UMLALB_ZZZI : sve_int_mla_long_by_indexed_elem<0b1010, "umlalb">;
defm UMLALT_ZZZI : sve_int_mla_long_by_indexed_elem<0b1011, "umlalt">;
defm SMLSLB_ZZZI : sve_int_mla_long_by_indexed_elem<0b1100, "smlslb">;
defm SMLSLT_ZZZI : sve_int_mla_long_by_indexed_elem<0b1101, "smlslt">;
defm UMLSLB_ZZZI : sve_int_mla_long_by_indexed_elem<0b1110, "umlslb">;
defm UMLSLT_ZZZI : sve_int_mla_long_by_indexed_elem<0b1111, "umlslt">;
// SVE2 integer multiply-add long (vectors, unpredicated)
defm SMLALB_ZZZ : sve_int_mla_long<0b10000, "smlalb">;
defm SMLALT_ZZZ : sve_int_mla_long<0b10001, "smlalt">;
defm UMLALB_ZZZ : sve_int_mla_long<0b10010, "umlalb">;
defm UMLALT_ZZZ : sve_int_mla_long<0b10011, "umlalt">;
defm SMLSLB_ZZZ : sve_int_mla_long<0b10100, "smlslb">;
defm SMLSLT_ZZZ : sve_int_mla_long<0b10101, "smlslt">;
defm UMLSLB_ZZZ : sve_int_mla_long<0b10110, "umlslb">;
defm UMLSLT_ZZZ : sve_int_mla_long<0b10111, "umlslt">;
// SVE2 saturating multiply-add (indexed)
defm SQDMLALB_ZZZI : sve_int_mla_long_by_indexed_elem<0b0100, "sqdmlalb">;
defm SQDMLALT_ZZZI : sve_int_mla_long_by_indexed_elem<0b0101, "sqdmlalt">;
defm SQDMLSLB_ZZZI : sve_int_mla_long_by_indexed_elem<0b0110, "sqdmlslb">;
defm SQDMLSLT_ZZZI : sve_int_mla_long_by_indexed_elem<0b0111, "sqdmlslt">;
// SVE2 saturating multiply-add (vectors, unpredicated)
defm SQDMLALB_ZZZ : sve_int_mla_long<0b11000, "sqdmlalb">;
defm SQDMLALT_ZZZ : sve_int_mla_long<0b11001, "sqdmlalt">;
defm SQDMLSLB_ZZZ : sve_int_mla_long<0b11010, "sqdmlslb">;
defm SQDMLSLT_ZZZ : sve_int_mla_long<0b11011, "sqdmlslt">;
// SVE2 saturating multiply-add interleaved long
defm SQDMLALBT_ZZZ : sve_int_mla_long<0b00010, "sqdmlalbt">;
defm SQDMLSLBT_ZZZ : sve_int_mla_long<0b00011, "sqdmlslbt">;
// SVE2 integer halving add/subtract (predicated)
defm SHADD_ZPmZ : sve2_int_arith_pred<0b100000, "shadd">;
defm UHADD_ZPmZ : sve2_int_arith_pred<0b100010, "uhadd">;
defm SHSUB_ZPmZ : sve2_int_arith_pred<0b100100, "shsub">;
defm UHSUB_ZPmZ : sve2_int_arith_pred<0b100110, "uhsub">;
defm SRHADD_ZPmZ : sve2_int_arith_pred<0b101000, "srhadd">;
defm URHADD_ZPmZ : sve2_int_arith_pred<0b101010, "urhadd">;
defm SHSUBR_ZPmZ : sve2_int_arith_pred<0b101100, "shsubr">;
defm UHSUBR_ZPmZ : sve2_int_arith_pred<0b101110, "uhsubr">;
// SVE2 integer pairwise add and accumulate long
defm SADALP_ZPmZ : sve2_int_sadd_long_accum_pairwise<0, "sadalp">;
defm UADALP_ZPmZ : sve2_int_sadd_long_accum_pairwise<1, "uadalp">;
// SVE2 integer pairwise arithmetic
defm ADDP_ZPmZ : sve2_int_arith_pred<0b100011, "addp">;
defm SMAXP_ZPmZ : sve2_int_arith_pred<0b101001, "smaxp">;
defm UMAXP_ZPmZ : sve2_int_arith_pred<0b101011, "umaxp">;
defm SMINP_ZPmZ : sve2_int_arith_pred<0b101101, "sminp">;
defm UMINP_ZPmZ : sve2_int_arith_pred<0b101111, "uminp">;
// SVE2 integer unary operations (predicated)
defm URECPE_ZPmZ : sve2_int_un_pred_arit_s<0b000, "urecpe">;
defm URSQRTE_ZPmZ : sve2_int_un_pred_arit_s<0b001, "ursqrte">;
defm SQABS_ZPmZ : sve2_int_un_pred_arit<0b100, "sqabs">;
defm SQNEG_ZPmZ : sve2_int_un_pred_arit<0b101, "sqneg">;
// SVE2 saturating add/subtract
defm SQADD_ZPmZ : sve2_int_arith_pred<0b110000, "sqadd">;
defm UQADD_ZPmZ : sve2_int_arith_pred<0b110010, "uqadd">;
defm SQSUB_ZPmZ : sve2_int_arith_pred<0b110100, "sqsub">;
defm UQSUB_ZPmZ : sve2_int_arith_pred<0b110110, "uqsub">;
defm SUQADD_ZPmZ : sve2_int_arith_pred<0b111000, "suqadd">;
defm USQADD_ZPmZ : sve2_int_arith_pred<0b111010, "usqadd">;
defm SQSUBR_ZPmZ : sve2_int_arith_pred<0b111100, "sqsubr">;
defm UQSUBR_ZPmZ : sve2_int_arith_pred<0b111110, "uqsubr">;
// SVE2 saturating/rounding bitwise shift left (predicated)
defm SRSHL_ZPmZ : sve2_int_arith_pred<0b000100, "srshl">;
defm URSHL_ZPmZ : sve2_int_arith_pred<0b000110, "urshl">;
defm SRSHLR_ZPmZ : sve2_int_arith_pred<0b001100, "srshlr">;
defm URSHLR_ZPmZ : sve2_int_arith_pred<0b001110, "urshlr">;
defm SQSHL_ZPmZ : sve2_int_arith_pred<0b010000, "sqshl">;
defm UQSHL_ZPmZ : sve2_int_arith_pred<0b010010, "uqshl">;
defm SQRSHL_ZPmZ : sve2_int_arith_pred<0b010100, "sqrshl">;
defm UQRSHL_ZPmZ : sve2_int_arith_pred<0b010110, "uqrshl">;
defm SQSHLR_ZPmZ : sve2_int_arith_pred<0b011000, "sqshlr">;
defm UQSHLR_ZPmZ : sve2_int_arith_pred<0b011010, "uqshlr">;
defm SQRSHLR_ZPmZ : sve2_int_arith_pred<0b011100, "sqrshlr">;
defm UQRSHLR_ZPmZ : sve2_int_arith_pred<0b011110, "uqrshlr">;
// SVE2 integer add/subtract long
defm SADDLB_ZZZ : sve2_wide_int_arith_long<0b00000, "saddlb">;
defm SADDLT_ZZZ : sve2_wide_int_arith_long<0b00001, "saddlt">;
defm UADDLB_ZZZ : sve2_wide_int_arith_long<0b00010, "uaddlb">;
defm UADDLT_ZZZ : sve2_wide_int_arith_long<0b00011, "uaddlt">;
defm SSUBLB_ZZZ : sve2_wide_int_arith_long<0b00100, "ssublb">;
defm SSUBLT_ZZZ : sve2_wide_int_arith_long<0b00101, "ssublt">;
defm USUBLB_ZZZ : sve2_wide_int_arith_long<0b00110, "usublb">;
defm USUBLT_ZZZ : sve2_wide_int_arith_long<0b00111, "usublt">;
defm SABDLB_ZZZ : sve2_wide_int_arith_long<0b01100, "sabdlb">;
defm SABDLT_ZZZ : sve2_wide_int_arith_long<0b01101, "sabdlt">;
defm UABDLB_ZZZ : sve2_wide_int_arith_long<0b01110, "uabdlb">;
defm UABDLT_ZZZ : sve2_wide_int_arith_long<0b01111, "uabdlt">;
// SVE2 integer add/subtract wide
defm SADDWB_ZZZ : sve2_wide_int_arith_wide<0b000, "saddwb">;
defm SADDWT_ZZZ : sve2_wide_int_arith_wide<0b001, "saddwt">;
defm UADDWB_ZZZ : sve2_wide_int_arith_wide<0b010, "uaddwb">;
defm UADDWT_ZZZ : sve2_wide_int_arith_wide<0b011, "uaddwt">;
defm SSUBWB_ZZZ : sve2_wide_int_arith_wide<0b100, "ssubwb">;
defm SSUBWT_ZZZ : sve2_wide_int_arith_wide<0b101, "ssubwt">;
defm USUBWB_ZZZ : sve2_wide_int_arith_wide<0b110, "usubwb">;
defm USUBWT_ZZZ : sve2_wide_int_arith_wide<0b111, "usubwt">;
// SVE2 integer multiply long
defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">;
defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">;
defm SMULLB_ZZZ : sve2_wide_int_arith_long<0b11100, "smullb">;
defm SMULLT_ZZZ : sve2_wide_int_arith_long<0b11101, "smullt">;
defm UMULLB_ZZZ : sve2_wide_int_arith_long<0b11110, "umullb">;
defm UMULLT_ZZZ : sve2_wide_int_arith_long<0b11111, "umullt">;
defm PMULLB_ZZZ : sve2_pmul_long<0b0, "pmullb">;
defm PMULLT_ZZZ : sve2_pmul_long<0b1, "pmullt">;
// SVE2 bitwise shift and insert
defm SRI_ZZI : sve2_int_bin_cons_shift_imm_right<0b0, "sri">;
defm SLI_ZZI : sve2_int_bin_cons_shift_imm_left< 0b1, "sli">;
// SVE2 bitwise shift right and accumulate
defm SSRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b00, "ssra">;
defm USRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b01, "usra">;
defm SRSRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b10, "srsra">;
defm URSRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b11, "ursra">;
// SVE2 complex integer add
defm CADD_ZZI : sve2_int_cadd<0b0, "cadd">;
defm SQCADD_ZZI : sve2_int_cadd<0b1, "sqcadd">;
// SVE2 integer absolute difference and accumulate
defm SABA_ZZZ : sve2_int_absdiff_accum<0b0, "saba">;
defm UABA_ZZZ : sve2_int_absdiff_accum<0b1, "uaba">;
// SVE2 integer absolute difference and accumulate long
defm SABALB_ZZZ : sve2_int_absdiff_accum_long<0b00, "sabalb">;
defm SABALT_ZZZ : sve2_int_absdiff_accum_long<0b01, "sabalt">;
defm UABALB_ZZZ : sve2_int_absdiff_accum_long<0b10, "uabalb">;
defm UABALT_ZZZ : sve2_int_absdiff_accum_long<0b11, "uabalt">;
// SVE2 integer add/subtract long with carry
defm ADCLB_ZZZ : sve2_int_addsub_long_carry<0b00, "adclb">;
defm ADCLT_ZZZ : sve2_int_addsub_long_carry<0b01, "adclt">;
defm SBCLB_ZZZ : sve2_int_addsub_long_carry<0b10, "sbclb">;
defm SBCLT_ZZZ : sve2_int_addsub_long_carry<0b11, "sbclt">;
// SVE2 bitwise shift right narrow
defm SQSHRUNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0000, "sqshrunb">;
defm SQSHRUNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0001, "sqshrunt">;
defm SQRSHRUNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0010, "sqrshrunb">;
defm SQRSHRUNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0011, "sqrshrunt">;
defm SHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0100, "shrnb">;
defm SHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0101, "shrnt">;
defm RSHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0110, "rshrnb">;
defm RSHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0111, "rshrnt">;
defm SQSHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1000, "sqshrnb">;
defm SQSHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1001, "sqshrnt">;
defm SQRSHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1010, "sqrshrnb">;
defm SQRSHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1011, "sqrshrnt">;
defm UQSHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1100, "uqshrnb">;
defm UQSHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1101, "uqshrnt">;
defm UQRSHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1110, "uqrshrnb">;
defm UQRSHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1111, "uqrshrnt">;
// SVE2 integer add/subtract narrow high part
defm ADDHNB_ZZZ : sve2_int_addsub_narrow_high<0b000, "addhnb">;
defm ADDHNT_ZZZ : sve2_int_addsub_narrow_high<0b001, "addhnt">;
defm RADDHNB_ZZZ : sve2_int_addsub_narrow_high<0b010, "raddhnb">;
defm RADDHNT_ZZZ : sve2_int_addsub_narrow_high<0b011, "raddhnt">;
defm SUBHNB_ZZZ : sve2_int_addsub_narrow_high<0b100, "subhnb">;
defm SUBHNT_ZZZ : sve2_int_addsub_narrow_high<0b101, "subhnt">;
defm RSUBHNB_ZZZ : sve2_int_addsub_narrow_high<0b110, "rsubhnb">;
defm RSUBHNT_ZZZ : sve2_int_addsub_narrow_high<0b111, "rsubhnt">;
// SVE2 saturating extract narrow
defm SQXTNB_ZZ : sve2_int_sat_extract_narrow<0b000, "sqxtnb">;
defm SQXTNT_ZZ : sve2_int_sat_extract_narrow<0b001, "sqxtnt">;
defm UQXTNB_ZZ : sve2_int_sat_extract_narrow<0b010, "uqxtnb">;
defm UQXTNT_ZZ : sve2_int_sat_extract_narrow<0b011, "uqxtnt">;
defm SQXTUNB_ZZ : sve2_int_sat_extract_narrow<0b100, "sqxtunb">;
defm SQXTUNT_ZZ : sve2_int_sat_extract_narrow<0b101, "sqxtunt">;
// SVE2 character match
defm MATCH_PPzZZ : sve2_char_match<0b0, "match">;
defm NMATCH_PPzZZ : sve2_char_match<0b1, "nmatch">;
// SVE2 bitwise exclusive-or interleaved
defm EORBT_ZZZ : sve2_bitwise_xor_interleaved<0b0, "eorbt">;
defm EORTB_ZZZ : sve2_bitwise_xor_interleaved<0b1, "eortb">;
// SVE2 bitwise shift left long
defm SSHLLB_ZZI : sve2_bitwise_shift_left_long<0b00, "sshllb">;
defm SSHLLT_ZZI : sve2_bitwise_shift_left_long<0b01, "sshllt">;
defm USHLLB_ZZI : sve2_bitwise_shift_left_long<0b10, "ushllb">;
defm USHLLT_ZZI : sve2_bitwise_shift_left_long<0b11, "ushllt">;
// SVE2 integer add/subtract interleaved long
defm SADDLBT_ZZZ : sve2_misc_int_addsub_long_interleaved<0b00, "saddlbt">;
defm SSUBLBT_ZZZ : sve2_misc_int_addsub_long_interleaved<0b10, "ssublbt">;
defm SSUBLTB_ZZZ : sve2_misc_int_addsub_long_interleaved<0b11, "ssubltb">;
// SVE2 histogram generation (segment)
def HISTSEG_ZZZ : sve2_hist_gen_segment<"histseg">;
// SVE2 histogram generation (vector)
defm HISTCNT_ZPzZZ : sve2_hist_gen_vector<"histcnt">;
// SVE2 floating-point convert precision
defm FCVTXNT_ZPmZ : sve2_fp_convert_down_odd_rounding<"fcvtxnt">;
defm FCVTNT_ZPmZ : sve2_fp_convert_down_narrow<"fcvtnt">;
defm FCVTLT_ZPmZ : sve2_fp_convert_up_long<"fcvtlt">;
// SVE2 floating-point pairwise operations
defm FADDP_ZPmZZ : sve2_fp_pairwise_pred<0b000, "faddp">;
defm FMAXNMP_ZPmZZ : sve2_fp_pairwise_pred<0b100, "fmaxnmp">;
defm FMINNMP_ZPmZZ : sve2_fp_pairwise_pred<0b101, "fminnmp">;
defm FMAXP_ZPmZZ : sve2_fp_pairwise_pred<0b110, "fmaxp">;
defm FMINP_ZPmZZ : sve2_fp_pairwise_pred<0b111, "fminp">;
// SVE2 floating-point multiply-add long (indexed)
def FMLALB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b00, "fmlalb">;
def FMLALT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b01, "fmlalt">;
def FMLSLB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b10, "fmlslb">;
def FMLSLT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b11, "fmlslt">;
// SVE2 floating-point multiply-add long
def FMLALB_ZZZ_SHH : sve2_fp_mla_long<0b00, "fmlalb">;
def FMLALT_ZZZ_SHH : sve2_fp_mla_long<0b01, "fmlalt">;
def FMLSLB_ZZZ_SHH : sve2_fp_mla_long<0b10, "fmlslb">;
def FMLSLT_ZZZ_SHH : sve2_fp_mla_long<0b11, "fmlslt">;
// SVE2 bitwise ternary operations
defm EOR3_ZZZZ_D : sve2_int_bitwise_ternary_op<0b000, "eor3">;
defm BCAX_ZZZZ_D : sve2_int_bitwise_ternary_op<0b010, "bcax">;
def BSL_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b001, "bsl">;
def BSL1N_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b011, "bsl1n">;
def BSL2N_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b101, "bsl2n">;
def NBSL_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b111, "nbsl">;
// sve_int_rotate_imm
defm XAR_ZZZI : sve2_int_rotate_right_imm<"xar">;
// SVE2 extract vector (immediate offset, constructive)
def EXT_ZZI_B : sve2_int_perm_extract_i_cons<"ext">;
// SVE floating-point convert precision
def FCVTX_ZPmZ_DtoS : sve_fp_2op_p_zd<0b0001010, "fcvtx", ZPR64, ZPR32, ElementSizeD>;
// SVE floating-point convert to integer
defm FLOGB_ZPmZ : sve2_fp_flogb<"flogb">;
// Non-temporal contiguous loads (vector + register)
defm LDNT1SB_ZZR_S : sve2_mem_cldnt_vs<0b00000, "ldnt1sb", Z_s, ZPR32>;
defm LDNT1B_ZZR_S : sve2_mem_cldnt_vs<0b00001, "ldnt1b", Z_s, ZPR32>;
defm LDNT1SH_ZZR_S : sve2_mem_cldnt_vs<0b00100, "ldnt1sh", Z_s, ZPR32>;
defm LDNT1H_ZZR_S : sve2_mem_cldnt_vs<0b00101, "ldnt1h", Z_s, ZPR32>;
defm LDNT1W_ZZR_S : sve2_mem_cldnt_vs<0b01001, "ldnt1w", Z_s, ZPR32>;
defm LDNT1SB_ZZR_D : sve2_mem_cldnt_vs<0b10000, "ldnt1sb", Z_d, ZPR64>;
defm LDNT1B_ZZR_D : sve2_mem_cldnt_vs<0b10010, "ldnt1b", Z_d, ZPR64>;
defm LDNT1SH_ZZR_D : sve2_mem_cldnt_vs<0b10100, "ldnt1sh", Z_d, ZPR64>;
defm LDNT1H_ZZR_D : sve2_mem_cldnt_vs<0b10110, "ldnt1h", Z_d, ZPR64>;
defm LDNT1SW_ZZR_D : sve2_mem_cldnt_vs<0b11000, "ldnt1sw", Z_d, ZPR64>;
defm LDNT1W_ZZR_D : sve2_mem_cldnt_vs<0b11010, "ldnt1w", Z_d, ZPR64>;
defm LDNT1D_ZZR_D : sve2_mem_cldnt_vs<0b11110, "ldnt1d", Z_d, ZPR64>;
// SVE2 vector splice (constructive)
defm SPLICE_ZPZZ : sve2_int_perm_splice_cons<"splice">;
// Predicated shifts
defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">;
defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">;
defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">;
// Non-temporal contiguous stores (vector + register)
defm STNT1B_ZZR_S : sve2_mem_cstnt_vs<0b001, "stnt1b", Z_s, ZPR32>;
defm STNT1H_ZZR_S : sve2_mem_cstnt_vs<0b011, "stnt1h", Z_s, ZPR32>;
defm STNT1W_ZZR_S : sve2_mem_cstnt_vs<0b101, "stnt1w", Z_s, ZPR32>;
defm STNT1B_ZZR_D : sve2_mem_cstnt_vs<0b000, "stnt1b", Z_d, ZPR64>;
defm STNT1H_ZZR_D : sve2_mem_cstnt_vs<0b010, "stnt1h", Z_d, ZPR64>;
defm STNT1W_ZZR_D : sve2_mem_cstnt_vs<0b100, "stnt1w", Z_d, ZPR64>;
defm STNT1D_ZZR_D : sve2_mem_cstnt_vs<0b110, "stnt1d", Z_d, ZPR64>;
// SVE table lookup (three sources)
defm TBL_ZZZZ : sve2_int_perm_tbl<"tbl">;
defm TBX_ZZZ : sve2_int_perm_tbx<"tbx">;
// SVE integer compare scalar count and limit
defm WHILEGE_PWW : sve_int_while4_rr<0b000, "whilege">;
defm WHILEGT_PWW : sve_int_while4_rr<0b001, "whilegt">;
defm WHILEHS_PWW : sve_int_while4_rr<0b100, "whilehs">;
defm WHILEHI_PWW : sve_int_while4_rr<0b101, "whilehi">;
defm WHILEGE_PXX : sve_int_while8_rr<0b000, "whilege">;
defm WHILEGT_PXX : sve_int_while8_rr<0b001, "whilegt">;
defm WHILEHS_PXX : sve_int_while8_rr<0b100, "whilehs">;
defm WHILEHI_PXX : sve_int_while8_rr<0b101, "whilehi">;
// SVE pointer conflict compare
defm WHILEWR_PXX : sve2_int_while_rr<0b0, "whilewr">;
defm WHILERW_PXX : sve2_int_while_rr<0b1, "whilerw">;
}
let Predicates = [HasSVE2AES] in {
// SVE2 crypto destructive binary operations
def AESE_ZZZ_B : sve2_crypto_des_bin_op<0b00, "aese", ZPR8>;
def AESD_ZZZ_B : sve2_crypto_des_bin_op<0b01, "aesd", ZPR8>;
// SVE2 crypto unary operations
def AESMC_ZZ_B : sve2_crypto_unary_op<0b0, "aesmc">;
def AESIMC_ZZ_B : sve2_crypto_unary_op<0b1, "aesimc">;
// PMULLB and PMULLT instructions which operate with 64-bit source and
// 128-bit destination elements are enabled with crypto extensions, similar
// to NEON PMULL2 instruction.
def PMULLB_ZZZ_Q : sve2_wide_int_arith<0b00, 0b11010, "pmullb",
ZPR128, ZPR64, ZPR64>;
def PMULLT_ZZZ_Q : sve2_wide_int_arith<0b00, 0b11011, "pmullt",
ZPR128, ZPR64, ZPR64>;
}
let Predicates = [HasSVE2SM4] in {
// SVE2 crypto constructive binary operations
def SM4EKEY_ZZZ_S : sve2_crypto_cons_bin_op<0b0, "sm4ekey", ZPR32>;
// SVE2 crypto destructive binary operations
def SM4E_ZZZ_S : sve2_crypto_des_bin_op<0b10, "sm4e", ZPR32>;
}
let Predicates = [HasSVE2SHA3] in {
// SVE2 crypto constructive binary operations
def RAX1_ZZZ_D : sve2_crypto_cons_bin_op<0b1, "rax1", ZPR64>;
}
let Predicates = [HasSVE2BitPerm] in {
// SVE2 bitwise permute
defm BEXT_ZZZ : sve2_misc_bitwise<0b1100, "bext">;
defm BDEP_ZZZ : sve2_misc_bitwise<0b1101, "bdep">;
defm BGRP_ZZZ : sve2_misc_bitwise<0b1110, "bgrp">;
}
Context not available.

lib/Target/AArch64/AArch64SchedA53.td

Context not available.
// v 1.0 Spreadsheet // v 1.0 Spreadsheet
let CompleteModel = 1; let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE]; list<Predicate> UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES,
HasSVE2SM4, HasSVE2SHA3,
HasSVE2BitPerm];
} }
Context not available.

lib/Target/AArch64/AArch64SchedA57.td

Context not available.
let LoopMicroOpBufferSize = 16; let LoopMicroOpBufferSize = 16;
let CompleteModel = 1; let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE]; list<Predicate> UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES,
HasSVE2SM4, HasSVE2SHA3,
HasSVE2BitPerm];
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Context not available.

lib/Target/AArch64/AArch64SchedCyclone.td

Context not available.
let MispredictPenalty = 16; // 14-19 cycles are typical. let MispredictPenalty = 16; // 14-19 cycles are typical.
let CompleteModel = 1; let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE]; list<Predicate> UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES,
HasSVE2SM4, HasSVE2SHA3,
HasSVE2BitPerm];
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Context not available.

lib/Target/AArch64/AArch64SchedExynosM1.td

Context not available.
let MispredictPenalty = 14; // Minimum branch misprediction penalty. let MispredictPenalty = 14; // Minimum branch misprediction penalty.
let CompleteModel = 1; // Use the default model otherwise. let CompleteModel = 1; // Use the default model otherwise.
list<Predicate> UnsupportedFeatures = [HasSVE]; list<Predicate> UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES,
javed.absarUnsubmitted
Not Done
ReplyInline Actions

Instead of repeating this list everywhere you can at top level :

class AArch64UnsupportedF { list<Predicate> F; }
def SVEUnsupported F : AArch64UnsupportedF {

let F = [HasSVE, HasSVE2, ... ];

}

and then in each AArch64SchedX.td ::
list<Predicate> UnsupportedFeatures = SVEUnsupported.F;

TableGen curently does not have globals otherwise it would be simpler, but this idiom works

javed.absar: Instead of repeating this list everywhere you can at top level : class AArch64UnsupportedF {…
c-rhodesAuthorUnsubmitted
Not Done
ReplyInline Actions

That's neat!

I presume top-level is AArch64.td, I'm happy to make the change there

c-rhodes: That's neat! I presume top-level is `AArch64.td`, I'm happy to make the change there
c-rhodesAuthorUnsubmitted
Done
ReplyInline Actions

@javed.absar I've split this patch up and implemented your suggestion in this revision: https://reviews.llvm.org/D61513

c-rhodes: @javed.absar I've split this patch up and implemented your suggestion in this revision: https…
HasSVE2SM4, HasSVE2SHA3,
HasSVE2BitPerm];
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Context not available.

lib/Target/AArch64/AArch64SchedExynosM3.td

Context not available.
let MispredictPenalty = 16; // Minimum branch misprediction penalty. let MispredictPenalty = 16; // Minimum branch misprediction penalty.
let CompleteModel = 1; // Use the default model otherwise. let CompleteModel = 1; // Use the default model otherwise.
list<Predicate> UnsupportedFeatures = [HasSVE]; list<Predicate> UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES,
HasSVE2SM4, HasSVE2SHA3,
HasSVE2BitPerm];
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Context not available.

lib/Target/AArch64/AArch64SchedExynosM4.td

Context not available.
let MispredictPenalty = 16; // Minimum branch misprediction penalty. let MispredictPenalty = 16; // Minimum branch misprediction penalty.
let CompleteModel = 1; // Use the default model otherwise. let CompleteModel = 1; // Use the default model otherwise.
list<Predicate> UnsupportedFeatures = [HasSVE]; list<Predicate> UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES,
HasSVE2SM4, HasSVE2SHA3,
HasSVE2BitPerm];
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Context not available.

lib/Target/AArch64/AArch64SchedFalkor.td

Context not available.
let MispredictPenalty = 11; // Minimum branch misprediction penalty. let MispredictPenalty = 11; // Minimum branch misprediction penalty.
let CompleteModel = 1; let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE]; list<Predicate> UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES,
HasSVE2SM4, HasSVE2SHA3,
HasSVE2BitPerm];
// FIXME: Remove when all errors have been fixed. // FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0; let FullInstRWOverlapCheck = 0;
Context not available.

lib/Target/AArch64/AArch64SchedKryo.td

Context not available.
let LoopMicroOpBufferSize = 16; let LoopMicroOpBufferSize = 16;
let CompleteModel = 1; let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE]; list<Predicate> UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES,
HasSVE2SM4, HasSVE2SHA3,
HasSVE2BitPerm];
// FIXME: Remove when all errors have been fixed. // FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0; let FullInstRWOverlapCheck = 0;
Context not available.

lib/Target/AArch64/AArch64SchedThunderX.td

Context not available.
let PostRAScheduler = 1; // Use PostRA scheduler. let PostRAScheduler = 1; // Use PostRA scheduler.
let CompleteModel = 1; let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE]; list<Predicate> UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES,
HasSVE2SM4, HasSVE2SHA3,
HasSVE2BitPerm];
// FIXME: Remove when all errors have been fixed. // FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0; let FullInstRWOverlapCheck = 0;
Context not available.

lib/Target/AArch64/AArch64SchedThunderX2T99.td

Context not available.
let PostRAScheduler = 1; // Using PostRA sched. let PostRAScheduler = 1; // Using PostRA sched.
let CompleteModel = 1; let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE]; list<Predicate> UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES,
HasSVE2SM4, HasSVE2SHA3,
HasSVE2BitPerm];
// FIXME: Remove when all errors have been fixed. // FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0; let FullInstRWOverlapCheck = 0;
Context not available.

lib/Target/AArch64/AArch64Subtarget.h

Context not available.
bool HasLSLFast = false; bool HasLSLFast = false;
bool HasSVE = false; bool HasSVE = false;
bool HasSVE2 = false;
bool HasRCPC = false; bool HasRCPC = false;
bool HasAggressiveFMA = false; bool HasAggressiveFMA = false;
Context not available.
bool HasRandGen = false; bool HasRandGen = false;
bool HasMTE = false; bool HasMTE = false;
// Arm SVE2 extensions
bool HasSVE2AES = true;
bool HasSVE2SM4 = true;
bool HasSVE2SHA3 = true;
bool HasSVE2BitPerm = true;
// HasZeroCycleRegMove - Has zero-cycle register mov instructions. // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
bool HasZeroCycleRegMove = false; bool HasZeroCycleRegMove = false;
Context not available.
bool hasSPE() const { return HasSPE; } bool hasSPE() const { return HasSPE; }
bool hasLSLFast() const { return HasLSLFast; } bool hasLSLFast() const { return HasLSLFast; }
bool hasSVE() const { return HasSVE; } bool hasSVE() const { return HasSVE; }
bool hasSVE2() const { return HasSVE2; }
bool hasRCPC() const { return HasRCPC; } bool hasRCPC() const { return HasRCPC; }
bool hasAggressiveFMA() const { return HasAggressiveFMA; } bool hasAggressiveFMA() const { return HasAggressiveFMA; }
bool hasAlternativeNZCV() const { return HasAlternativeNZCV; } bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
Context not available.
bool hasBTI() const { return HasBTI; } bool hasBTI() const { return HasBTI; }
bool hasRandGen() const { return HasRandGen; } bool hasRandGen() const { return HasRandGen; }
bool hasMTE() const { return HasMTE; } bool hasMTE() const { return HasMTE; }
// Arm SVE2 extensions
bool hasSVE2AES() const { return HasSVE2AES; }
bool hasSVE2SM4() const { return HasSVE2SM4; }
bool hasSVE2SHA3() const { return HasSVE2SHA3; }
bool hasSVE2BitPerm() const { return HasSVE2BitPerm; }
bool isLittleEndian() const { return IsLittle; } bool isLittleEndian() const { return IsLittle; }
Context not available.

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Context not available.
{"pan-rwv", {AArch64::FeaturePAN_RWV}}, {"pan-rwv", {AArch64::FeaturePAN_RWV}},
{"ccpp", {AArch64::FeatureCCPP}}, {"ccpp", {AArch64::FeatureCCPP}},
{"sve", {AArch64::FeatureSVE}}, {"sve", {AArch64::FeatureSVE}},
{"sve2", {AArch64::FeatureSVE2}},
{"sve2-aes", {AArch64::FeatureSVE2AES}},
{"sve2-sm4", {AArch64::FeatureSVE2SM4}},
{"sve2-sha3", {AArch64::FeatureSVE2SHA3}},
{"bitperm", {AArch64::FeatureSVE2BitPerm}},
// FIXME: Unsupported extensions // FIXME: Unsupported extensions
{"pan", {}}, {"pan", {}},
{"lor", {}}, {"lor", {}},
Context not available.

lib/Target/AArch64/SVEInstrFormats.td

Context not available.
(!cast<Instruction>(NAME # _Q) ZPR128:$Zd, FPR128asZPR:$Qn, 0), 2>; (!cast<Instruction>(NAME # _Q) ZPR128:$Zd, FPR128asZPR:$Qn, 0), 2>;
} }
class sve_int_perm_tbl<bits<2> sz8_64, string asm, ZPRRegOp zprty, class sve_int_perm_tbl<bits<2> sz8_64, bits<2> opc, string asm,
RegisterOperand VecList> ZPRRegOp zprty, RegisterOperand VecList>
: I<(outs zprty:$Zd), (ins VecList:$Zn, zprty:$Zm), : I<(outs zprty:$Zd), (ins VecList:$Zn, zprty:$Zm),
asm, "\t$Zd, $Zn, $Zm", asm, "\t$Zd, $Zn, $Zm",
"", "",
Context not available.
let Inst{23-22} = sz8_64; let Inst{23-22} = sz8_64;
let Inst{21} = 0b1; let Inst{21} = 0b1;
let Inst{20-16} = Zm; let Inst{20-16} = Zm;
let Inst{15-10} = 0b001100; let Inst{15-13} = 0b001;
let Inst{12-11} = opc;
let Inst{10} = 0b0;
let Inst{9-5} = Zn; let Inst{9-5} = Zn;
let Inst{4-0} = Zd; let Inst{4-0} = Zd;
} }
multiclass sve_int_perm_tbl<string asm> { multiclass sve_int_perm_tbl<string asm> {
def _B : sve_int_perm_tbl<0b00, asm, ZPR8, Z_b>; def _B : sve_int_perm_tbl<0b00, 0b10, asm, ZPR8, Z_b>;
def _H : sve_int_perm_tbl<0b01, asm, ZPR16, Z_h>; def _H : sve_int_perm_tbl<0b01, 0b10, asm, ZPR16, Z_h>;
def _S : sve_int_perm_tbl<0b10, asm, ZPR32, Z_s>; def _S : sve_int_perm_tbl<0b10, 0b10, asm, ZPR32, Z_s>;
def _D : sve_int_perm_tbl<0b11, asm, ZPR64, Z_d>; def _D : sve_int_perm_tbl<0b11, 0b10, asm, ZPR64, Z_d>;
def : InstAlias<asm # "\t$Zd, $Zn, $Zm", def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
(!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 0>; (!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 0>;
Context not available.
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>; (!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>;
} }
multiclass sve2_int_perm_tbl<string asm> {
def _B : sve_int_perm_tbl<0b00, 0b01, asm, ZPR8, ZZ_b>;
def _H : sve_int_perm_tbl<0b01, 0b01, asm, ZPR16, ZZ_h>;
def _S : sve_int_perm_tbl<0b10, 0b01, asm, ZPR32, ZZ_s>;
def _D : sve_int_perm_tbl<0b11, 0b01, asm, ZPR64, ZZ_d>;
}
class sve2_int_perm_tbx<bits<2> sz8_64, string asm, ZPRRegOp zprty>
: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
asm, "\t$Zd, $Zn, $Zm",
"",
[]>, Sched<[]> {
bits<5> Zd;
bits<5> Zm;
bits<5> Zn;
let Inst{31-24} = 0b00000101;
let Inst{23-22} = sz8_64;
let Inst{21} = 0b1;
let Inst{20-16} = Zm;
let Inst{15-10} = 0b001011;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
multiclass sve2_int_perm_tbx<string asm> {
def _B : sve2_int_perm_tbx<0b00, asm, ZPR8>;
def _H : sve2_int_perm_tbx<0b01, asm, ZPR16>;
def _S : sve2_int_perm_tbx<0b10, asm, ZPR32>;
def _D : sve2_int_perm_tbx<0b11, asm, ZPR64>;
}
class sve_int_perm_reverse_z<bits<2> sz8_64, string asm, ZPRRegOp zprty> class sve_int_perm_reverse_z<bits<2> sz8_64, string asm, ZPRRegOp zprty>
: I<(outs zprty:$Zd), (ins zprty:$Zn), : I<(outs zprty:$Zd), (ins zprty:$Zn),
asm, "\t$Zd, $Zn", asm, "\t$Zd, $Zn",
Context not available.
let ElementSize = ElementSizeNone; let ElementSize = ElementSizeNone;
} }
class sve2_int_perm_extract_i_cons<string asm>
: I<(outs ZPR8:$Zd), (ins ZZ_b:$Zn, imm0_255:$imm8),
asm, "\t$Zd, $Zn, $imm8",
"", []>, Sched<[]> {
bits<5> Zd;
bits<5> Zn;
bits<8> imm8;
let Inst{31-21} = 0b00000101011;
let Inst{20-16} = imm8{7-3};
let Inst{15-13} = 0b000;
let Inst{12-10} = imm8{2-0};
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Vector Select Group // SVE Vector Select Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Context not available.
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE2 Floating Point Convert Group
//===----------------------------------------------------------------------===//
class sve2_fp_convert_precision<bits<4> opc, string asm,
ZPRRegOp zprty1, ZPRRegOp zprty2>
: I<(outs zprty1:$Zd), (ins PPR3bAny:$Pg, zprty2:$Zn),
asm, "\t$Zd, $Pg/m, $Zn",
"",
[]>, Sched<[]> {
bits<5> Zd;
bits<5> Zn;
bits<3> Pg;
let Inst{31-24} = 0b01100100;
let Inst{23-22} = opc{3-2};
let Inst{21-18} = 0b0010;
let Inst{17-16} = opc{1-0};
let Inst{15-13} = 0b101;
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
multiclass sve2_fp_convert_down_narrow<string asm> {
def _StoH : sve2_fp_convert_precision<0b1000, asm, ZPR16, ZPR32>;
def _DtoS : sve2_fp_convert_precision<0b1110, asm, ZPR32, ZPR64>;
}
multiclass sve2_fp_convert_up_long<string asm> {
def _HtoS : sve2_fp_convert_precision<0b1001, asm, ZPR32, ZPR16>;
def _StoD : sve2_fp_convert_precision<0b1111, asm, ZPR64, ZPR32>;
}
multiclass sve2_fp_convert_down_odd_rounding<string asm> {
def _DtoS : sve2_fp_convert_precision<0b0010, asm, ZPR32, ZPR64>;
}
//===----------------------------------------------------------------------===//
// SVE2 Floating Point Pairwise Group
//===----------------------------------------------------------------------===//
class sve2_fp_pairwise_pred<bits<2> sz, bits<3> opc, string asm,
ZPRRegOp zprty>
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
"",
[]>, Sched<[]> {
bits<3> Pg;
bits<5> Zm;
bits<5> Zdn;
let Inst{31-24} = 0b01100100;
let Inst{23-22} = sz;
let Inst{21-19} = 0b010;
let Inst{18-16} = opc;
let Inst{15-13} = 0b100;
let Inst{12-10} = Pg;
let Inst{9-5} = Zm;
let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
}
multiclass sve2_fp_pairwise_pred<bits<3> opc, string asm> {
def _H : sve2_fp_pairwise_pred<0b01, opc, asm, ZPR16>;
def _S : sve2_fp_pairwise_pred<0b10, opc, asm, ZPR32>;
def _D : sve2_fp_pairwise_pred<0b11, opc, asm, ZPR64>;
}
//===----------------------------------------------------------------------===//
// SVE2 Floating Point Widening Multiply-Add - Indexed Group
//===----------------------------------------------------------------------===//
class sve2_fp_mla_long_by_indexed_elem<bits<2> opc, string asm>
: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm,
VectorIndexH:$iop),
asm, "\t$Zda, $Zn, $Zm$iop",
"",
[]>, Sched<[]> {
bits<5> Zda;
bits<5> Zn;
bits<3> Zm;
bits<3> iop;
let Inst{31-21} = 0b01100100101;
let Inst{20-19} = iop{2-1};
let Inst{18-16} = Zm;
let Inst{15-14} = 0b01;
let Inst{13} = opc{1};
let Inst{12} = 0b0;
let Inst{11} = iop{0};
let Inst{10} = opc{0};
let Inst{9-5} = Zn;
let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
}
//===----------------------------------------------------------------------===//
// SVE2 Floating Point Widening Multiply-Add Group
//===----------------------------------------------------------------------===//
class sve2_fp_mla_long<bits<2> opc, string asm>
: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm),
asm, "\t$Zda, $Zn, $Zm",
"",
[]>, Sched<[]> {
bits<5> Zda;
bits<5> Zn;
bits<5> Zm;
let Inst{31-21} = 0b01100100101;
let Inst{20-16} = Zm;
let Inst{15-14} = 0b10;
let Inst{13} = opc{1};
let Inst{12-11} = 0b00;
let Inst{10} = opc{0};
let Inst{9-5} = Zn;
let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
}
//===----------------------------------------------------------------------===//
// SVE Stack Allocation Group // SVE Stack Allocation Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Context not available.
def _D : sve_fp_2op_p_zd<{ 0b11, opc }, asm, ZPR64, ZPR64, ElementSizeD>; def _D : sve_fp_2op_p_zd<{ 0b11, opc }, asm, ZPR64, ZPR64, ElementSizeD>;
} }
multiclass sve2_fp_flogb<string asm> {
def _H : sve_fp_2op_p_zd<0b0011010, asm, ZPR16, ZPR16, ElementSizeH>;
def _S : sve_fp_2op_p_zd<0b0011100, asm, ZPR32, ZPR32, ElementSizeS>;
def _D : sve_fp_2op_p_zd<0b0011110, asm, ZPR64, ZPR64, ElementSizeD>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Floating Point Unary Operations - Unpredicated Group // SVE Floating Point Unary Operations - Unpredicated Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Context not available.
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Integer Multiply-Add Group // SVE Integer Multiply-Add - Vectors Group (Predicated)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve_int_mladdsub_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm, class sve_int_mladdsub_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm,
Context not available.
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE2 Integer Multiply-Add - Unpredicated Group
//===----------------------------------------------------------------------===//
class sve_int_mla<bits<2> sz, bits<5> opc, string asm,
ZPRRegOp zprty1, ZPRRegOp zprty2>
: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm),
asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
bits<5> Zda;
bits<5> Zn;
bits<5> Zm;
let Inst{31-24} = 0b01000100;
let Inst{23-22} = sz;
let Inst{21} = 0b0;
let Inst{20-16} = Zm;
let Inst{15} = 0b0;
let Inst{14-10} = opc;
let Inst{9-5} = Zn;
let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
}
multiclass sve_int_mla<bit S, string asm> {
def _B : sve_int_mla<0b00, { 0b1110, S }, asm, ZPR8, ZPR8>;
def _H : sve_int_mla<0b01, { 0b1110, S }, asm, ZPR16, ZPR16>;
def _S : sve_int_mla<0b10, { 0b1110, S }, asm, ZPR32, ZPR32>;
def _D : sve_int_mla<0b11, { 0b1110, S }, asm, ZPR64, ZPR64>;
}
multiclass sve_int_mla_long<bits<5> opc, string asm> {
def _H : sve_int_mla<0b01, opc, asm, ZPR16, ZPR8>;
def _S : sve_int_mla<0b10, opc, asm, ZPR32, ZPR16>;
def _D : sve_int_mla<0b11, opc, asm, ZPR64, ZPR32>;
}
//===----------------------------------------------------------------------===//
// SVE2 Integer Multiply-Add - Indexed Group
//===----------------------------------------------------------------------===//
class sve_int_mla_by_indexed_elem<bits<2> sz, bits<6> opc, string asm,
ZPRRegOp zprty1, ZPRRegOp zprty2,
ZPRRegOp zprty3, Operand itype>
: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop),
asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> {
bits<5> Zda;
bits<5> Zn;
let Inst{31-24} = 0b01000100;
let Inst{23-22} = sz;
let Inst{21} = 0b1;
let Inst{15-10} = opc;
let Inst{9-5} = Zn;
let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
}
multiclass sve_int_mla_by_indexed_elem<bits<2> opc, bit S, string asm> {
def _H : sve_int_mla_by_indexed_elem<{0, ?}, { 0b000, opc, S }, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexH> {
bits<3> Zm;
bits<3> iop;
let Inst{22} = iop{2};
let Inst{20-19} = iop{1-0};
let Inst{18-16} = Zm;
}
def _S : sve_int_mla_by_indexed_elem<0b10, { 0b000, opc, S }, asm, ZPR32, ZPR32, ZPR3b32, VectorIndexS> {
bits<3> Zm;
bits<2> iop;
let Inst{20-19} = iop;
let Inst{18-16} = Zm;
}
def _D : sve_int_mla_by_indexed_elem<0b11, { 0b000, opc, S }, asm, ZPR64, ZPR64, ZPR4b64, VectorIndexD> {
bits<4> Zm;
bit iop;
let Inst{20} = iop;
let Inst{19-16} = Zm;
}
}
//===----------------------------------------------------------------------===//
// SVE2 Integer Multiply-Add Long - Indexed Group
//===----------------------------------------------------------------------===//
multiclass sve_int_mla_long_by_indexed_elem<bits<4> opc, string asm> {
def _S : sve_int_mla_by_indexed_elem<0b10, { opc{3}, 0b0, opc{2-1}, ?, opc{0} },
asm, ZPR32, ZPR16, ZPR3b16, VectorIndexH> {
bits<3> Zm;
bits<3> iop;
let Inst{20-19} = iop{2-1};
let Inst{18-16} = Zm;
let Inst{11} = iop{0};
}
def _D : sve_int_mla_by_indexed_elem<0b11, { opc{3}, 0b0, opc{2-1}, ?, opc{0} },
asm, ZPR64, ZPR32, ZPR4b32, VectorIndexS> {
bits<4> Zm;
bits<2> iop;
let Inst{20} = iop{1};
let Inst{19-16} = Zm;
let Inst{11} = iop{0};
}
}
//===----------------------------------------------------------------------===//
// SVE Integer Dot Product Group // SVE Integer Dot Product Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Context not available.
"", []>, Sched<[]> { "", []>, Sched<[]> {
bits<5> Zda; bits<5> Zda;
bits<5> Zn; bits<5> Zn;
let Inst{31-23} = 0b010001001; let Inst{31-23} = 0b010001001;
let Inst{22} = sz; let Inst{22} = sz;
let Inst{21} = 0b1;
let Inst{15-11} = 0;
let Inst{10} = U;
let Inst{9-5} = Zn;
let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
}
multiclass sve_intx_dot_by_indexed_elem<bit opc, string asm> {
def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS> {
bits<2> iop;
bits<3> Zm;
let Inst{20-19} = iop;
let Inst{18-16} = Zm;
}
def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD> {
bits<1> iop;
bits<4> Zm;
let Inst{20} = iop;
let Inst{19-16} = Zm;
}
}
//===----------------------------------------------------------------------===//
// SVE2 Complex Integer Dot Product Group
//===----------------------------------------------------------------------===//
class sve2_complex_int_arith<bits<2> sz, bits<4> opc, string asm,
ZPRRegOp zprty1, ZPRRegOp zprty2>
: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm,
complexrotateop:$rot),
asm, "\t$Zda, $Zn, $Zm, $rot", "", []>, Sched<[]> {
bits<5> Zda;
bits<5> Zn;
bits<5> Zm;
bits<2> rot;
let Inst{31-24} = 0b01000100;
let Inst{23-22} = sz;
let Inst{21} = 0b0;
let Inst{20-16} = Zm;
let Inst{15-12} = opc;
let Inst{11-10} = rot;
let Inst{9-5} = Zn;
let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
}
multiclass sve_cintx_dot<string asm> {
def _S : sve2_complex_int_arith<0b10, 0b0001, asm, ZPR32, ZPR8>;
def _D : sve2_complex_int_arith<0b11, 0b0001, asm, ZPR64, ZPR16>;
}
//===----------------------------------------------------------------------===//
// SVE2 Complex Multiply-Add Group
//===----------------------------------------------------------------------===//
multiclass sve_int_cmla<bit opc, string asm> {
def _B : sve2_complex_int_arith<0b00, { 0b001, opc }, asm, ZPR8, ZPR8>;
def _H : sve2_complex_int_arith<0b01, { 0b001, opc }, asm, ZPR16, ZPR16>;
def _S : sve2_complex_int_arith<0b10, { 0b001, opc }, asm, ZPR32, ZPR32>;
def _D : sve2_complex_int_arith<0b11, { 0b001, opc }, asm, ZPR64, ZPR64>;
}
//===----------------------------------------------------------------------===//
// SVE2 Complex Integer Dot Product - Indexed Group
//===----------------------------------------------------------------------===//
class sve2_complex_int_arith_indexed<bits<2> sz, bits<4> opc, string asm,
ZPRRegOp zprty1, ZPRRegOp zprty2,
ZPRRegOp zprty3, Operand itype>
: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop,
complexrotateop:$rot),
asm, "\t$Zda, $Zn, $Zm$iop, $rot", "", []>, Sched<[]> {
bits<5> Zda;
bits<5> Zn;
bits<2> rot;
let Inst{31-24} = 0b01000100;
let Inst{23-22} = sz;
let Inst{21} = 0b1;
let Inst{15-12} = opc;
let Inst{11-10} = rot;
let Inst{9-5} = Zn;
let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
}
multiclass sve_cintx_dot_by_indexed_elem<string asm> {
def _S : sve2_complex_int_arith_indexed<0b10, 0b0100, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS> {
bits<2> iop;
bits<3> Zm;
let Inst{20-19} = iop;
let Inst{18-16} = Zm;
}
def _D : sve2_complex_int_arith_indexed<0b11, 0b0100, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD> {
bit iop;
bits<4> Zm;
let Inst{20} = iop;
let Inst{19-16} = Zm;
}
}
//===----------------------------------------------------------------------===//
// SVE2 Complex Multiply-Add - Indexed Group
//===----------------------------------------------------------------------===//
multiclass sve_cmla_by_indexed_elem<bit opc, string asm> {
def _H : sve2_complex_int_arith_indexed<0b10, { 0b011, opc }, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexS> {
bits<2> iop;
bits<3> Zm;
let Inst{20-19} = iop;
let Inst{18-16} = Zm;
}
def _S : sve2_complex_int_arith_indexed<0b11, { 0b011, opc }, asm, ZPR32, ZPR32, ZPR4b32, VectorIndexD> {
bit iop;
bits<4> Zm;
let Inst{20} = iop;
let Inst{19-16} = Zm;
}
}
//===----------------------------------------------------------------------===//
// SVE2 Integer Multiply - Unpredicated Group
//===----------------------------------------------------------------------===//
class sve_int_mul<bits<2> sz, bits<3> opc, string asm, ZPRRegOp zprty>
: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
bits<5> Zd;
bits<5> Zm;
bits<5> Zn;
let Inst{31-24} = 0b00000100;
let Inst{23-22} = sz;
let Inst{21} = 0b1;
let Inst{20-16} = Zm;
let Inst{15-13} = 0b011;
let Inst{12-10} = opc;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
multiclass sve_int_mul<bits<3> opc, string asm> {
def _B : sve_int_mul<0b00, opc, asm, ZPR8>;
def _H : sve_int_mul<0b01, opc, asm, ZPR16>;
def _S : sve_int_mul<0b10, opc, asm, ZPR32>;
def _D : sve_int_mul<0b11, opc, asm, ZPR64>;
}
//===----------------------------------------------------------------------===//
// SVE2 Integer Multiply - Indexed Group
//===----------------------------------------------------------------------===//
class sve_int_mul_by_indexed_elem<bits<2> sz, bits<4> opc, string asm,
ZPRRegOp zprty1, ZPRRegOp zprty2,
ZPRRegOp zprty3, Operand itype>
: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm, itype:$iop),
asm, "\t$Zd, $Zn, $Zm$iop", "", []>, Sched<[]> {
bits<5> Zd;
bits<5> Zn;
let Inst{31-24} = 0b01000100;
let Inst{23-22} = sz;
let Inst{21} = 0b1;
let Inst{15-14} = 0b11;
let Inst{13-10} = opc;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
multiclass sve_int_mul_by_indexed_elem<bits<4> opc, string asm> {
def _H : sve_int_mul_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexH> {
bits<3> Zm;
bits<3> iop;
let Inst{22} = iop{2};
let Inst{20-19} = iop{1-0};
let Inst{18-16} = Zm;
}
def _S : sve_int_mul_by_indexed_elem<0b10, opc, asm, ZPR32, ZPR32, ZPR3b32, VectorIndexS> {
bits<3> Zm;
bits<2> iop;
let Inst{20-19} = iop;
let Inst{18-16} = Zm;
}
def _D : sve_int_mul_by_indexed_elem<0b11, opc, asm, ZPR64, ZPR64, ZPR4b64, VectorIndexD> {
bits<4> Zm;
bit iop;
let Inst{20} = iop;
let Inst{19-16} = Zm;
}
}
multiclass sve_int_mul_long_by_indexed_elem<bits<3> opc, string asm> {
def _S : sve_int_mul_by_indexed_elem<0b10, { opc{2-1}, ?, opc{0} }, asm,
ZPR32, ZPR16, ZPR3b16, VectorIndexH> {
bits<3> Zm;
bits<3> iop;
let Inst{20-19} = iop{2-1};
let Inst{18-16} = Zm;
let Inst{11} = iop{0};
}
def _D : sve_int_mul_by_indexed_elem<0b11, { opc{2-1}, ?, opc{0} }, asm,
ZPR64, ZPR32, ZPR4b32, VectorIndexS> {
bits<4> Zm;
bits<2> iop;
let Inst{20} = iop{1};
let Inst{19-16} = Zm;
let Inst{11} = iop{0};
}
}
//===----------------------------------------------------------------------===//
// SVE2 Integer - Predicated Group
//===----------------------------------------------------------------------===//
class sve2_int_arith_pred<bits<2> sz, bits<6> opc, string asm,
ZPRRegOp zprty>
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> {
bits<3> Pg;
bits<5> Zm;
bits<5> Zdn;
let Inst{31-24} = 0b01000100;
let Inst{23-22} = sz;
let Inst{21-20} = 0b01;
let Inst{20-16} = opc{5-1};
let Inst{15-14} = 0b10;
let Inst{13} = opc{0};
let Inst{12-10} = Pg;
let Inst{9-5} = Zm;
let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
}
multiclass sve2_int_arith_pred<bits<6> opc, string asm> {
def _B : sve2_int_arith_pred<0b00, opc, asm, ZPR8>;
def _H : sve2_int_arith_pred<0b01, opc, asm, ZPR16>;
def _S : sve2_int_arith_pred<0b10, opc, asm, ZPR32>;
def _D : sve2_int_arith_pred<0b11, opc, asm, ZPR64>;
}
class sve2_int_sadd_long_accum_pairwise<bits<2> sz, bit U, string asm,
ZPRRegOp zprty1, ZPRRegOp zprty2>
: I<(outs zprty1:$Zda), (ins PPR3bAny:$Pg, zprty1:$_Zda, zprty2:$Zn),
asm, "\t$Zda, $Pg/m, $Zn", "", []>, Sched<[]> {
bits<3> Pg;
bits<5> Zn;
bits<5> Zda;
let Inst{31-24} = 0b01000100;
let Inst{23-22} = sz;
let Inst{21-17} = 0b00010;
let Inst{16} = U;
let Inst{15-13} = 0b101;
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = zprty1.ElementSize;
}
multiclass sve2_int_sadd_long_accum_pairwise<bit U, string asm> {
def _H : sve2_int_sadd_long_accum_pairwise<0b01, U, asm, ZPR16, ZPR8>;
def _S : sve2_int_sadd_long_accum_pairwise<0b10, U, asm, ZPR32, ZPR16>;
def _D : sve2_int_sadd_long_accum_pairwise<0b11, U, asm, ZPR64, ZPR32>;
}
class sve2_int_un_pred_arit<bits<2> sz, bit Q, bits<2> opc,
string asm, ZPRRegOp zprty>
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
asm, "\t$Zd, $Pg/m, $Zn",
"",
[]>, Sched<[]> {
bits<3> Pg;
bits<5> Zd;
bits<5> Zn;
let Inst{31-24} = 0b01000100;
let Inst{23-22} = sz;
let Inst{21-20} = 0b00;
let Inst{19} = Q;
let Inst{18} = 0b0;
let Inst{17-16} = opc;
let Inst{15-13} = 0b101;
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
let Constraints = "$Zd = $_Zd";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
}
multiclass sve2_int_un_pred_arit_s<bits<3> opc, string asm> {
def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>;
}
multiclass sve2_int_un_pred_arit<bits<3> opc, string asm> {
def _B : sve2_int_un_pred_arit<0b00, opc{2}, opc{1-0}, asm, ZPR8>;
def _H : sve2_int_un_pred_arit<0b01, opc{2}, opc{1-0}, asm, ZPR16>;
def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>;
def _D : sve2_int_un_pred_arit<0b11, opc{2}, opc{1-0}, asm, ZPR64>;
}
//===----------------------------------------------------------------------===//
// SVE2 Widening Integer Arithmetic Group
//===----------------------------------------------------------------------===//
class sve2_wide_int_arith<bits<2> sz, bits<5> opc, string asm,
ZPRRegOp zprty1, ZPRRegOp zprty2, ZPRRegOp zprty3>
: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm),
asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
bits<5> Zd;
bits<5> Zn;
bits<5> Zm;
let Inst{31-24} = 0b01000101;
let Inst{23-22} = sz;
let Inst{21} = 0b0;
let Inst{20-16} = Zm;
let Inst{15} = 0b0;
let Inst{14-10} = opc;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
multiclass sve2_wide_int_arith_long<bits<5> opc, string asm> {
def _H : sve2_wide_int_arith<0b01, opc, asm, ZPR16, ZPR8, ZPR8>;
def _S : sve2_wide_int_arith<0b10, opc, asm, ZPR32, ZPR16, ZPR16>;
def _D : sve2_wide_int_arith<0b11, opc, asm, ZPR64, ZPR32, ZPR32>;
}
multiclass sve2_wide_int_arith_wide<bits<3> opc, string asm> {
def _H : sve2_wide_int_arith<0b01, { 0b10, opc }, asm, ZPR16, ZPR16, ZPR8>;
def _S : sve2_wide_int_arith<0b10, { 0b10, opc }, asm, ZPR32, ZPR32, ZPR16>;
def _D : sve2_wide_int_arith<0b11, { 0b10, opc }, asm, ZPR64, ZPR64, ZPR32>;
}
multiclass sve2_pmul_long<bits<1> opc, string asm> {
def _H : sve2_wide_int_arith<0b01, {0b1101, opc}, asm, ZPR16, ZPR8, ZPR8>;
def _D : sve2_wide_int_arith<0b11, {0b1101, opc}, asm, ZPR64, ZPR32, ZPR32>;
}
//===----------------------------------------------------------------------===//
// SVE2 Misc Group
//===----------------------------------------------------------------------===//
class sve2_misc<bits<2> sz, bits<4> opc, string asm,
ZPRRegOp zprty1, ZPRRegOp zprty2>
: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty2:$Zm),
asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
bits<5> Zd;
bits<5> Zn;
bits<5> Zm;
let Inst{31-24} = 0b01000101;
let Inst{23-22} = sz;
let Inst{21} = 0b0;
let Inst{20-16} = Zm;
let Inst{15-14} = 0b10;
let Inst{13-10} = opc;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
multiclass sve2_misc_bitwise<bits<4> opc, string asm> {
def _B : sve2_misc<0b00, opc, asm, ZPR8, ZPR8>;
def _H : sve2_misc<0b01, opc, asm, ZPR16, ZPR16>;
def _S : sve2_misc<0b10, opc, asm, ZPR32, ZPR32>;
def _D : sve2_misc<0b11, opc, asm, ZPR64, ZPR64>;
}
multiclass sve2_bitwise_xor_interleaved<bit opc, string asm> {
let DestructiveInstType = Destructive, ElementSize = ElementSizeNone in {
def _B : sve2_misc<0b00, { 0b010, opc }, asm, ZPR8, ZPR8>;
def _H : sve2_misc<0b01, { 0b010, opc }, asm, ZPR16, ZPR16>;
def _S : sve2_misc<0b10, { 0b010, opc }, asm, ZPR32, ZPR32>;
def _D : sve2_misc<0b11, { 0b010, opc }, asm, ZPR64, ZPR64>;
}
}
multiclass sve2_misc_int_addsub_long_interleaved<bits<2> opc, string asm> {
def _H : sve2_misc<0b01, { 0b00, opc }, asm, ZPR16, ZPR8>;
def _S : sve2_misc<0b10, { 0b00, opc }, asm, ZPR32, ZPR16>;
def _D : sve2_misc<0b11, { 0b00, opc }, asm, ZPR64, ZPR32>;
}
class sve2_bitwise_shift_left_long<bits<3> tsz8_64, bits<2> opc, string asm,
ZPRRegOp zprty1, ZPRRegOp zprty2,
Operand immtype>
: I<(outs zprty1:$Zd), (ins zprty2:$Zn, immtype:$imm),
asm, "\t$Zd, $Zn, $imm",
"", []>, Sched<[]> {
bits<5> Zd;
bits<5> Zn;
bits<5> imm;
let Inst{31-23} = 0b010001010;
let Inst{22} = tsz8_64{2};
let Inst{21} = 0b0;
let Inst{20-19} = tsz8_64{1-0};
let Inst{18-16} = imm{2-0}; // imm3
let Inst{15-12} = 0b1010;
let Inst{11-10} = opc;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
multiclass sve2_bitwise_shift_left_long<bits<2> opc, string asm> {
def _H : sve2_bitwise_shift_left_long<{0,0,1}, opc, asm,
ZPR16, ZPR8, vecshiftL8>;
def _S : sve2_bitwise_shift_left_long<{0,1,?}, opc, asm,
ZPR32, ZPR16, vecshiftL16> {
let Inst{19} = imm{3};
}
def _D : sve2_bitwise_shift_left_long<{1,?,?}, opc, asm,
ZPR64, ZPR32, vecshiftL32> {
let Inst{20-19} = imm{4-3};
}
}
//===----------------------------------------------------------------------===//
// SVE2 Accumulate Group
//===----------------------------------------------------------------------===//
class sve2_int_bin_cons_shift_imm<bits<4> tsz8_64, bit opc, string asm,
ZPRRegOp zprty, Operand immtype>
: I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$imm),
asm, "\t$Zd, $Zn, $imm",
"", []>, Sched<[]> {
bits<5> Zd;
bits<5> Zn;
bits<6> imm;
let Inst{31-24} = 0b01000101;
let Inst{23-22} = tsz8_64{3-2};
let Inst{21} = 0b0;
let Inst{20-19} = tsz8_64{1-0};
let Inst{18-16} = imm{2-0}; // imm3
let Inst{15-11} = 0b11110;
let Inst{10} = opc;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
multiclass sve2_int_bin_cons_shift_imm_left<bit opc, string asm> {
def _B : sve2_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>;
def _H : sve2_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> {
let Inst{19} = imm{3};
}
def _S : sve2_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> {
let Inst{20-19} = imm{4-3};
}
def _D : sve2_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> {
let Inst{22} = imm{5};
let Inst{20-19} = imm{4-3};
}
}
multiclass sve2_int_bin_cons_shift_imm_right<bit opc, string asm> {
def _B : sve2_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
def _H : sve2_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
let Inst{19} = imm{3};
}
def _S : sve2_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
let Inst{20-19} = imm{4-3};
}
def _D : sve2_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
let Inst{22} = imm{5};
let Inst{20-19} = imm{4-3};
}
}
class sve2_int_bin_accum_cons_shift_imm<bits<4> tsz8_64, bits<2> opc, string asm,
ZPRRegOp zprty, Operand immtype>
: I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, immtype:$imm),
asm, "\t$Zda, $Zn, $imm",
"", []>, Sched<[]> {
bits<5> Zda;
bits<5> Zn;
bits<6> imm;
let Inst{31-24} = 0b01000101;
let Inst{23-22} = tsz8_64{3-2};
let Inst{21} = 0b0;
let Inst{20-19} = tsz8_64{1-0};
let Inst{18-16} = imm{2-0}; // imm3
let Inst{15-12} = 0b1110;
let Inst{11-10} = opc;
let Inst{9-5} = Zn;
let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
}
multiclass sve2_int_bin_accum_cons_shift_imm_right<bits<2> opc, string asm> {
def _B : sve2_int_bin_accum_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
def _H : sve2_int_bin_accum_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
let Inst{19} = imm{3};
}
def _S : sve2_int_bin_accum_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
let Inst{20-19} = imm{4-3};
}
def _D : sve2_int_bin_accum_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
let Inst{22} = imm{5};
let Inst{20-19} = imm{4-3};
}
}
class sve2_int_cadd<bits<2> sz, bit opc, string asm, ZPRRegOp zprty>
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, complexrotateopodd:$rot),
asm, "\t$Zdn, $_Zdn, $Zm, $rot", "", []>, Sched<[]> {
bits<5> Zdn;
bits<5> Zm;
bit rot;
let Inst{31-24} = 0b01000101;
let Inst{23-22} = sz;
let Inst{21-17} = 0b00000;
let Inst{16} = opc;
let Inst{15-11} = 0b11011;
let Inst{10} = rot;
let Inst{9-5} = Zm;
let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
}
multiclass sve2_int_cadd<bit opc, string asm> {
def _B : sve2_int_cadd<0b00, opc, asm, ZPR8>;
def _H : sve2_int_cadd<0b01, opc, asm, ZPR16>;
def _S : sve2_int_cadd<0b10, opc, asm, ZPR32>;
def _D : sve2_int_cadd<0b11, opc, asm, ZPR64>;
}
class sve2_int_absdiff_accum<bits<2> sz, bits<4> opc, string asm,
ZPRRegOp zprty1, ZPRRegOp zprty2>
: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm),
asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
bits<5> Zda;
bits<5> Zn;
bits<5> Zm;
let Inst{31-24} = 0b01000101;
let Inst{23-22} = sz;
let Inst{21} = 0b0;
let Inst{20-16} = Zm;
let Inst{15-14} = 0b11;
let Inst{13-10} = opc;
let Inst{9-5} = Zn;
let Inst{4-0} = Zda;
let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
}
multiclass sve2_int_absdiff_accum<bit opc, string asm> {
def _B : sve2_int_absdiff_accum<0b00, { 0b111, opc }, asm, ZPR8, ZPR8>;
def _H : sve2_int_absdiff_accum<0b01, { 0b111, opc }, asm, ZPR16, ZPR16>;
def _S : sve2_int_absdiff_accum<0b10, { 0b111, opc }, asm, ZPR32, ZPR32>;
def _D : sve2_int_absdiff_accum<0b11, { 0b111, opc }, asm, ZPR64, ZPR64>;
}
multiclass sve2_int_absdiff_accum_long<bits<2> opc, string asm> {
def _H : sve2_int_absdiff_accum<0b01, { 0b00, opc }, asm, ZPR16, ZPR8>;
def _S : sve2_int_absdiff_accum<0b10, { 0b00, opc }, asm, ZPR32, ZPR16>;
def _D : sve2_int_absdiff_accum<0b11, { 0b00, opc }, asm, ZPR64, ZPR32>;
}
multiclass sve2_int_addsub_long_carry<bits<2> opc, string asm> {
def _S : sve2_int_absdiff_accum<{ opc{1}, 0b0 }, { 0b010, opc{0} }, asm,
ZPR32, ZPR32>;
def _D : sve2_int_absdiff_accum<{ opc{1}, 0b1 }, { 0b010, opc{0} }, asm,
ZPR64, ZPR64>;
}
//===----------------------------------------------------------------------===//
// SVE2 Narrowing Group
//===----------------------------------------------------------------------===//
class sve2_int_bin_cons_shift_imm_narrow<bits<3> tsz8_64, bits<4> opc,
string asm, ZPRRegOp zprty1,
ZPRRegOp zprty2, Operand immtype>
: I<(outs zprty1:$Zd), (ins zprty2:$Zn, immtype:$imm),
asm, "\t$Zd, $Zn, $imm",
"", []>, Sched<[]> {
bits<5> Zd;
bits<5> Zn;
bits<5> imm;
let Inst{31-23} = 0b010001010;
let Inst{22} = tsz8_64{2};
let Inst{21} = 0b1;
let Inst{20-19} = tsz8_64{1-0};
let Inst{18-16} = imm{2-0}; // imm3
let Inst{15-14} = 0b00;
let Inst{13-10} = opc;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
multiclass sve2_int_bin_cons_shift_imm_right_narrow<bits<4> opc, string asm> {
def _B : sve2_int_bin_cons_shift_imm_narrow<{0,0,1}, opc, asm, ZPR8, ZPR16,
vecshiftR8>;
def _H : sve2_int_bin_cons_shift_imm_narrow<{0,1,?}, opc, asm, ZPR16, ZPR32,
vecshiftR16> {
let Inst{19} = imm{3};
}
def _S : sve2_int_bin_cons_shift_imm_narrow<{1,?,?}, opc, asm, ZPR32, ZPR64,
vecshiftR32> {
let Inst{20-19} = imm{4-3};
}
}
class sve2_int_addsub_narrow_high<bits<2> sz, bits<3> opc, string asm,
ZPRRegOp zprty1, ZPRRegOp zprty2>
: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty2:$Zm),
asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
bits<5> Zd;
bits<5> Zn;
bits<5> Zm;
let Inst{31-24} = 0b01000101;
let Inst{23-22} = sz;
let Inst{21} = 0b1;
let Inst{20-16} = Zm;
let Inst{15-13} = 0b011;
let Inst{12-10} = opc; // S, R, T
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
multiclass sve2_int_addsub_narrow_high<bits<3> opc, string asm> {
def _B : sve2_int_addsub_narrow_high<0b01, opc, asm, ZPR8, ZPR16>;
def _H : sve2_int_addsub_narrow_high<0b10, opc, asm, ZPR16, ZPR32>;
def _S : sve2_int_addsub_narrow_high<0b11, opc, asm, ZPR32, ZPR64>;
}
class sve2_int_sat_extract_narrow<bits<3> tsz8_64, bits<3> opc, string asm,
ZPRRegOp zprty1, ZPRRegOp zprty2>
: I<(outs zprty1:$Zd), (ins zprty2:$Zn),
asm, "\t$Zd, $Zn", "", []>, Sched<[]> {
bits<5> Zd;
bits<5> Zn;
let Inst{31-23} = 0b010001010;
let Inst{22} = tsz8_64{2};
let Inst{21} = 0b1; let Inst{21} = 0b1;
let Inst{15-11} = 0; let Inst{20-19} = tsz8_64{1-0};
let Inst{10} = U; let Inst{18-13} = 0b000010;
let Inst{12-10} = opc;
let Inst{9-5} = Zn; let Inst{9-5} = Zn;
let Inst{4-0} = Zda; let Inst{4-0} = Zd;
let Constraints = "$Zda = $_Zda";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
} }
multiclass sve_intx_dot_by_indexed_elem<bit opc, string asm> { multiclass sve2_int_sat_extract_narrow<bits<3> opc, string asm> {
def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS> { def _B : sve2_int_sat_extract_narrow<0b001, opc, asm, ZPR8, ZPR16>;
bits<2> iop; def _H : sve2_int_sat_extract_narrow<0b010, opc, asm, ZPR16, ZPR32>;
bits<3> Zm; def _S : sve2_int_sat_extract_narrow<0b100, opc, asm, ZPR32, ZPR64>;
let Inst{20-19} = iop;
let Inst{18-16} = Zm;
}
def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD> {
bits<1> iop;
bits<4> Zm;
let Inst{20} = iop;
let Inst{19-16} = Zm;
}
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Context not available.
let Inst{4-0} = Zd; let Inst{4-0} = Zd;
} }
class sve2_int_bitwise_ternary_op_d<bits<3> opc, string asm>
: I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, ZPR64:$Zm, ZPR64:$Zk),
asm, "\t$Zdn, $_Zdn, $Zm, $Zk",
"",
[]>, Sched<[]> {
bits<5> Zdn;
bits<5> Zk;
bits<5> Zm;
let Inst{31-24} = 0b00000100;
let Inst{23-22} = opc{2-1};
let Inst{21} = 0b1;
let Inst{20-16} = Zm;
let Inst{15-11} = 0b00111;
let Inst{10} = opc{0};
let Inst{9-5} = Zk;
let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
}
multiclass sve2_int_bitwise_ternary_op<bits<3> opc, string asm> {
def NAME : sve2_int_bitwise_ternary_op_d<opc, asm>;
def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
(!cast<Instruction>(NAME) ZPR8:$Zdn, ZPR8:$Zm, ZPR8:$Zk), 1>;
def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
(!cast<Instruction>(NAME) ZPR16:$Zdn, ZPR16:$Zm, ZPR16:$Zk), 1>;
def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
(!cast<Instruction>(NAME) ZPR32:$Zdn, ZPR32:$Zm, ZPR32:$Zk), 1>;
}
class sve2_int_rotate_right_imm<bits<4> tsz8_64, string asm,
ZPRRegOp zprty, Operand immtype>
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, immtype:$imm),
asm, "\t$Zdn, $_Zdn, $Zm, $imm",
"",
[]>, Sched<[]> {
bits<5> Zdn;
bits<5> Zm;
bits<6> imm;
let Inst{31-24} = 0b00000100;
let Inst{23-22} = tsz8_64{3-2};
let Inst{21} = 0b1;
let Inst{20-19} = tsz8_64{1-0};
let Inst{18-16} = imm{2-0}; // imm3
let Inst{15-10} = 0b001101;
let Inst{9-5} = Zm;
let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone;
}
multiclass sve2_int_rotate_right_imm<string asm> {
def _B : sve2_int_rotate_right_imm<{0,0,0,1}, asm, ZPR8, vecshiftR8>;
def _H : sve2_int_rotate_right_imm<{0,0,1,?}, asm, ZPR16, vecshiftR16> {
let Inst{19} = imm{3};
}
def _S : sve2_int_rotate_right_imm<{0,1,?,?}, asm, ZPR32, vecshiftR32> {
let Inst{20-19} = imm{4-3};
}
def _D : sve2_int_rotate_right_imm<{1,?,?,?}, asm, ZPR64, vecshiftR64> {
let Inst{22} = imm{5};
let Inst{20-19} = imm{4-3};
}
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Integer Wide Immediate - Predicated Group // SVE Integer Wide Immediate - Predicated Group
Context not available.
def _D : sve_int_while_rr<0b11, { 1, opc }, asm, GPR64, PPR64>; def _D : sve_int_while_rr<0b11, { 1, opc }, asm, GPR64, PPR64>;
} }
class sve2_int_while_rr<bits<2> sz8_64, bits<1> rw, string asm,
PPRRegOp pprty>
: I<(outs pprty:$Pd), (ins GPR64:$Rn, GPR64:$Rm),
asm, "\t$Pd, $Rn, $Rm",
"", []>, Sched<[]> {
bits<4> Pd;
bits<5> Rm;
bits<5> Rn;
let Inst{31-24} = 0b00100101;
let Inst{23-22} = sz8_64;
let Inst{21} = 0b1;
let Inst{20-16} = Rm;
let Inst{15-10} = 0b001100;
let Inst{9-5} = Rn;
let Inst{4} = rw;
let Inst{3-0} = Pd;
let Defs = [NZCV];
}
multiclass sve2_int_while_rr<bits<1> rw, string asm> {
def _B : sve2_int_while_rr<0b00, rw, asm, PPR8>;
def _H : sve2_int_while_rr<0b01, rw, asm, PPR16>;
def _S : sve2_int_while_rr<0b10, rw, asm, PPR32>;
def _D : sve2_int_while_rr<0b11, rw, asm, PPR64>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Floating Point Fast Reduction Group // SVE Floating Point Fast Reduction Group
Context not available.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Bitwise Shift - Predicated Group // SVE Bitwise Shift - Predicated Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<3> opc, string asm, class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<4> opc, string asm,
ZPRRegOp zprty, Operand immtype, ZPRRegOp zprty, Operand immtype,
ElementSizeEnum size> ElementSizeEnum size>
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm), : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm),
Context not available.
bits<6> imm; bits<6> imm;
let Inst{31-24} = 0b00000100; let Inst{31-24} = 0b00000100;
let Inst{23-22} = tsz8_64{3-2}; let Inst{23-22} = tsz8_64{3-2};
let Inst{21-19} = 0b000; let Inst{21-20} = 0b00;
let Inst{18-16} = opc; let Inst{19-16} = opc;
let Inst{15-13} = 0b100; let Inst{15-13} = 0b100;
let Inst{12-10} = Pg; let Inst{12-10} = Pg;
let Inst{9-8} = tsz8_64{1-0}; let Inst{9-8} = tsz8_64{1-0};
Context not available.
let ElementSize = size; let ElementSize = size;
} }
multiclass sve_int_bin_pred_shift_imm_left<bits<3> opc, string asm> { multiclass sve_int_bin_pred_shift_imm_left<bits<4> opc, string asm> {
def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8, def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8,
ElementSizeB>; ElementSizeB>;
def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16, def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16,
Context not available.
} }
} }
multiclass sve_int_bin_pred_shift_imm_right<bits<3> opc, string asm> { multiclass sve_int_bin_pred_shift_imm_right<bits<4> opc, string asm> {
def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8, def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8,
ElementSizeB>; ElementSizeB>;
def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16, def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16,
Context not available.
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
} }
class sve2_mem_cstnt_vs_base<bits<3> opc, dag iops, string asm,
RegisterOperand VecList>
: I<(outs VecList:$Zt), iops,
asm, "\t$Zt, $Pg, [$Zn, $Rm]",
"",
[]>, Sched<[]> {
bits<3> Pg;
bits<5> Rm;
bits<5> Zn;
bits<5> Zt;
let Inst{31-25} = 0b1110010;
let Inst{24-22} = opc;
let Inst{21} = 0b0;
let Inst{20-16} = Rm;
let Inst{15-13} = 0b001;
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Zt;
let mayStore = 1;
}
multiclass sve2_mem_cstnt_vs<bits<3> opc, string asm,
RegisterOperand listty, ZPRRegOp zprty> {
def _REAL : sve2_mem_cstnt_vs_base<opc, (ins PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm),
asm, listty>;
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $Rm]",
(!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
(!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>;
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $Rm]",
(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>;
}
class sve_mem_sst_sv<bits<3> opc, bit xs, bit scaled, string asm, class sve_mem_sst_sv<bits<3> opc, bit xs, bit scaled, string asm,
RegisterOperand VecList, RegisterOperand zprext> RegisterOperand VecList, RegisterOperand zprext>
: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
Context not available.
def _D : sve_int_perm_splice<0b11, asm, ZPR64>; def _D : sve_int_perm_splice<0b11, asm, ZPR64>;
} }
class sve2_int_perm_splice_cons<bits<2> sz8_64, string asm,
ZPRRegOp zprty, RegisterOperand VecList>
: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, VecList:$Zn),
asm, "\t$Zd, $Pg, $Zn",
"",
[]>, Sched<[]> {
bits<3> Pg;
bits<5> Zn;
bits<5> Zd;
let Inst{31-24} = 0b00000101;
let Inst{23-22} = sz8_64;
let Inst{21-13} = 0b101101100;
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
multiclass sve2_int_perm_splice_cons<string asm> {
def _B : sve2_int_perm_splice_cons<0b00, asm, ZPR8, ZZ_b>;
def _H : sve2_int_perm_splice_cons<0b01, asm, ZPR16, ZZ_h>;
def _S : sve2_int_perm_splice_cons<0b10, asm, ZPR32, ZZ_s>;
def _D : sve2_int_perm_splice_cons<0b11, asm, ZPR64, ZZ_d>;
}
class sve_int_perm_rev<bits<2> sz8_64, bits<2> opc, string asm, class sve_int_perm_rev<bits<2> sz8_64, bits<2> opc, string asm,
ZPRRegOp zprty> ZPRRegOp zprty>
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn), : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
Context not available.
(!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>; (!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
} }
class sve2_mem_cldnt_vs_base<bits<5> opc, dag iops, string asm,
RegisterOperand VecList>
: I<(outs VecList:$Zt), iops,
asm, "\t$Zt, $Pg/z, [$Zn, $Rm]",
"",
[]>, Sched<[]> {
bits<3> Pg;
bits<5> Rm;
bits<5> Zn;
bits<5> Zt;
let Inst{31} = 0b1;
let Inst{30} = opc{4};
let Inst{29-25} = 0b00010;
let Inst{24-23} = opc{3-2};
let Inst{22-21} = 0b00;
let Inst{20-16} = Rm;
let Inst{15} = 0b1;
let Inst{14-13} = opc{1-0};
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Zt;
let mayLoad = 1;
}
multiclass sve2_mem_cldnt_vs<bits<5> opc, string asm,
RegisterOperand listty, ZPRRegOp zprty> {
def _REAL : sve2_mem_cldnt_vs_base<opc, (ins PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm),
asm, listty>;
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $Rm]",
(!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
(!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>;
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $Rm]",
(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Memory - 64-bit Gather Group // SVE Memory - 64-bit Gather Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Context not available.
def NAME : sve_int_break<opc, asm, "/z", (ins PPRAny:$Pg, PPR8:$Pn)>; def NAME : sve_int_break<opc, asm, "/z", (ins PPRAny:$Pg, PPR8:$Pn)>;
} }
//===----------------------------------------------------------------------===//
// SVE2 String Processing Group
//===----------------------------------------------------------------------===//
class sve2_char_match<bit sz, bit opc, string asm,
PPRRegOp pprty, ZPRRegOp zprty>
: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
asm, "\t$Pd, $Pg/z, $Zn, $Zm",
"",
[]>, Sched<[]> {
bits<4> Pd;
bits<3> Pg;
bits<5> Zm;
bits<5> Zn;
let Inst{31-23} = 0b010001010;
let Inst{22} = sz;
let Inst{21} = 0b1;
let Inst{20-16} = Zm;
let Inst{15-13} = 0b100;
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4} = opc;
let Inst{3-0} = Pd;
let Defs = [NZCV];
}
multiclass sve2_char_match<bit opc, string asm> {
def _B : sve2_char_match<0b0, opc, asm, PPR8, ZPR8>;
def _H : sve2_char_match<0b1, opc, asm, PPR16, ZPR16>;
}
//===----------------------------------------------------------------------===//
// SVE2 Histogram Computation - Segment Group
//===----------------------------------------------------------------------===//
class sve2_hist_gen_segment<string asm>
: I<(outs ZPR8:$Zd), (ins ZPR8:$Zn, ZPR8:$Zm),
asm, "\t$Zd, $Zn, $Zm",
"",
[]>, Sched<[]> {
bits<5> Zd;
bits<5> Zn;
bits<5> Zm;
let Inst{31-21} = 0b01000101001;
let Inst{20-16} = Zm;
let Inst{15-10} = 0b101000;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
//===----------------------------------------------------------------------===//
// SVE2 Histogram Computation - Vector Group
//===----------------------------------------------------------------------===//
class sve2_hist_gen_vector<bit sz, string asm, ZPRRegOp zprty>
: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
asm, "\t$Zd, $Pg/z, $Zn, $Zm",
"",
[]>, Sched<[]> {
bits<5> Zd;
bits<5> Zn;
bits<3> Pg;
bits<5> Zm;
let Inst{31-23} = 0b010001011;
let Inst{22} = sz;
let Inst{21} = 0b1;
let Inst{20-16} = Zm;
let Inst{15-13} = 0b110;
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
multiclass sve2_hist_gen_vector<string asm> {
def _S : sve2_hist_gen_vector<0b0, asm, ZPR32>;
def _D : sve2_hist_gen_vector<0b1, asm, ZPR64>;
}
//===----------------------------------------------------------------------===//
// SVE2 Crypto Extensions Group
//===----------------------------------------------------------------------===//
class sve2_crypto_cons_bin_op<bit opc, string asm, ZPRRegOp zprty>
: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
asm, "\t$Zd, $Zn, $Zm",
"",
[]>, Sched<[]> {
bits<5> Zd;
bits<5> Zn;
bits<5> Zm;
let Inst{31-21} = 0b01000101001;
let Inst{20-16} = Zm;
let Inst{15-11} = 0b11110;
let Inst{10} = opc;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
class sve2_crypto_des_bin_op<bits<2> opc, string asm, ZPRRegOp zprty>
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm),
asm, "\t$Zdn, $_Zdn, $Zm",
"",
[]>, Sched<[]> {
bits<5> Zdn;
bits<5> Zm;
let Inst{31-17} = 0b010001010010001;
let Inst{16} = opc{1};
let Inst{15-11} = 0b11100;
let Inst{10} = opc{0};
let Inst{9-5} = Zm;
let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn";
}
class sve2_crypto_unary_op<bit opc, string asm>
: I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn),
asm, "\t$Zdn, $_Zdn",
"",
[]>, Sched<[]> {
bits<5> Zdn;
let Inst{31-11} = 0b010001010010000011100;
let Inst{10} = opc;
let Inst{9-5} = 0b00000;
let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn";
}
Context not available.

test/MC/AArch64/SVE/ldnt1b-diagnostics.s

Context not available.
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1b z0.s, p0/z, [x0] ldnt1b z0.s, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1b z0.s, p0/z, [x0] // CHECK-NEXT: ldnt1b z0.s, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1b z0.d, p0/z, [x0] ldnt1b z0.d, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1b z0.d, p0/z, [x0] // CHECK-NEXT: ldnt1b z0.d, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Context not available.

test/MC/AArch64/SVE/movprfx-diagnostics.s

Context not available.
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Destination used in other operand (ternary + indexed)
movprfx z0, z1
sdot z0.s, z1.b, z0.b[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source
// CHECK-NEXT: sdot z0.s, z1.b, z0.b[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Different general predicate (unary) // Different general predicate (unary)
movprfx z0.d, p0/m, z1.d movprfx z0.d, p0/m, z1.d
Context not available.

test/MC/AArch64/SVE/stnt1b-diagnostics.s

Context not available.
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1b z0.s, p0, [x0] stnt1b z0.s, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1b z0.s, p0, [x0] // CHECK-NEXT: stnt1b z0.s, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1b z0.d, p0, [x0] stnt1b z0.d, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1b z0.d, p0, [x0] // CHECK-NEXT: stnt1b z0.d, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Context not available.

test/MC/AArch64/SVE2/adclb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
adclb z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: adclb z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
adclb z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: adclb z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
adclb z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: adclb z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/adclb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
adclb z0.s, z1.s, z31.s
// CHECK-INST: adclb z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xd0,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 d0 1f 45 <unknown>
adclb z0.d, z1.d, z31.d
// CHECK-INST: adclb z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xd0,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 d0 5f 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
adclb z0.d, z1.d, z31.d
// CHECK-INST: adclb z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xd0,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 d0 5f 45 <unknown>

test/MC/AArch64/SVE2/adclt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
adclt z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: adclt z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
adclt z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: adclt z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
adclt z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: adclt z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/adclt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
adclt z0.s, z1.s, z31.s
// CHECK-INST: adclt z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xd4,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 d4 1f 45 <unknown>
adclt z0.d, z1.d, z31.d
// CHECK-INST: adclt z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xd4,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 d4 5f 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
adclt z0.d, z1.d, z31.d
// CHECK-INST: adclt z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xd4,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 d4 5f 45 <unknown>

test/MC/AArch64/SVE2/addhnb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
addhnb z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: addhnb z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
addhnb z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: addhnb z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
addhnb z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: addhnb z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
addhnb z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: addhnb z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
addhnb z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: addhnb z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
addhnb z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: addhnb z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/addhnb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
addhnb z0.b, z1.h, z31.h
// CHECK-INST: addhnb z0.b, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x60,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 60 7f 45 <unknown>
addhnb z0.h, z1.s, z31.s
// CHECK-INST: addhnb z0.h, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x60,0xbf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 60 bf 45 <unknown>
addhnb z0.s, z1.d, z31.d
// CHECK-INST: addhnb z0.s, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x60,0xff,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 60 ff 45 <unknown>

test/MC/AArch64/SVE2/addhnt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
addhnt z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: addhnt z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
addhnt z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: addhnt z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
addhnt z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: addhnt z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
addhnt z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: addhnt z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
addhnt z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: addhnt z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
addhnt z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: addhnt z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/addhnt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
addhnt z0.b, z1.h, z31.h
// CHECK-INST: addhnt z0.b, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x64,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 64 7f 45 <unknown>
addhnt z0.h, z1.s, z31.s
// CHECK-INST: addhnt z0.h, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x64,0xbf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 64 bf 45 <unknown>
addhnt z0.s, z1.d, z31.d
// CHECK-INST: addhnt z0.s, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x64,0xff,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 64 ff 45 <unknown>

test/MC/AArch64/SVE2/addp-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
addp z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: addp z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
addp z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: addp z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
addp z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: addp z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
addp z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: addp z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/addp.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
addp z0.b, p0/m, z0.b, z1.b
// CHECK-INST: addp z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0xa0,0x11,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 11 44 <unknown>
addp z0.h, p0/m, z0.h, z1.h
// CHECK-INST: addp z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0xa0,0x51,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 51 44 <unknown>
addp z29.s, p7/m, z29.s, z30.s
// CHECK-INST: addp z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0xbf,0x91,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd bf 91 44 <unknown>
addp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: addp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0xbf,0xd1,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df bf d1 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
addp z31.d, p0/m, z31.d, z30.d
// CHECK-INST: addp z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0xa3,0xd1,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df a3 d1 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
addp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: addp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0xbf,0xd1,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df bf d1 44 <unknown>

test/MC/AArch64/SVE2/aesd-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
aesd z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: aesd z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
aesd z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: aesd z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
aesd z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: aesd z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
aesd z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: aesd z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.b, p0/z, z7.b
aesd z0.b, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: aesd z0.b, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
aesd z0.b, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: aesd z0.b, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/aesd.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
// RUN: | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
aesd z0.b, z0.b, z31.b
// CHECK-INST: aesd z0.b, z0.b, z31.b
// CHECK-ENCODING: [0xe0,0xe7,0x22,0x45]
// CHECK-ERROR: instruction requires: sve2-aes
// CHECK-UNKNOWN: e0 e7 22 45 <unknown>

test/MC/AArch64/SVE2/aese-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
aese z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: aese z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
aese z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: aese z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
aese z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: aese z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
aese z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: aese z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.b, p0/z, z7.b
aese z0.b, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: aese z0.b, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
aese z0.b, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: aese z0.b, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/aese.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
// RUN: | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
aese z0.b, z0.b, z31.b
// CHECK-INST: aese z0.b, z0.b, z31.b
// CHECK-ENCODING: [0xe0,0xe3,0x22,0x45]
// CHECK-ERROR: instruction requires: sve2-aes
// CHECK-UNKNOWN: e0 e3 22 45 <unknown>

test/MC/AArch64/SVE2/aesimc-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
aesimc z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: aesimc z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
aesimc z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: aesimc z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
aesimc z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: aesimc z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
aesimc z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: aesimc z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.b, p0/z, z7.b
aesimc z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: aesimc z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
aesimc z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: aesimc z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/aesimc.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
// RUN: | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
aesimc z0.b, z0.b
// CHECK-INST: aesimc z0.b, z0.b
// CHECK-ENCODING: [0x00,0xe4,0x20,0x45]
// CHECK-ERROR: instruction requires: sve2-aes
// CHECK-UNKNOWN: 00 e4 20 45 <unknown>
aesimc z31.b, z31.b
// CHECK-INST: aesimc z31.b, z31.b
// CHECK-ENCODING: [0x1f,0xe4,0x20,0x45]
// CHECK-ERROR: instruction requires: sve2-aes
// CHECK-UNKNOWN: 1f e4 20 45 <unknown>

test/MC/AArch64/SVE2/aesmc-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
aesmc z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: aesmc z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
aesmc z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: aesmc z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
aesmc z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: aesmc z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
aesmc z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: aesmc z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.b, p0/z, z7.b
aesmc z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: aesmc z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
aesmc z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: aesmc z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/aesmc.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
// RUN: | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
aesmc z0.b, z0.b
// CHECK-INST: aesmc z0.b, z0.b
// CHECK-ENCODING: [0x00,0xe0,0x20,0x45]
// CHECK-ERROR: instruction requires: sve2-aes
// CHECK-UNKNOWN: 00 e0 20 45 <unknown>
aesmc z31.b, z31.b
// CHECK-INST: aesmc z31.b, z31.b
// CHECK-ENCODING: [0x1f,0xe0,0x20,0x45]
// CHECK-ERROR: instruction requires: sve2-aes
// CHECK-UNKNOWN: 1f e0 20 45 <unknown>

test/MC/AArch64/SVE2/bcax-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
bcax z0.b, z0.b, z1.s, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bcax z0.b, z0.b, z1.s, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bcax z0.h, z0.h, z1.h, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bcax z0.h, z0.h, z1.h, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bcax z0.d, z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bcax z0.d, z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
bcax z0.d, z1.d, z2.d, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: bcax z0.d, z1.d, z2.d, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
bcax z0.d, z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: bcax z0.d, z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/bcax.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
bcax z29.d, z29.d, z30.d, z31.d
// CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 7e 04 <unknown>
// --------------------------------------------------------------------------//
// Test aliases.
bcax z29.b, z29.b, z30.b, z31.b
// CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 7e 04 <unknown>
bcax z29.h, z29.h, z30.h, z31.h
// CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 7e 04 <unknown>
bcax z29.s, z29.s, z30.s, z31.s
// CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 7e 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z7
// CHECK-INST: movprfx z31, z7
// CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bc 20 04 <unknown>
bcax z31.d, z31.d, z30.d, z29.d
// CHECK-INST: bcax z31.d, z31.d, z30.d, z29.d
// CHECK-ENCODING: [0xbf,0x3b,0x7e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bf 3b 7e 04 <unknown>

test/MC/AArch64/SVE2/bdep-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
bdep z0.b, z1.h, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bdep z0.b, z1.h, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
bdep z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: bdep z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
bdep z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: bdep z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/bdep.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \
// RUN: | llvm-objdump -d -mattr=+bitperm - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
bdep z0.b, z1.b, z31.b
// CHECK-INST: bdep z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xb4,0x1f,0x45]
// CHECK-ERROR: instruction requires: bitperm
// CHECK-UNKNOWN: 20 b4 1f 45 <unknown>
bdep z0.h, z1.h, z31.h
// CHECK-INST: bdep z0.h, z1.h, z31.h
// CHECK-ENCODING: [0x20,0xb4,0x5f,0x45]
// CHECK-ERROR: instruction requires: bitperm
// CHECK-UNKNOWN: 20 b4 5f 45 <unknown>
bdep z0.s, z1.s, z31.s
// CHECK-INST: bdep z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xb4,0x9f,0x45]
// CHECK-ERROR: instruction requires: bitperm
// CHECK-UNKNOWN: 20 b4 9f 45 <unknown>
bdep z0.d, z1.d, z31.d
// CHECK-INST: bdep z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xb4,0xdf,0x45]
// CHECK-ERROR: instruction requires: bitperm
// CHECK-UNKNOWN: 20 b4 df 45 <unknown>

test/MC/AArch64/SVE2/bext-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
bext z0.b, z1.h, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bext z0.b, z1.h, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
bext z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: bext z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
bext z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: bext z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/bext.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \
// RUN: | llvm-objdump -d -mattr=+bitperm - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
bext z0.b, z1.b, z31.b
// CHECK-INST: bext z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xb0,0x1f,0x45]
// CHECK-ERROR: instruction requires: bitperm
// CHECK-UNKNOWN: 20 b0 1f 45 <unknown>
bext z0.h, z1.h, z31.h
// CHECK-INST: bext z0.h, z1.h, z31.h
// CHECK-ENCODING: [0x20,0xb0,0x5f,0x45]
// CHECK-ERROR: instruction requires: bitperm
// CHECK-UNKNOWN: 20 b0 5f 45 <unknown>
bext z0.s, z1.s, z31.s
// CHECK-INST: bext z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xb0,0x9f,0x45]
// CHECK-ERROR: instruction requires: bitperm
// CHECK-UNKNOWN: 20 b0 9f 45 <unknown>
bext z0.d, z1.d, z31.d
// CHECK-INST: bext z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xb0,0xdf,0x45]
// CHECK-ERROR: instruction requires: bitperm
// CHECK-UNKNOWN: 20 b0 df 45 <unknown>

test/MC/AArch64/SVE2/bgrp-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
bgrp z0.b, z1.h, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bgrp z0.b, z1.h, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
bgrp z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: bgrp z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
bgrp z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: bgrp z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/bgrp.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \
// RUN: | llvm-objdump -d -mattr=+bitperm - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
bgrp z0.b, z1.b, z31.b
// CHECK-INST: bgrp z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xb8,0x1f,0x45]
// CHECK-ERROR: instruction requires: bitperm
// CHECK-UNKNOWN: 20 b8 1f 45 <unknown>
bgrp z0.h, z1.h, z31.h
// CHECK-INST: bgrp z0.h, z1.h, z31.h
// CHECK-ENCODING: [0x20,0xb8,0x5f,0x45]
// CHECK-ERROR: instruction requires: bitperm
// CHECK-UNKNOWN: 20 b8 5f 45 <unknown>
bgrp z0.s, z1.s, z31.s
// CHECK-INST: bgrp z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xb8,0x9f,0x45]
// CHECK-ERROR: instruction requires: bitperm
// CHECK-UNKNOWN: 20 b8 9f 45 <unknown>
bgrp z0.d, z1.d, z31.d
// CHECK-INST: bgrp z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xb8,0xdf,0x45]
// CHECK-ERROR: instruction requires: bitperm
// CHECK-UNKNOWN: 20 b8 df 45 <unknown>

test/MC/AArch64/SVE2/bsl-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
bsl z0.b, z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl z0.b, z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bsl z0.h, z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl z0.h, z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bsl z0.s, z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl z0.s, z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
bsl z0.d, z1.d, z2.d, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: bsl z0.d, z1.d, z2.d, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
bsl z0.d, z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: bsl z0.d, z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/bsl.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
bsl z0.d, z0.d, z1.d, z2.d
// CHECK-INST: bsl z0.d, z0.d, z1.d, z2.d
// CHECK-ENCODING: [0x40,0x3c,0x21,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 40 3c 21 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z7
// CHECK-INST: movprfx z31, z7
// CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bc 20 04 <unknown>
bsl z31.d, z31.d, z30.d, z29.d
// CHECK-INST: bsl z31.d, z31.d, z30.d, z29.d
// CHECK-ENCODING: [0xbf,0x3f,0x3e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bf 3f 3e 04 <unknown>

test/MC/AArch64/SVE2/bsl1n-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
bsl1n z0.b, z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl1n z0.b, z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bsl1n z0.h, z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl1n z0.h, z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bsl1n z0.s, z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl1n z0.s, z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
bsl1n z0.d, z1.d, z2.d, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: bsl1n z0.d, z1.d, z2.d, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
bsl1n z0.d, z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: bsl1n z0.d, z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/bsl1n.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
bsl1n z0.d, z0.d, z1.d, z2.d
// CHECK-INST: bsl1n z0.d, z0.d, z1.d, z2.d
// CHECK-ENCODING: [0x40,0x3c,0x61,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 40 3c 61 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z7
// CHECK-INST: movprfx z31, z7
// CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bc 20 04 <unknown>
bsl1n z31.d, z31.d, z30.d, z29.d
// CHECK-INST: bsl1n z31.d, z31.d, z30.d, z29.d
// CHECK-ENCODING: [0xbf,0x3f,0x7e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bf 3f 7e 04 <unknown>

test/MC/AArch64/SVE2/bsl2n-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
bsl2n z0.b, z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl2n z0.b, z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bsl2n z0.h, z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl2n z0.h, z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
bsl2n z0.s, z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: bsl2n z0.s, z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
bsl2n z0.d, z1.d, z2.d, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: bsl2n z0.d, z1.d, z2.d, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
bsl2n z0.d, z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: bsl2n z0.d, z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/bsl2n.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
bsl2n z0.d, z0.d, z1.d, z2.d
// CHECK-INST: bsl2n z0.d, z0.d, z1.d, z2.d
// CHECK-ENCODING: [0x40,0x3c,0xa1,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 40 3c a1 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z7
// CHECK-INST: movprfx z31, z7
// CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bc 20 04 <unknown>
bsl2n z31.d, z31.d, z30.d, z29.d
// CHECK-INST: bsl2n z31.d, z31.d, z30.d, z29.d
// CHECK-ENCODING: [0xbf,0x3f,0xbe,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bf 3f be 04 <unknown>

test/MC/AArch64/SVE2/cadd-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
cadd z0.d, z1.d, z2.d, #90
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: cadd z0.d, z1.d, z2.d, #90
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid rotation
cadd z0.d, z0.d, z1.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
// CHECK-NEXT: cadd z0.d, z0.d, z1.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cadd z0.d, z0.d, z1.d, #180
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
// CHECK-NEXT: cadd z0.d, z0.d, z1.d, #180
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cadd z0.d, z0.d, z1.d, #450
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
// CHECK-NEXT: cadd z0.d, z0.d, z1.d, #450
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
cadd z0.d, z0.d, z31.d, #90
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: cadd z0.d, z0.d, z31.d, #90
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/cadd.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
cadd z0.b, z0.b, z0.b, #90
// CHECK-INST: cadd z0.b, z0.b, z0.b, #90
// CHECK-ENCODING: [0x00,0xd8,0x00,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 d8 00 45 <unknown>
cadd z0.h, z0.h, z0.h, #90
// CHECK-INST: cadd z0.h, z0.h, z0.h, #90
// CHECK-ENCODING: [0x00,0xd8,0x40,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 d8 40 45 <unknown>
cadd z0.s, z0.s, z0.s, #90
// CHECK-INST: cadd z0.s, z0.s, z0.s, #90
// CHECK-ENCODING: [0x00,0xd8,0x80,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 d8 80 45 <unknown>
cadd z0.d, z0.d, z0.d, #90
// CHECK-INST: cadd z0.d, z0.d, z0.d, #90
// CHECK-ENCODING: [0x00,0xd8,0xc0,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 d8 c0 45 <unknown>
cadd z31.b, z31.b, z31.b, #270
// CHECK-INST: cadd z31.b, z31.b, z31.b, #270
// CHECK-ENCODING: [0xff,0xdf,0x00,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 00 45 <unknown>
cadd z31.h, z31.h, z31.h, #270
// CHECK-INST: cadd z31.h, z31.h, z31.h, #270
// CHECK-ENCODING: [0xff,0xdf,0x40,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 40 45 <unknown>
cadd z31.s, z31.s, z31.s, #270
// CHECK-INST: cadd z31.s, z31.s, z31.s, #270
// CHECK-ENCODING: [0xff,0xdf,0x80,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 80 45 <unknown>
cadd z31.d, z31.d, z31.d, #270
// CHECK-INST: cadd z31.d, z31.d, z31.d, #270
// CHECK-ENCODING: [0xff,0xdf,0xc0,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df c0 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
cadd z4.d, z4.d, z31.d, #270
// CHECK-INST: cadd z4.d, z4.d, z31.d, #270
// CHECK-ENCODING: [0xe4,0xdf,0xc0,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 df c0 45 <unknown>

test/MC/AArch64/SVE2/cdot-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element size
cdot z0.s, z1.h, z31.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: cdot z0.s, z1.h, z31.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cdot z0.s, z1.s, z31.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: cdot z0.s, z1.s, z31.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cdot z0.s, z1.d, z31.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: cdot z0.s, z1.d, z31.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cdot z0.d, z1.b, z31.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: cdot z0.d, z1.b, z31.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cdot z0.d, z1.s, z31.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: cdot z0.d, z1.s, z31.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cdot z0.d, z1.d, z31.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: cdot z0.d, z1.d, z31.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid restricted register for indexed vector.
cdot z0.s, z1.b, z8.b[3], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: cdot z0.s, z1.b, z8.b[3], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cdot z0.d, z1.h, z16.h[1], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: cdot z0.d, z1.h, z16.h[1], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element index
cdot z0.s, z1.b, z7.b[-1], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: cdot z0.s, z1.b, z7.b[-1], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cdot z0.s, z1.b, z7.b[4], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: cdot z0.s, z1.b, z7.b[4], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cdot z0.d, z1.h, z15.h[-1], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: cdot z0.d, z1.h, z15.h[-1], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cdot z0.d, z1.h, z15.h[2], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: cdot z0.d, z1.h, z15.h[2], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid rotation
cdot z0.s, z1.b, z2.b[0], #360
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270.
// CHECK-NEXT: cdot z0.s, z1.b, z2.b[0], #360
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cdot z0.d, z1.h, z2.h[0], #450
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270.
// CHECK-NEXT: cdot z0.d, z1.h, z2.h[0], #450
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
cdot z0.d, z1.h, z31.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: cdot z0.d, z1.h, z31.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
cdot z0.d, z1.h, z15.h[1], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: cdot z0.d, z1.h, z15.h[1], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/cdot.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
cdot z0.s, z1.b, z31.b, #0
// CHECK-INST: cdot z0.s, z1.b, z31.b, #0
// CHECK-ENCODING: [0x20,0x10,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 10 9f 44 <unknown>
cdot z0.d, z1.h, z31.h, #0
// CHECK-INST: cdot z0.d, z1.h, z31.h, #0
// CHECK-ENCODING: [0x20,0x10,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 10 df 44 <unknown>
cdot z0.d, z1.h, z31.h, #90
// CHECK-INST: cdot z0.d, z1.h, z31.h, #90
// CHECK-ENCODING: [0x20,0x14,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 14 df 44 <unknown>
cdot z0.d, z1.h, z31.h, #180
// CHECK-INST: cdot z0.d, z1.h, z31.h, #180
// CHECK-ENCODING: [0x20,0x18,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 18 df 44 <unknown>
cdot z0.d, z1.h, z31.h, #270
// CHECK-INST: cdot z0.d, z1.h, z31.h, #270
// CHECK-ENCODING: [0x20,0x1c,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 1c df 44 <unknown>
cdot z0.s, z1.b, z7.b[3], #0
// CHECK-INST: cdot z0.s, z1.b, z7.b[3], #0
// CHECK-ENCODING: [0x20,0x40,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 40 bf 44 <unknown>
cdot z0.d, z1.h, z15.h[1], #0
// CHECK-INST: cdot z0.d, z1.h, z15.h[1], #0
// CHECK-ENCODING: [0x20,0x40,0xff,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 40 ff 44 <unknown>
cdot z5.d, z6.h, z3.h[0], #90
// CHECK-INST: cdot z5.d, z6.h, z3.h[0], #90
// CHECK-ENCODING: [0xc5,0x44,0xe3,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: c5 44 e3 44 <unknown>
cdot z29.d, z30.h, z0.h[0], #180
// CHECK-INST: cdot z29.d, z30.h, z0.h[0], #180
// CHECK-ENCODING: [0xdd,0x4b,0xe0,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 4b e0 44 <unknown>
cdot z31.d, z30.h, z7.h[1], #270
// CHECK-INST: cdot z31.d, z30.h, z7.h[1], #270
// CHECK-ENCODING: [0xdf,0x4f,0xf7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 4f f7 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
cdot z0.d, z1.h, z31.h, #0
// CHECK-INST: cdot z0.d, z1.h, z31.h, #0
// CHECK-ENCODING: [0x20,0x10,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 10 df 44 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
cdot z0.d, z1.h, z15.h[1], #0
// CHECK-INST: cdot z0.d, z1.h, z15.h[1], #0
// CHECK-ENCODING: [0x20,0x40,0xff,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 40 ff 44 <unknown>

test/MC/AArch64/SVE2/cmla-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element size
cmla z0.h, z1.b, z2.b[0], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: cmla z0.h, z1.b, z2.b[0], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmla z0.h, z1.s, z2.s[0], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: cmla z0.h, z1.s, z2.s[0], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmla z0.h, z1.d, z2.d[0], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: cmla z0.h, z1.d, z2.d[0], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmla z0.s, z1.b, z2.b[0], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: cmla z0.s, z1.b, z2.b[0], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmla z0.s, z1.h, z2.h[0], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: cmla z0.s, z1.h, z2.h[0], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmla z0.s, z1.d, z2.d[0], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: cmla z0.s, z1.d, z2.d[0], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid restricted register for indexed vector.
cmla z0.h, z1.h, z8.h[3], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: cmla z0.h, z1.h, z8.h[3], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmla z0.s, z1.s, z16.s[1], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: cmla z0.s, z1.s, z16.s[1], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element index
cmla z0.h, z1.h, z7.h[-1], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: cmla z0.h, z1.h, z7.h[-1], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmla z0.h, z1.h, z7.h[4], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: cmla z0.h, z1.h, z7.h[4], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmla z0.s, z1.s, z15.s[-1], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: cmla z0.s, z1.s, z15.s[-1], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmla z0.s, z1.s, z15.s[2], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: cmla z0.s, z1.s, z15.s[2], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid rotation
cmla z0.h, z1.h, z2.h[0], #360
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270.
// CHECK-NEXT: cmla z0.h, z1.h, z2.h[0], #360
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cmla z0.s, z1.s, z2.s[0], #450
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270.
// CHECK-NEXT: cmla z0.s, z1.s, z2.s[0], #450
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.b, p0/z, z7.b
cmla z0.b, z1.b, z31.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: cmla z0.b, z1.b, z31.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
cmla z0.s, z1.s, z15.s[1], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: cmla z0.s, z1.s, z15.s[1], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/cmla.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
cmla z0.b, z1.b, z2.b, #0
// CHECK-INST: cmla z0.b, z1.b, z2.b, #0
// CHECK-ENCODING: [0x20,0x20,0x02,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 02 44 <unknown>
cmla z0.h, z1.h, z2.h, #0
// CHECK-INST: cmla z0.h, z1.h, z2.h, #0
// CHECK-ENCODING: [0x20,0x20,0x42,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 42 44 <unknown>
cmla z0.s, z1.s, z2.s, #0
// CHECK-INST: cmla z0.s, z1.s, z2.s, #0
// CHECK-ENCODING: [0x20,0x20,0x82,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 82 44 <unknown>
cmla z0.d, z1.d, z2.d, #0
// CHECK-INST: cmla z0.d, z1.d, z2.d, #0
// CHECK-ENCODING: [0x20,0x20,0xc2,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 c2 44 <unknown>
cmla z29.b, z30.b, z31.b, #90
// CHECK-INST: cmla z29.b, z30.b, z31.b, #90
// CHECK-ENCODING: [0xdd,0x27,0x1f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 27 1f 44 <unknown>
cmla z29.h, z30.h, z31.h, #90
// CHECK-INST: cmla z29.h, z30.h, z31.h, #90
// CHECK-ENCODING: [0xdd,0x27,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 27 5f 44 <unknown>
cmla z29.s, z30.s, z31.s, #90
// CHECK-INST: cmla z29.s, z30.s, z31.s, #90
// CHECK-ENCODING: [0xdd,0x27,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 27 9f 44 <unknown>
cmla z29.d, z30.d, z31.d, #90
// CHECK-INST: cmla z29.d, z30.d, z31.d, #90
// CHECK-ENCODING: [0xdd,0x27,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 27 df 44 <unknown>
cmla z31.b, z31.b, z31.b, #180
// CHECK-INST: cmla z31.b, z31.b, z31.b, #180
// CHECK-ENCODING: [0xff,0x2b,0x1f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 2b 1f 44 <unknown>
cmla z31.h, z31.h, z31.h, #180
// CHECK-INST: cmla z31.h, z31.h, z31.h, #180
// CHECK-ENCODING: [0xff,0x2b,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 2b 5f 44 <unknown>
cmla z31.s, z31.s, z31.s, #180
// CHECK-INST: cmla z31.s, z31.s, z31.s, #180
// CHECK-ENCODING: [0xff,0x2b,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 2b 9f 44 <unknown>
cmla z31.d, z31.d, z31.d, #180
// CHECK-INST: cmla z31.d, z31.d, z31.d, #180
// CHECK-ENCODING: [0xff,0x2b,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 2b df 44 <unknown>
cmla z15.b, z16.b, z17.b, #270
// CHECK-INST: cmla z15.b, z16.b, z17.b, #270
// CHECK-ENCODING: [0x0f,0x2e,0x11,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 2e 11 44 <unknown>
cmla z15.h, z16.h, z17.h, #270
// CHECK-INST: cmla z15.h, z16.h, z17.h, #270
// CHECK-ENCODING: [0x0f,0x2e,0x51,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 2e 51 44 <unknown>
cmla z15.s, z16.s, z17.s, #270
// CHECK-INST: cmla z15.s, z16.s, z17.s, #270
// CHECK-ENCODING: [0x0f,0x2e,0x91,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 2e 91 44 <unknown>
cmla z15.d, z16.d, z17.d, #270
// CHECK-INST: cmla z15.d, z16.d, z17.d, #270
// CHECK-ENCODING: [0x0f,0x2e,0xd1,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 2e d1 44 <unknown>
cmla z0.h, z1.h, z2.h[0], #0
// CHECK-INST: cmla z0.h, z1.h, z2.h[0], #0
// CHECK-ENCODING: [0x20,0x60,0xa2,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 60 a2 44 <unknown>
cmla z0.s, z1.s, z2.s[0], #0
// CHECK-INST: cmla z0.s, z1.s, z2.s[0], #0
// CHECK-ENCODING: [0x20,0x60,0xe2,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 60 e2 44 <unknown>
cmla z31.h, z30.h, z7.h[0], #180
// CHECK-INST: cmla z31.h, z30.h, z7.h[0], #180
// CHECK-ENCODING: [0xdf,0x6b,0xa7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 6b a7 44 <unknown>
cmla z31.s, z30.s, z7.s[0], #180
// CHECK-INST: cmla z31.s, z30.s, z7.s[0], #180
// CHECK-ENCODING: [0xdf,0x6b,0xe7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 6b e7 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
cmla z4.d, z31.d, z31.d, #270
// CHECK-INST: cmla z4.d, z31.d, z31.d, #270
// CHECK-ENCODING: [0xe4,0x2f,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 2f df 44 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
cmla z21.s, z10.s, z5.s[1], #90
// CHECK-INST: cmla z21.s, z10.s, z5.s[1], #90
// CHECK-ENCODING: [0x55,0x65,0xf5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 55 65 f5 44 <unknown>

test/MC/AArch64/SVE2/directive-arch-negative.s

  • This file was added.
// RUN: not llvm-mc -filetype asm -o - %s 2>&1 | FileCheck %s
.arch armv8-a+nosve2
tbx z0.b, z1.b, z2.b
// CHECK: error: instruction requires: sve2
// CHECK-NEXT: tbx z0.b, z1.b, z2.b
.arch armv8-a+nosve2-aes
aesd z23.b, z23.b, z13.b
// CHECK: error: instruction requires: sve2-aes
// CHECK-NEXT: aesd z23.b, z23.b, z13.b
.arch armv8-a+nosve2-sm4
sm4e z0.s, z0.s, z0.s
// CHECK: error: instruction requires: sve2-sm4
// CHECK-NEXT: sm4e z0.s, z0.s, z0.s
.arch armv8-a+nosve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: error: instruction requires: sve2-sha3
// CHECK-NEXT: rax1 z0.d, z0.d, z0.d
.arch armv8-a+nobitperm
bgrp z21.s, z10.s, z21.s
// CHECK: error: instruction requires: bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s

test/MC/AArch64/SVE2/directive-arch.s

  • This file was added.
// RUN: llvm-mc -filetype asm -o - %s 2>&1 | FileCheck %s
.arch armv8-a+sve2
tbx z0.b, z1.b, z2.b
// CHECK: tbx z0.b, z1.b, z2.b
.arch armv8-a+sve2-aes
aesd z23.b, z23.b, z13.b
// CHECK: aesd z23.b, z23.b, z13.b
.arch armv8-a+sve2-sm4
sm4e z0.s, z0.s, z0.s
// CHECK: sm4e z0.s, z0.s, z0.s
.arch armv8-a+sve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: rax1 z0.d, z0.d, z0.d
.arch armv8-a+bitperm
bgrp z21.s, z10.s, z21.s
// CHECK: bgrp z21.s, z10.s, z21.s

test/MC/AArch64/SVE2/directive-arch_extension-negative.s

  • This file was added.
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
.arch_extension nosve2
tbx z0.b, z1.b, z2.b
// CHECK: error: instruction requires: sve2
// CHECK-NEXT: tbx z0.b, z1.b, z2.b
.arch_extension nosve2-aes
aesd z23.b, z23.b, z13.b
// CHECK: error: instruction requires: sve2-aes
// CHECK-NEXT: aesd z23.b, z23.b, z13.b
.arch_extension nosve2-sm4
sm4e z0.s, z0.s, z0.s
// CHECK: error: instruction requires: sve2-sm4
// CHECK-NEXT: sm4e z0.s, z0.s, z0.s
.arch_extension nosve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: error: instruction requires: sve2-sha3
// CHECK-NEXT: rax1 z0.d, z0.d, z0.d
.arch_extension nobitperm
bgrp z21.s, z10.s, z21.s
// CHECK: error: instruction requires: bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s

test/MC/AArch64/SVE2/directive-arch_extension.s

  • This file was added.
// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
.arch_extension sve2
tbx z0.b, z1.b, z2.b
// CHECK: tbx z0.b, z1.b, z2.b
.arch_extension sve2-aes
aesd z23.b, z23.b, z13.b
// CHECK: aesd z23.b, z23.b, z13.b
.arch_extension sve2-sm4
sm4e z0.s, z0.s, z0.s
// CHECK: sm4e z0.s, z0.s, z0.s
.arch_extension sve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: rax1 z0.d, z0.d, z0.d
.arch_extension bitperm
bgrp z21.s, z10.s, z21.s
// CHECK: bgrp z21.s, z10.s, z21.s

test/MC/AArch64/SVE2/directive-cpu-negative.s

  • This file was added.
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
.cpu generic+nosve2
tbx z0.b, z1.b, z2.b
// CHECK: error: instruction requires: sve2
// CHECK-NEXT: tbx z0.b, z1.b, z2.b
.cpu generic+nosve2-aes
aesd z23.b, z23.b, z13.b
// CHECK: error: instruction requires: sve2-aes
// CHECK-NEXT: aesd z23.b, z23.b, z13.b
.cpu generic+nosve2-sm4
sm4e z0.s, z0.s, z0.s
// CHECK: error: instruction requires: sve2-sm4
// CHECK-NEXT: sm4e z0.s, z0.s, z0.s
.cpu generic+nosve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: error: instruction requires: sve2-sha3
// CHECK-NEXT: rax1 z0.d, z0.d, z0.d
.cpu generic+nobitperm
bgrp z21.s, z10.s, z21.s
// CHECK: error: instruction requires: bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s

test/MC/AArch64/SVE2/directive-cpu.s

  • This file was added.
// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
.cpu generic+sve2
tbx z0.b, z1.b, z2.b
// CHECK: tbx z0.b, z1.b, z2.b
.cpu generic+sve2-aes
aesd z23.b, z23.b, z13.b
// CHECK: aesd z23.b, z23.b, z13.b
.cpu generic+sve2-sm4
sm4e z0.s, z0.s, z0.s
// CHECK: sm4e z0.s, z0.s, z0.s
.cpu generic+sve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: rax1 z0.d, z0.d, z0.d
.cpu generic+bitperm
bgrp z21.s, z10.s, z21.s
// CHECK: bgrp z21.s, z10.s, z21.s

test/MC/AArch64/SVE2/eor3-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
eor3 z0.b, z0.b, z1.s, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: eor3 z0.b, z0.b, z1.s, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eor3 z0.h, z0.h, z1.h, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: eor3 z0.h, z0.h, z1.h, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eor3 z0.d, z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: eor3 z0.d, z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
eor3 z0.d, z1.d, z2.d, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: eor3 z0.d, z1.d, z2.d, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
eor3 z0.d, z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: eor3 z0.d, z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/eor3.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
eor3 z29.d, z29.d, z30.d, z31.d
// CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 3e 04 <unknown>
// --------------------------------------------------------------------------//
// Test aliases.
eor3 z29.b, z29.b, z30.b, z31.b
// CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 3e 04 <unknown>
eor3 z29.h, z29.h, z30.h, z31.h
// CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 3e 04 <unknown>
eor3 z29.s, z29.s, z30.s, z31.s
// CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d
// CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fd 3b 3e 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z7
// CHECK-INST: movprfx z31, z7
// CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bc 20 04 <unknown>
eor3 z31.d, z31.d, z30.d, z29.d
// CHECK-INST: eor3 z31.d, z31.d, z30.d, z29.d
// CHECK-ENCODING: [0xbf,0x3b,0x3e,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bf 3b 3e 04 <unknown>

test/MC/AArch64/SVE2/eorbt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
eorbt z0.b, z1.h, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: eorbt z0.b, z1.h, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
eorbt z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: eorbt z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/eorbt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
eorbt z0.b, z1.b, z31.b
// CHECK-INST: eorbt z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x90,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 90 1f 45 <unknown>
eorbt z0.h, z1.h, z31.h
// CHECK-INST: eorbt z0.h, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x90,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 90 5f 45 <unknown>
eorbt z0.s, z1.s, z31.s
// CHECK-INST: eorbt z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x90,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 90 9f 45 <unknown>
eorbt z0.d, z1.d, z31.d
// CHECK-INST: eorbt z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x90,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 90 df 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
eorbt z0.d, z1.d, z31.d
// CHECK-INST: eorbt z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x90,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 90 df 45 <unknown>

test/MC/AArch64/SVE2/eortb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
eortb z0.b, z1.h, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: eortb z0.b, z1.h, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
eortb z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: eortb z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/eortb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
eortb z0.b, z1.b, z31.b
// CHECK-INST: eortb z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x94,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 94 1f 45 <unknown>
eortb z0.h, z1.h, z31.h
// CHECK-INST: eortb z0.h, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x94,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 94 5f 45 <unknown>
eortb z0.s, z1.s, z31.s
// CHECK-INST: eortb z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x94,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 94 9f 45 <unknown>
eortb z0.d, z1.d, z31.d
// CHECK-INST: eortb z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x94,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 94 df 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
eortb z0.d, z1.d, z31.d
// CHECK-INST: eortb z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x94,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 94 df 45 <unknown>

test/MC/AArch64/SVE2/ext-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element widths.
ext z0.h, { z1.h, z2.h }, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ext z0.h, { z1.h, z2.h }, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ext z0.s, { z1.s, z2.s }, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ext z0.s, { z1.s, z2.s }, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ext z0.d, { z1.d, z2.d }, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ext z0.d, { z1.d, z2.d }, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid immediate range.
ext z0.b, { z1.b, z2.b }, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
// CHECK-NEXT: ext z0.b, { z1.b, z2.b }, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ext z0.b, { z1.b, z2.b }, #256
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
// CHECK-NEXT: ext z0.b, { z1.b, z2.b }, #256
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
ext z0.b, { }, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: ext z0.b, { }, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ext z0.b, { z1.b }, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ext z0.b, { z1.b }, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ext z0.b, { z1.b, z2.b, z3.b }, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ext z0.b, { z1.b, z2.b, z3.b }, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ext z0.b, { z1.b, z2.h }, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
// CHECK-NEXT: ext z0.b, { z1.b, z2.h }, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ext z0.b, { z1.b, z31.b }, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: ext z0.b, { z1.b, z31.b }, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ext z0.b, { v0.4b, v1.4b }, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ext z0.b, { v0.4b, v1.4b }, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
ext z31.b, { z30.b, z31.b }, #255
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ext z31.b, { z30.b, z31.b }, #255
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.b, p0/z, z6.b
ext z31.b, { z30.b, z31.b }, #255
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ext z31.b, { z30.b, z31.b }, #255
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ext.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ext z0.b, { z1.b, z2.b }, #0
// CHECK-INST: ext z0.b, { z1.b, z2.b }, #0
// CHECK-ENCODING: [0x20,0x00,0x60,0x05]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 00 60 05 <unknown>
ext z31.b, { z30.b, z31.b }, #255
// CHECK-INST: ext z31.b, { z30.b, z31.b }, #255
// CHECK-ENCODING: [0xdf,0x1f,0x7f,0x05]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 1f 7f 05 <unknown>

test/MC/AArch64/SVE2/faddp-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
faddp z0.h, p0/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: faddp z0.h, p0/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
faddp z0.b, p0/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: faddp z0.b, p0/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
faddp z0.h, p0/m, z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: faddp z0.h, p0/m, z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
faddp z0.h, p0/m, z0.h, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: faddp z0.h, p0/m, z0.h, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
faddp z0.h, p8/m, z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: faddp z0.h, p8/m, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/faddp.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
faddp z0.h, p0/m, z0.h, z1.h
// CHECK-INST: faddp z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x50,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 50 64 <unknown>
faddp z29.s, p3/m, z29.s, z30.s
// CHECK-INST: faddp z29.s, p3/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x8f,0x90,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 8f 90 64 <unknown>
faddp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: faddp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd0,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d0 64 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
faddp z31.d, p0/m, z31.d, z30.d
// CHECK-INST: faddp z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xd0,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 d0 64 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
faddp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: faddp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd0,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d0 64 <unknown>

test/MC/AArch64/SVE2/fcvtlt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid element width
fcvtlt z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtlt z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtlt z0.h, p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtlt z0.h, p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtlt z0.s, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtlt z0.s, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtlt z0.d, p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtlt z0.d, p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtlt z0.h, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtlt z0.h, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtlt z0.q, p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtlt z0.q, p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid predicate operation
fcvtlt z0.s, p0/z, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvtlt z0.s, p0/z, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
fcvtlt z0.s, p8/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: fcvtlt z0.s, p8/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/m, z7.s
fcvtlt z0.s, p7/m, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcvtlt z0.s, p7/m, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcvtlt z0.s, p7/m, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcvtlt z0.s, p7/m, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fcvtlt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
fcvtlt z0.s, p0/m, z1.h
// CHECK-INST: fcvtlt z0.s, p0/m, z1.h
// CHECK-ENCODING: [0x20,0xa0,0x89,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 89 64 <unknown>
fcvtlt z30.d, p7/m, z31.s
// CHECK-INST: fcvtlt z30.d, p7/m, z31.s
// CHECK-ENCODING: [0xfe,0xbf,0xcb,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fe bf cb 64 <unknown>

test/MC/AArch64/SVE2/fcvtnt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid element width
fcvtnt z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtnt z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtnt z0.h, p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtnt z0.h, p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtnt z0.s, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtnt z0.s, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtnt z0.d, p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtnt z0.d, p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtnt z0.b, p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtnt z0.b, p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtnt z0.d, p0/m, z0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtnt z0.d, p0/m, z0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid predicate operation
fcvtnt z0.h, p0/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvtnt z0.h, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
fcvtnt z0.h, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: fcvtnt z0.h, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/m, z7.s
fcvtnt z0.s, p7/m, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcvtnt z0.s, p7/m, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcvtnt z0.s, p7/m, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcvtnt z0.s, p7/m, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fcvtnt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
fcvtnt z0.h, p0/m, z1.s
// CHECK-INST: fcvtnt z0.h, p0/m, z1.s
// CHECK-ENCODING: [0x20,0xa0,0x88,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 88 64 <unknown>
fcvtnt z30.s, p7/m, z31.d
// CHECK-INST: fcvtnt z30.s, p7/m, z31.d
// CHECK-ENCODING: [0xfe,0xbf,0xca,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fe bf ca 64 <unknown>

test/MC/AArch64/SVE2/fcvtx-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid element width
fcvtx z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtx z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtx z0.h, p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtx z0.h, p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtx z0.s, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtx z0.s, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtx z0.d, p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtx z0.d, p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
fcvtx z0.s, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: fcvtx z0.s, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fcvtx.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
fcvtx z0.s, p0/m, z0.d
// CHECK-INST: fcvtx z0.s, p0/m, z0.d
// CHECK-ENCODING: [0x00,0xa0,0x0a,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 a0 0a 65 <unknown>
fcvtx z30.s, p7/m, z31.d
// CHECK-INST: fcvtx z30.s, p7/m, z31.d
// CHECK-ENCODING: [0xfe,0xbf,0x0a,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fe bf 0a 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z5.d, p0/z, z7.d
// CHECK-INST: movprfx z5.d, p0/z, z7.d
// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
fcvtx z5.s, p0/m, z0.d
// CHECK-INST: fcvtx z5.s, p0/m, z0.d
// CHECK-ENCODING: [0x05,0xa0,0x0a,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 05 a0 0a 65 <unknown>
movprfx z5, z7
// CHECK-INST: movprfx z5, z7
// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
fcvtx z5.s, p0/m, z0.d
// CHECK-INST: fcvtx z5.s, p0/m, z0.d
// CHECK-ENCODING: [0x05,0xa0,0x0a,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 05 a0 0a 65 <unknown>

test/MC/AArch64/SVE2/fcvtxnt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid element width
fcvtxnt z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtxnt z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtxnt z0.h, p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtxnt z0.h, p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtxnt z0.s, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtxnt z0.s, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtxnt z0.d, p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtxnt z0.d, p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtxnt z0.h, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtxnt z0.h, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtxnt z0.b, p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtxnt z0.b, p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtxnt z0.d, p0/m, z0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtxnt z0.d, p0/m, z0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid predicate operation
fcvtxnt z0.s, p0/z, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvtxnt z0.s, p0/z, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
fcvtxnt z0.s, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: fcvtxnt z0.s, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/m, z7.s
fcvtxnt z0.s, p7/m, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcvtxnt z0.s, p7/m, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
fcvtxnt z0.s, p7/m, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: fcvtxnt z0.s, p7/m, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fcvtxnt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
fcvtxnt z0.s, p0/m, z1.d
// CHECK-INST: fcvtxnt z0.s, p0/m, z1.d
// CHECK-ENCODING: [0x20,0xa0,0x0a,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 0a 64 <unknown>
fcvtxnt z30.s, p7/m, z31.d
// CHECK-INST: fcvtxnt z30.s, p7/m, z31.d
// CHECK-ENCODING: [0xfe,0xbf,0x0a,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fe bf 0a 64 <unknown>

test/MC/AArch64/SVE2/flogb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid element width
flogb z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: flogb z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid predicate operation
flogb z0.s, p0/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: flogb z0.s, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
flogb z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]
// CHECK-NEXT: flogb z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/flogb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
flogb z31.h, p7/m, z31.h
// CHECK-INST: flogb z31.h, p7/m, z31.h
// CHECK-ENCODING: [0xff,0xbf,0x1a,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 1a 65 <unknown>
flogb z31.s, p7/m, z31.s
// CHECK-INST: flogb z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x1c,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 1c 65 <unknown>
flogb z31.d, p7/m, z31.d
// CHECK-INST: flogb z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0x1e,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 1e 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
flogb z4.d, p7/m, z31.d
// CHECK-INST: flogb z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0x1e,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 1e 65 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
flogb z4.d, p7/m, z31.d
// CHECK-INST: flogb z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0x1e,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 1e 65 <unknown>

test/MC/AArch64/SVE2/fmaxnmp-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
fmaxnmp z0.h, p0/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: fmaxnmp z0.h, p0/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
fmaxnmp z0.b, p0/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmaxnmp z0.b, p0/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
fmaxnmp z0.h, p0/m, z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmaxnmp z0.h, p0/m, z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmaxnmp z0.h, p0/m, z0.h, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmaxnmp z0.h, p0/m, z0.h, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
fmaxnmp z0.h, p8/m, z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: fmaxnmp z0.h, p8/m, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fmaxnmp.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
fmaxnmp z0.h, p0/m, z0.h, z1.h
// CHECK-INST: fmaxnmp z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x54,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 54 64 <unknown>
fmaxnmp z29.s, p3/m, z29.s, z30.s
// CHECK-INST: fmaxnmp z29.s, p3/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x8f,0x94,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 8f 94 64 <unknown>
fmaxnmp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: fmaxnmp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd4,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d4 64 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
fmaxnmp z31.d, p0/m, z31.d, z30.d
// CHECK-INST: fmaxnmp z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xd4,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 d4 64 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
fmaxnmp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: fmaxnmp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd4,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d4 64 <unknown>

test/MC/AArch64/SVE2/fmaxp-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
fmaxp z0.h, p0/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: fmaxp z0.h, p0/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
fmaxp z0.b, p0/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmaxp z0.b, p0/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
fmaxp z0.h, p0/m, z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmaxp z0.h, p0/m, z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmaxp z0.h, p0/m, z0.h, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmaxp z0.h, p0/m, z0.h, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
fmaxp z0.h, p8/m, z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: fmaxp z0.h, p8/m, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fmaxp.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
fmaxp z0.h, p0/m, z0.h, z1.h
// CHECK-INST: fmaxp z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x56,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 56 64 <unknown>
fmaxp z29.s, p3/m, z29.s, z30.s
// CHECK-INST: fmaxp z29.s, p3/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x8f,0x96,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 8f 96 64 <unknown>
fmaxp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: fmaxp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd6,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d6 64 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
fmaxp z31.d, p0/m, z31.d, z30.d
// CHECK-INST: fmaxp z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xd6,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 d6 64 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
fmaxp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: fmaxp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd6,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d6 64 <unknown>

test/MC/AArch64/SVE2/fminnmp-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
fminnmp z0.h, p0/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: fminnmp z0.h, p0/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
fminnmp z0.b, p0/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fminnmp z0.b, p0/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
fminnmp z0.h, p0/m, z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fminnmp z0.h, p0/m, z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fminnmp z0.h, p0/m, z0.h, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fminnmp z0.h, p0/m, z0.h, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
fminnmp z0.h, p8/m, z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: fminnmp z0.h, p8/m, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fminnmp.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
fminnmp z0.h, p0/m, z0.h, z1.h
// CHECK-INST: fminnmp z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x55,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 55 64 <unknown>
fminnmp z29.s, p3/m, z29.s, z30.s
// CHECK-INST: fminnmp z29.s, p3/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x8f,0x95,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 8f 95 64 <unknown>
fminnmp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: fminnmp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd5,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d5 64 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
fminnmp z31.d, p0/m, z31.d, z30.d
// CHECK-INST: fminnmp z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xd5,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 d5 64 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
fminnmp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: fminnmp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd5,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d5 64 <unknown>

test/MC/AArch64/SVE2/fminp-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
fminp z0.h, p0/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: fminp z0.h, p0/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
fminp z0.b, p0/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fminp z0.b, p0/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
fminp z0.h, p0/m, z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fminp z0.h, p0/m, z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fminp z0.h, p0/m, z0.h, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fminp z0.h, p0/m, z0.h, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
fminp z0.h, p8/m, z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: fminp z0.h, p8/m, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fminp.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
fminp z0.h, p0/m, z0.h, z1.h
// CHECK-INST: fminp z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x57,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 57 64 <unknown>
fminp z29.s, p3/m, z29.s, z30.s
// CHECK-INST: fminp z29.s, p3/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x8f,0x97,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 8f 97 64 <unknown>
fminp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: fminp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd7,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d7 64 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
fminp z31.d, p0/m, z31.d, z30.d
// CHECK-INST: fminp z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xd7,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 d7 64 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
fminp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: fminp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd7,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d7 64 <unknown>

test/MC/AArch64/SVE2/fmlalb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
fmlalb z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmlalb z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
fmlalb z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmlalb z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmlalb z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmlalb z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
fmlalb z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmlalb z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmlalb z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmlalb z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmlalb z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmlalb z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z29.s, p0/z, z7.s
fmlalb z29.s, z30.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: fmlalb z29.s, z30.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
fmlalb z0.s, z1.h, z7.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: fmlalb z0.s, z1.h, z7.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fmlalb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
fmlalb z29.s, z30.h, z31.h
// CHECK-INST: fmlalb z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x83,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 83 bf 64 <unknown>
fmlalb z0.s, z1.h, z7.h[0]
// CHECK-INST: fmlalb z0.s, z1.h, z7.h[0]
// CHECK-ENCODING: [0x20,0x40,0xa7,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 40 a7 64 <unknown>
fmlalb z30.s, z31.h, z7.h[7]
// CHECK-INST: fmlalb z30.s, z31.h, z7.h[7]
// CHECK-ENCODING: [0xfe,0x4b,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fe 4b bf 64 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z29, z28
// CHECK-INST: movprfx z29, z28
// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
fmlalb z29.s, z30.h, z31.h
// CHECK-INST: fmlalb z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x83,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 83 bf 64 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
fmlalb z21.s, z1.h, z7.h[7]
// CHECK-INST: fmlalb z21.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x35,0x48,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 48 bf 64 <unknown>

test/MC/AArch64/SVE2/fmlalt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
fmlalt z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmlalt z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
fmlalt z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmlalt z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmlalt z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmlalt z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
fmlalt z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmlalt z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmlalt z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmlalt z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmlalt z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmlalt z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z29.s, p0/z, z7.s
fmlalt z29.s, z30.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: fmlalt z29.s, z30.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
fmlalt z0.s, z1.h, z7.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: fmlalt z0.s, z1.h, z7.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fmlalt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
fmlalt z29.s, z30.h, z31.h
// CHECK-INST: fmlalt z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x87,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 87 bf 64 <unknown>
fmlalt z0.s, z1.h, z7.h[0]
// CHECK-INST: fmlalt z0.s, z1.h, z7.h[0]
// CHECK-ENCODING: [0x20,0x44,0xa7,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 44 a7 64 <unknown>
fmlalt z30.s, z31.h, z7.h[7]
// CHECK-INST: fmlalt z30.s, z31.h, z7.h[7]
// CHECK-ENCODING: [0xfe,0x4f,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fe 4f bf 64 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z29, z28
// CHECK-INST: movprfx z29, z28
// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
fmlalt z29.s, z30.h, z31.h
// CHECK-INST: fmlalt z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x87,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 87 bf 64 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
fmlalt z21.s, z1.h, z7.h[7]
// CHECK-INST: fmlalt z21.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x35,0x4c,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 4c bf 64 <unknown>

test/MC/AArch64/SVE2/fmlslb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
fmlslb z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmlslb z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
fmlslb z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmlslb z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmlslb z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmlslb z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
fmlslb z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmlslb z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmlslb z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmlslb z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmlslb z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmlslb z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z29.s, p0/z, z7.s
fmlslb z29.s, z30.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: fmlslb z29.s, z30.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
fmlslb z0.s, z1.h, z7.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: fmlslb z0.s, z1.h, z7.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fmlslb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
fmlslb z29.s, z30.h, z31.h
// CHECK-INST: fmlslb z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0xa3,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd a3 bf 64 <unknown>
fmlslb z0.s, z1.h, z7.h[0]
// CHECK-INST: fmlslb z0.s, z1.h, z7.h[0]
// CHECK-ENCODING: [0x20,0x60,0xa7,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 60 a7 64 <unknown>
fmlslb z30.s, z31.h, z7.h[7]
// CHECK-INST: fmlslb z30.s, z31.h, z7.h[7]
// CHECK-ENCODING: [0xfe,0x6b,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fe 6b bf 64 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z29, z28
// CHECK-INST: movprfx z29, z28
// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
fmlslb z29.s, z30.h, z31.h
// CHECK-INST: fmlslb z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0xa3,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd a3 bf 64 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
fmlslb z21.s, z1.h, z7.h[7]
// CHECK-INST: fmlslb z21.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x35,0x68,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 68 bf 64 <unknown>

test/MC/AArch64/SVE2/fmlslt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
fmlslt z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmlslt z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
fmlslt z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmlslt z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmlslt z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmlslt z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
fmlslt z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmlslt z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmlslt z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmlslt z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmlslt z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmlslt z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z29.s, p0/z, z7.s
fmlslt z29.s, z30.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: fmlslt z29.s, z30.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
fmlslt z0.s, z1.h, z7.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: fmlslt z0.s, z1.h, z7.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/fmlslt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
fmlslt z29.s, z30.h, z31.h
// CHECK-INST: fmlslt z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0xa7,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd a7 bf 64 <unknown>
fmlslt z0.s, z1.h, z7.h[0]
// CHECK-INST: fmlslt z0.s, z1.h, z7.h[0]
// CHECK-ENCODING: [0x20,0x64,0xa7,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 64 a7 64 <unknown>
fmlslt z30.s, z31.h, z7.h[7]
// CHECK-INST: fmlslt z30.s, z31.h, z7.h[7]
// CHECK-ENCODING: [0xfe,0x6f,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fe 6f bf 64 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z29, z28
// CHECK-INST: movprfx z29, z28
// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
fmlslt z29.s, z30.h, z31.h
// CHECK-INST: fmlslt z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0xa7,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd a7 bf 64 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
fmlslt z21.s, z1.h, z7.h[7]
// CHECK-INST: fmlslt z21.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x35,0x6c,0xbf,0x64]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 6c bf 64 <unknown>

test/MC/AArch64/SVE2/histcnt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid element width
histcnt z0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: histcnt z0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
histcnt z0.h, p0/z, z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: histcnt z0.h, p0/z, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid predicate operation
histcnt z0.s, p0/m, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: histcnt z0.s, p0/m, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
histcnt z0.s, p8/z, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: histcnt z0.s, p8/z, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/z, z7.s
histcnt z0.s, p7/z, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: histcnt z0.s, p7/z, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
histcnt z0.s, p7/z, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: histcnt z0.s, p7/z, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/histcnt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
histcnt z0.s, p0/z, z1.s, z2.s
// CHECK-INST: histcnt z0.s, p0/z, z1.s, z2.s
// CHECK-ENCODING: [0x20,0xc0,0xa2,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c0 a2 45 <unknown>
histcnt z29.d, p7/z, z30.d, z31.d
// CHECK-INST: histcnt z29.d, p7/z, z30.d, z31.d
// CHECK-ENCODING: [0xdd,0xdf,0xff,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd df ff 45 <unknown>

test/MC/AArch64/SVE2/histseg-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid element width
histseg z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: histseg z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
histseg z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: histseg z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
histseg z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: histseg z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
histseg z31.b, z30.b, z29.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: histseg z31.b, z30.b, z29.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.b, p0/m, z6.b
histseg z31.b, z30.b, z29.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: histseg z31.b, z30.b, z29.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/histseg.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
histseg z0.b, z1.b, z31.b
// CHECK-INST: histseg z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xa0,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 3f 45 <unknown>

test/MC/AArch64/SVE2/ldnt1b-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid result type.
ldnt1b { z0.b }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1b { z0.b }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1b { z0.h }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1b { z0.h }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid base vector.
ldnt1b { z0.s }, p0/z, [z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldnt1b { z0.s }, p0/z, [z0.b]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1b { z0.d }, p0/z, [z0.h]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldnt1b { z0.d }, p0/z, [z0.h]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid offset type.
ldnt1b { z0.d }, p0/z, [z0.d, z1.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1b { z0.d }, p0/z, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// restricted predicate has range [0, 7].
ldnt1b { z27.d }, p8/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ldnt1b { z27.d }, p8/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
ldnt1b { }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: ldnt1b { }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1b { z0.d, z1.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1b { z0.d, z1.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1b { v0.2d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1b { v0.2d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ldnt1b { z0.d }, p0/z, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1b { z0.d }, p0/z, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldnt1b { z0.s }, p0/z, [z0.s, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1b { z0.s }, p0/z, [z0.s, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ldnt1b.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ldnt1b z0.s, p0/z, [z1.s]
// CHECK-INST: ldnt1b { z0.s }, p0/z, [z1.s]
// CHECK-ENCODING: [0x20,0xa0,0x1f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 1f 84 <unknown>
ldnt1b z31.s, p7/z, [z31.s, xzr]
// CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s]
// CHECK-ENCODING: [0xff,0xbf,0x1f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 1f 84 <unknown>
ldnt1b z31.s, p7/z, [z31.s, x0]
// CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s, x0]
// CHECK-ENCODING: [0xff,0xbf,0x00,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 00 84 <unknown>
ldnt1b z0.d, p0/z, [z1.d]
// CHECK-INST: ldnt1b { z0.d }, p0/z, [z1.d]
// CHECK-ENCODING: [0x20,0xc0,0x1f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c0 1f c4 <unknown>
ldnt1b z31.d, p7/z, [z31.d, xzr]
// CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d]
// CHECK-ENCODING: [0xff,0xdf,0x1f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 1f c4 <unknown>
ldnt1b z31.d, p7/z, [z31.d, x0]
// CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d, x0]
// CHECK-ENCODING: [0xff,0xdf,0x00,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 00 c4 <unknown>
ldnt1b { z0.s }, p0/z, [z1.s]
// CHECK-INST: ldnt1b { z0.s }, p0/z, [z1.s]
// CHECK-ENCODING: [0x20,0xa0,0x1f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 1f 84 <unknown>
ldnt1b { z31.s }, p7/z, [z31.s, xzr]
// CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s]
// CHECK-ENCODING: [0xff,0xbf,0x1f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 1f 84 <unknown>
ldnt1b { z31.s }, p7/z, [z31.s, x0]
// CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s, x0]
// CHECK-ENCODING: [0xff,0xbf,0x00,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 00 84 <unknown>
ldnt1b { z0.d }, p0/z, [z1.d]
// CHECK-INST: ldnt1b { z0.d }, p0/z, [z1.d]
// CHECK-ENCODING: [0x20,0xc0,0x1f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c0 1f c4 <unknown>
ldnt1b { z31.d }, p7/z, [z31.d, xzr]
// CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d]
// CHECK-ENCODING: [0xff,0xdf,0x1f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 1f c4 <unknown>
ldnt1b { z31.d }, p7/z, [z31.d, x0]
// CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d, x0]
// CHECK-ENCODING: [0xff,0xdf,0x00,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 00 c4 <unknown>

test/MC/AArch64/SVE2/ldnt1d-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid result type.
ldnt1d { z0.b }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1d { z0.b }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1d { z0.h }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1d { z0.h }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1d { z0.s }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1d { z0.s }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid base vector.
ldnt1d { z0.d }, p0/z, [z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [z0.b]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid offset type.
ldnt1d { z0.d }, p0/z, [z0.d, z1.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// restricted predicate has range [0, 7].
ldnt1d { z27.d }, p8/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ldnt1d { z27.d }, p8/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
ldnt1d { }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: ldnt1d { }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1d { z0.d, z1.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1d { z0.d, z1.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1d { v0.2d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1d { v0.2d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ldnt1d { z0.d }, p0/z, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldnt1d { z0.d }, p0/z, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ldnt1d.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ldnt1d z0.d, p0/z, [z1.d]
// CHECK-INST: ldnt1d { z0.d }, p0/z, [z1.d]
// CHECK-ENCODING: [0x20,0xc0,0x9f,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c0 9f c5 <unknown>
ldnt1d z31.d, p7/z, [z31.d, xzr]
// CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d]
// CHECK-ENCODING: [0xff,0xdf,0x9f,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 9f c5 <unknown>
ldnt1d z31.d, p7/z, [z31.d, x0]
// CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d, x0]
// CHECK-ENCODING: [0xff,0xdf,0x80,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 80 c5 <unknown>
ldnt1d { z0.d }, p0/z, [z1.d]
// CHECK-INST: ldnt1d { z0.d }, p0/z, [z1.d]
// CHECK-ENCODING: [0x20,0xc0,0x9f,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c0 9f c5 <unknown>
ldnt1d { z31.d }, p7/z, [z31.d, xzr]
// CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d]
// CHECK-ENCODING: [0xff,0xdf,0x9f,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 9f c5 <unknown>
ldnt1d { z31.d }, p7/z, [z31.d, x0]
// CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d, x0]
// CHECK-ENCODING: [0xff,0xdf,0x80,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 80 c5 <unknown>

test/MC/AArch64/SVE2/ldnt1h-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid result type.
ldnt1h { z0.b }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1h { z0.b }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1h { z0.h }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1h { z0.h }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid base vector.
ldnt1h { z0.s }, p0/z, [z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldnt1h { z0.s }, p0/z, [z0.b]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1h { z0.d }, p0/z, [z0.h]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldnt1h { z0.d }, p0/z, [z0.h]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid offset type.
ldnt1h { z0.d }, p0/z, [z0.d, z1.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1h { z0.d }, p0/z, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// restricted predicate has range [0, 7].
ldnt1h { z27.d }, p8/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ldnt1h { z27.d }, p8/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
ldnt1h { }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: ldnt1h { }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1h { z0.d, z1.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1h { z0.d, z1.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1h { v0.2d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1h { v0.2d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ldnt1h { z0.d }, p0/z, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1h { z0.d }, p0/z, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldnt1h { z0.s }, p0/z, [z0.s, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1h { z0.s }, p0/z, [z0.s, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ldnt1h.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ldnt1h z0.s, p0/z, [z1.s]
// CHECK-INST: ldnt1h { z0.s }, p0/z, [z1.s]
// CHECK-ENCODING: [0x20,0xa0,0x9f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 9f 84 <unknown>
ldnt1h z31.s, p7/z, [z31.s, xzr]
// CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s]
// CHECK-ENCODING: [0xff,0xbf,0x9f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 9f 84 <unknown>
ldnt1h z31.s, p7/z, [z31.s, x0]
// CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s, x0]
// CHECK-ENCODING: [0xff,0xbf,0x80,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 80 84 <unknown>
ldnt1h z0.d, p0/z, [z1.d]
// CHECK-INST: ldnt1h { z0.d }, p0/z, [z1.d]
// CHECK-ENCODING: [0x20,0xc0,0x9f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c0 9f c4 <unknown>
ldnt1h z31.d, p7/z, [z31.d, xzr]
// CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d]
// CHECK-ENCODING: [0xff,0xdf,0x9f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 9f c4 <unknown>
ldnt1h z31.d, p7/z, [z31.d, x0]
// CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d, x0]
// CHECK-ENCODING: [0xff,0xdf,0x80,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 80 c4 <unknown>
ldnt1h { z0.s }, p0/z, [z1.s]
// CHECK-INST: ldnt1h { z0.s }, p0/z, [z1.s]
// CHECK-ENCODING: [0x20,0xa0,0x9f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 9f 84 <unknown>
ldnt1h { z31.s }, p7/z, [z31.s, xzr]
// CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s]
// CHECK-ENCODING: [0xff,0xbf,0x9f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 9f 84 <unknown>
ldnt1h { z31.s }, p7/z, [z31.s, x0]
// CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s, x0]
// CHECK-ENCODING: [0xff,0xbf,0x80,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 80 84 <unknown>
ldnt1h { z0.d }, p0/z, [z1.d]
// CHECK-INST: ldnt1h { z0.d }, p0/z, [z1.d]
// CHECK-ENCODING: [0x20,0xc0,0x9f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c0 9f c4 <unknown>
ldnt1h { z31.d }, p7/z, [z31.d, xzr]
// CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d]
// CHECK-ENCODING: [0xff,0xdf,0x9f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 9f c4 <unknown>
ldnt1h { z31.d }, p7/z, [z31.d, x0]
// CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d, x0]
// CHECK-ENCODING: [0xff,0xdf,0x80,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 80 c4 <unknown>

test/MC/AArch64/SVE2/ldnt1sb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid result type.
ldnt1sb { z0.b }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sb { z0.b }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1sb { z0.h }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sb { z0.h }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid base vector.
ldnt1sb { z0.s }, p0/z, [z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldnt1sb { z0.s }, p0/z, [z0.b]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1sb { z0.d }, p0/z, [z0.h]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldnt1sb { z0.d }, p0/z, [z0.h]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid offset type.
ldnt1sb { z0.d }, p0/z, [z0.d, z1.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sb { z0.d }, p0/z, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// restricted predicate has range [0, 7].
ldnt1sb { z27.d }, p8/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ldnt1sb { z27.d }, p8/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
ldnt1sb { }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: ldnt1sb { }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1sb { z0.d, z1.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sb { z0.d, z1.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1sb { v0.2d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sb { v0.2d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ldnt1sb { z0.d }, p0/z, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1sb { z0.d }, p0/z, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldnt1sb { z0.s }, p0/z, [z0.s, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1sb { z0.s }, p0/z, [z0.s, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ldnt1sb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ldnt1sb z0.s, p0/z, [z1.s]
// CHECK-INST: ldnt1sb { z0.s }, p0/z, [z1.s]
// CHECK-ENCODING: [0x20,0x80,0x1f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 1f 84 <unknown>
ldnt1sb z31.s, p7/z, [z31.s, xzr]
// CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s]
// CHECK-ENCODING: [0xff,0x9f,0x1f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 1f 84 <unknown>
ldnt1sb z31.s, p7/z, [z31.s, x0]
// CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x9f,0x00,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 00 84 <unknown>
ldnt1sb z0.d, p0/z, [z1.d]
// CHECK-INST: ldnt1sb { z0.d }, p0/z, [z1.d]
// CHECK-ENCODING: [0x20,0x80,0x1f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 1f c4 <unknown>
ldnt1sb z31.d, p7/z, [z31.d, xzr]
// CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d]
// CHECK-ENCODING: [0xff,0x9f,0x1f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 1f c4 <unknown>
ldnt1sb z31.d, p7/z, [z31.d, x0]
// CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x9f,0x00,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 00 c4 <unknown>
ldnt1sb { z0.s }, p0/z, [z1.s]
// CHECK-INST: ldnt1sb { z0.s }, p0/z, [z1.s]
// CHECK-ENCODING: [0x20,0x80,0x1f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 1f 84 <unknown>
ldnt1sb { z31.s }, p7/z, [z31.s, xzr]
// CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s]
// CHECK-ENCODING: [0xff,0x9f,0x1f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 1f 84 <unknown>
ldnt1sb { z31.s }, p7/z, [z31.s, x0]
// CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x9f,0x00,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 00 84 <unknown>
ldnt1sb { z0.d }, p0/z, [z1.d]
// CHECK-INST: ldnt1sb { z0.d }, p0/z, [z1.d]
// CHECK-ENCODING: [0x20,0x80,0x1f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 1f c4 <unknown>
ldnt1sb { z31.d }, p7/z, [z31.d, xzr]
// CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d]
// CHECK-ENCODING: [0xff,0x9f,0x1f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 1f c4 <unknown>
ldnt1sb { z31.d }, p7/z, [z31.d, x0]
// CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x9f,0x00,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 00 c4 <unknown>

test/MC/AArch64/SVE2/ldnt1sh-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid result type.
ldnt1sh { z0.b }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sh { z0.b }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1sh { z0.h }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sh { z0.h }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid base vector.
ldnt1sh { z0.s }, p0/z, [z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldnt1sh { z0.s }, p0/z, [z0.b]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1sh { z0.d }, p0/z, [z0.h]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldnt1sh { z0.d }, p0/z, [z0.h]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid offset type.
ldnt1sh { z0.d }, p0/z, [z0.d, z1.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sh { z0.d }, p0/z, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// restricted predicate has range [0, 7].
ldnt1sh { z27.d }, p8/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ldnt1sh { z27.d }, p8/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
ldnt1sh { }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: ldnt1sh { }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1sh { z0.d, z1.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sh { z0.d, z1.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1sh { v0.2d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sh { v0.2d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ldnt1sh { z0.d }, p0/z, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1sh { z0.d }, p0/z, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldnt1sh { z0.s }, p0/z, [z0.s, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1sh { z0.s }, p0/z, [z0.s, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ldnt1sh.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ldnt1sh z0.s, p0/z, [z1.s]
// CHECK-INST: ldnt1sh { z0.s }, p0/z, [z1.s]
// CHECK-ENCODING: [0x20,0x80,0x9f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 9f 84 <unknown>
ldnt1sh z31.s, p7/z, [z31.s, xzr]
// CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s]
// CHECK-ENCODING: [0xff,0x9f,0x9f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 9f 84 <unknown>
ldnt1sh z31.s, p7/z, [z31.s, x0]
// CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x9f,0x80,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 80 84 <unknown>
ldnt1sh z0.d, p0/z, [z1.d]
// CHECK-INST: ldnt1sh { z0.d }, p0/z, [z1.d]
// CHECK-ENCODING: [0x20,0x80,0x9f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 9f c4 <unknown>
ldnt1sh z31.d, p7/z, [z31.d, xzr]
// CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d]
// CHECK-ENCODING: [0xff,0x9f,0x9f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 9f c4 <unknown>
ldnt1sh z31.d, p7/z, [z31.d, x0]
// CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x9f,0x80,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 80 c4 <unknown>
ldnt1sh { z0.s }, p0/z, [z1.s]
// CHECK-INST: ldnt1sh { z0.s }, p0/z, [z1.s]
// CHECK-ENCODING: [0x20,0x80,0x9f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 9f 84 <unknown>
ldnt1sh { z31.s }, p7/z, [z31.s, xzr]
// CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s]
// CHECK-ENCODING: [0xff,0x9f,0x9f,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 9f 84 <unknown>
ldnt1sh { z31.s }, p7/z, [z31.s, x0]
// CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x9f,0x80,0x84]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 80 84 <unknown>
ldnt1sh { z0.d }, p0/z, [z1.d]
// CHECK-INST: ldnt1sh { z0.d }, p0/z, [z1.d]
// CHECK-ENCODING: [0x20,0x80,0x9f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 9f c4 <unknown>
ldnt1sh { z31.d }, p7/z, [z31.d, xzr]
// CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d]
// CHECK-ENCODING: [0xff,0x9f,0x9f,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 9f c4 <unknown>
ldnt1sh { z31.d }, p7/z, [z31.d, x0]
// CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x9f,0x80,0xc4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 80 c4 <unknown>

test/MC/AArch64/SVE2/ldnt1sw-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid result type.
ldnt1sw { z0.b }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sw { z0.b }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1sw { z0.h }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sw { z0.h }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1sw { z0.s }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sw { z0.s }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid base vector.
ldnt1sw { z0.d }, p0/z, [z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldnt1sw { z0.d }, p0/z, [z0.b]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid offset type.
ldnt1sw { z0.d }, p0/z, [z0.d, z1.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sw { z0.d }, p0/z, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// restricted predicate has range [0, 7].
ldnt1sw { z27.d }, p8/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ldnt1sw { z27.d }, p8/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
ldnt1sw { }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: ldnt1sw { }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1sw { z0.d, z1.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sw { z0.d, z1.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1sw { v0.2d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1sw { v0.2d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ldnt1sw { z0.d }, p0/z, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1sw { z0.d }, p0/z, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldnt1sw { z0.d }, p0/z, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1sw { z0.d }, p0/z, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ldnt1sw.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ldnt1sw z0.d, p0/z, [z1.d]
// CHECK-INST: ldnt1sw { z0.d }, p0/z, [z1.d]
// CHECK-ENCODING: [0x20,0x80,0x1f,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 1f c5 <unknown>
ldnt1sw z31.d, p7/z, [z31.d, xzr]
// CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d]
// CHECK-ENCODING: [0xff,0x9f,0x1f,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 1f c5 <unknown>
ldnt1sw z31.d, p7/z, [z31.d, x0]
// CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x9f,0x00,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 00 c5 <unknown>
ldnt1sw { z0.d }, p0/z, [z1.d]
// CHECK-INST: ldnt1sw { z0.d }, p0/z, [z1.d]
// CHECK-ENCODING: [0x20,0x80,0x1f,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 1f c5 <unknown>
ldnt1sw { z31.d }, p7/z, [z31.d, xzr]
// CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d]
// CHECK-ENCODING: [0xff,0x9f,0x1f,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 1f c5 <unknown>
ldnt1sw { z31.d }, p7/z, [z31.d, x0]
// CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x9f,0x00,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 9f 00 c5 <unknown>

test/MC/AArch64/SVE2/ldnt1w-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid result type.
ldnt1w { z0.b }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1w { z0.b }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1w { z0.h }, p0/z, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1w { z0.h }, p0/z, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid base vector.
ldnt1w { z0.s }, p0/z, [z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldnt1w { z0.s }, p0/z, [z0.b]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1w { z0.d }, p0/z, [z0.h]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldnt1w { z0.d }, p0/z, [z0.h]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid offset type.
ldnt1w { z0.d }, p0/z, [z0.d, z1.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1w { z0.d }, p0/z, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// restricted predicate has range [0, 7].
ldnt1w { z27.d }, p8/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ldnt1w { z27.d }, p8/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
ldnt1w { }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: ldnt1w { }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1w { z0.d, z1.d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1w { z0.d, z1.d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnt1w { v0.2d }, p0/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ldnt1w { v0.2d }, p0/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ldnt1w { z0.d }, p0/z, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1w { z0.d }, p0/z, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
ldnt1w { z0.s }, p0/z, [z0.s, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ldnt1w { z0.s }, p0/z, [z0.s, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ldnt1w.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ldnt1w z0.s, p0/z, [z1.s]
// CHECK-INST: ldnt1w { z0.s }, p0/z, [z1.s]
// CHECK-ENCODING: [0x20,0xa0,0x1f,0x85]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 1f 85 <unknown>
ldnt1w z31.s, p7/z, [z31.s, xzr]
// CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s]
// CHECK-ENCODING: [0xff,0xbf,0x1f,0x85]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 1f 85 <unknown>
ldnt1w z31.s, p7/z, [z31.s, x0]
// CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s, x0]
// CHECK-ENCODING: [0xff,0xbf,0x00,0x85]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 00 85 <unknown>
ldnt1w z0.d, p0/z, [z1.d]
// CHECK-INST: ldnt1w { z0.d }, p0/z, [z1.d]
// CHECK-ENCODING: [0x20,0xc0,0x1f,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c0 1f c5 <unknown>
ldnt1w z31.d, p7/z, [z31.d, xzr]
// CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d]
// CHECK-ENCODING: [0xff,0xdf,0x1f,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 1f c5 <unknown>
ldnt1w z31.d, p7/z, [z31.d, x0]
// CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d, x0]
// CHECK-ENCODING: [0xff,0xdf,0x00,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 00 c5 <unknown>
ldnt1w { z0.s }, p0/z, [z1.s]
// CHECK-INST: ldnt1w { z0.s }, p0/z, [z1.s]
// CHECK-ENCODING: [0x20,0xa0,0x1f,0x85]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 1f 85 <unknown>
ldnt1w { z31.s }, p7/z, [z31.s, xzr]
// CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s]
// CHECK-ENCODING: [0xff,0xbf,0x1f,0x85]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 1f 85 <unknown>
ldnt1w { z31.s }, p7/z, [z31.s, x0]
// CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s, x0]
// CHECK-ENCODING: [0xff,0xbf,0x00,0x85]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 00 85 <unknown>
ldnt1w { z0.d }, p0/z, [z1.d]
// CHECK-INST: ldnt1w { z0.d }, p0/z, [z1.d]
// CHECK-ENCODING: [0x20,0xc0,0x1f,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c0 1f c5 <unknown>
ldnt1w { z31.d }, p7/z, [z31.d, xzr]
// CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d]
// CHECK-ENCODING: [0xff,0xdf,0x1f,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 1f c5 <unknown>
ldnt1w { z31.d }, p7/z, [z31.d, x0]
// CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d, x0]
// CHECK-ENCODING: [0xff,0xdf,0x00,0xc5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 00 c5 <unknown>

test/MC/AArch64/SVE2/match-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Restricted predicate out of range.
match p0.b, p8/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: match p0.b, p8/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid predicate operation
match p0.b, p0/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: match p0.b, p0/m, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid destination predicate register
match p0.s, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
// CHECK-NEXT: match p0.s, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
match p0.d, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
// CHECK-NEXT: match p0.d, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
match p0.b, p0/z, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: match p0.b, p0/z, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
match p0.b, p0/z, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: match p0.b, p0/z, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.b, p0/z, z7.b
match p0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: match p0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
match p0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: match p0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/match.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
match p0.b, p0/z, z0.b, z0.b
// CHECK-INST: match p0.b, p0/z, z0.b, z0.b
// CHECK-ENCODING: [0x00,0x80,0x20,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 80 20 45 <unknown>
match p0.h, p0/z, z0.h, z0.h
// CHECK-INST: match p0.h, p0/z, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x80,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 80 60 45 <unknown>
match p15.b, p7/z, z30.b, z31.b
// CHECK-INST: match p15.b, p7/z, z30.b, z31.b
// CHECK-ENCODING: [0xcf,0x9f,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: cf 9f 3f 45 <unknown>
match p15.h, p7/z, z30.h, z31.h
// CHECK-INST: match p15.h, p7/z, z30.h, z31.h
// CHECK-ENCODING: [0xcf,0x9f,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: cf 9f 7f 45 <unknown>

test/MC/AArch64/SVE2/mla-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
mla z0.h, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h
// CHECK-NEXT: mla z0.h, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mla z0.s, z1.s, z8.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s
// CHECK-NEXT: mla z0.s, z1.s, z8.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mla z0.d, z1.d, z16.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
// CHECK-NEXT: mla z0.d, z1.d, z16.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element index
mla z0.h, z1.h, z2.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: mla z0.h, z1.h, z2.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mla z0.h, z1.h, z2.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: mla z0.h, z1.h, z2.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mla z0.s, z1.s, z2.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: mla z0.s, z1.s, z2.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mla z0.s, z1.s, z2.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: mla z0.s, z1.s, z2.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mla z0.d, z1.d, z2.d[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: mla z0.d, z1.d, z2.d[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mla z0.d, z1.d, z2.d[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: mla z0.d, z1.d, z2.d[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
mla z0.d, z1.d, z7.d[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: mla z0.d, z1.d, z7.d[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/mla.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
mla z0.h, z1.h, z7.h[7]
// CHECK-INST: mla z0.h, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0x08,0x7f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 08 7f 44 <unknown>
mla z0.s, z1.s, z7.s[3]
// CHECK-INST: mla z0.s, z1.s, z7.s[3]
// CHECK-ENCODING: [0x20,0x08,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 08 bf 44 <unknown>
mla z0.d, z1.d, z7.d[1]
// CHECK-INST: mla z0.d, z1.d, z7.d[1]
// CHECK-ENCODING: [0x20,0x08,0xf7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 08 f7 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
mla z0.d, z1.d, z7.d[1]
// CHECK-INST: mla z0.d, z1.d, z7.d[1]
// CHECK-ENCODING: [0x20,0x08,0xf7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 08 f7 44 <unknown>

test/MC/AArch64/SVE2/mls-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
mls z0.h, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h
// CHECK-NEXT: mls z0.h, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mls z0.s, z1.s, z8.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s
// CHECK-NEXT: mls z0.s, z1.s, z8.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mls z0.d, z1.d, z16.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
// CHECK-NEXT: mls z0.d, z1.d, z16.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element index
mls z0.h, z1.h, z2.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: mls z0.h, z1.h, z2.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mls z0.h, z1.h, z2.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: mls z0.h, z1.h, z2.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mls z0.s, z1.s, z2.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: mls z0.s, z1.s, z2.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mls z0.s, z1.s, z2.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: mls z0.s, z1.s, z2.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mls z0.d, z1.d, z2.d[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: mls z0.d, z1.d, z2.d[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mls z0.d, z1.d, z2.d[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: mls z0.d, z1.d, z2.d[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
mls z0.d, z1.d, z7.d[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: mls z0.d, z1.d, z7.d[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/mls.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
mls z0.h, z1.h, z7.h[7]
// CHECK-INST: mls z0.h, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0x0c,0x7f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 0c 7f 44 <unknown>
mls z0.s, z1.s, z7.s[3]
// CHECK-INST: mls z0.s, z1.s, z7.s[3]
// CHECK-ENCODING: [0x20,0x0c,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 0c bf 44 <unknown>
mls z0.d, z1.d, z7.d[1]
// CHECK-INST: mls z0.d, z1.d, z7.d[1]
// CHECK-ENCODING: [0x20,0x0c,0xf7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 0c f7 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
mls z0.d, z1.d, z7.d[1]
// CHECK-INST: mls z0.d, z1.d, z7.d[1]
// CHECK-ENCODING: [0x20,0x0c,0xf7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 0c f7 44 <unknown>

test/MC/AArch64/SVE2/mul-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
mul z0.h, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mul z0.h, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mul z0.s, z1.s, z8.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mul z0.s, z1.s, z8.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mul z0.d, z1.d, z16.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mul z0.d, z1.d, z16.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element index
mul z0.h, z1.h, z2.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: mul z0.h, z1.h, z2.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mul z0.h, z1.h, z2.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: mul z0.h, z1.h, z2.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mul z0.s, z1.s, z2.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: mul z0.s, z1.s, z2.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mul z0.s, z1.s, z2.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: mul z0.s, z1.s, z2.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mul z0.d, z1.d, z2.d[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: mul z0.d, z1.d, z2.d[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mul z0.d, z1.d, z2.d[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: mul z0.d, z1.d, z2.d[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
mul z0.b, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: mul z0.b, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mul z0.h, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: mul z0.h, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mul z0.s, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: mul z0.s, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mul z0.d, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: mul z0.d, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
mul z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mul z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
mul z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mul z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.d, p0/z, z6.d
mul z31.d, z31.d, z15.d[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mul z31.d, z31.d, z15.d[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
mul z31.d, z31.d, z15.d[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: mul z31.d, z31.d, z15.d[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/mul.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
mul z0.b, z1.b, z2.b
// CHECK-INST: mul z0.b, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x60,0x22,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 60 22 04 <unknown>
mul z0.h, z1.h, z2.h
// CHECK-INST: mul z0.h, z1.h, z2.h
// CHECK-ENCODING: [0x20,0x60,0x62,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 60 62 04 <unknown>
mul z29.s, z30.s, z31.s
// CHECK-INST: mul z29.s, z30.s, z31.s
// CHECK-ENCODING: [0xdd,0x63,0xbf,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 63 bf 04 <unknown>
mul z31.d, z31.d, z31.d
// CHECK-INST: mul z31.d, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x63,0xff,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 63 ff 04 <unknown>
mul z0.h, z1.h, z7.h[7]
// CHECK-INST: mul z0.h, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0xf8,0x7f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 f8 7f 44 <unknown>
mul z0.s, z1.s, z7.s[3]
// CHECK-INST: mul z0.s, z1.s, z7.s[3]
// CHECK-ENCODING: [0x20,0xf8,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 f8 bf 44 <unknown>
mul z0.d, z1.d, z15.d[1]
// CHECK-INST: mul z0.d, z1.d, z15.d[1]
// CHECK-ENCODING: [0x20,0xf8,0xff,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 f8 ff 44 <unknown>

test/MC/AArch64/SVE2/nbsl-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
nbsl z0.b, z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: nbsl z0.b, z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
nbsl z0.h, z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: nbsl z0.h, z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
nbsl z0.s, z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: nbsl z0.s, z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
nbsl z0.d, z1.d, z2.d, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: nbsl z0.d, z1.d, z2.d, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
nbsl z0.d, z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: nbsl z0.d, z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/nbsl.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
nbsl z0.d, z0.d, z1.d, z2.d
// CHECK-INST: nbsl z0.d, z0.d, z1.d, z2.d
// CHECK-ENCODING: [0x40,0x3c,0xe1,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 40 3c e1 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z7
// CHECK-INST: movprfx z31, z7
// CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bc 20 04 <unknown>
nbsl z31.d, z31.d, z30.d, z29.d
// CHECK-INST: nbsl z31.d, z31.d, z30.d, z29.d
// CHECK-ENCODING: [0xbf,0x3f,0xfe,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bf 3f fe 04 <unknown>

test/MC/AArch64/SVE2/nmatch-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Restricted predicate out of range.
nmatch p0.b, p8/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: nmatch p0.b, p8/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid predicate operation
nmatch p0.b, p0/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: nmatch p0.b, p0/m, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid destination predicate register
nmatch p0.s, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
// CHECK-NEXT: nmatch p0.s, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
nmatch p0.d, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
// CHECK-NEXT: nmatch p0.d, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
nmatch p0.b, p0/z, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: nmatch p0.b, p0/z, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
nmatch p0.b, p0/z, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: nmatch p0.b, p0/z, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.b, p0/z, z7.b
nmatch p0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: nmatch p0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
nmatch p0.b, p0/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: nmatch p0.b, p0/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/nmatch.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
nmatch p0.b, p0/z, z0.b, z0.b
// CHECK-INST: nmatch p0.b, p0/z, z0.b, z0.b
// CHECK-ENCODING: [0x10,0x80,0x20,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 10 80 20 45 <unknown>
nmatch p0.h, p0/z, z0.h, z0.h
// CHECK-INST: nmatch p0.h, p0/z, z0.h, z0.h
// CHECK-ENCODING: [0x10,0x80,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 10 80 60 45 <unknown>
nmatch p15.b, p7/z, z30.b, z31.b
// CHECK-INST: nmatch p15.b, p7/z, z30.b, z31.b
// CHECK-ENCODING: [0xdf,0x9f,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f 3f 45 <unknown>
nmatch p15.h, p7/z, z30.h, z31.h
// CHECK-INST: nmatch p15.h, p7/z, z30.h, z31.h
// CHECK-ENCODING: [0xdf,0x9f,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f 7f 45 <unknown>

test/MC/AArch64/SVE2/pmul-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
pmul z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: pmul z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
pmul z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: pmul z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
pmul z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: pmul z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.b, p0/z, z7.b
pmul z0.b, z1.b, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: pmul z0.b, z1.b, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
pmul z0.b, z1.b, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: pmul z0.b, z1.b, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/pmul.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
pmul z0.b, z1.b, z2.b
// CHECK-INST: pmul z0.b, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x64,0x22,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 64 22 04 <unknown>
pmul z29.b, z30.b, z31.b
// CHECK-INST: pmul z29.b, z30.b, z31.b
// CHECK-ENCODING: [0xdd,0x67,0x3f,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 67 3f 04 <unknown>

test/MC/AArch64/SVE2/pmullb-128-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
pmullb z0.q, z0.q, z0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: pmullb z0.q, z0.q, z0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
pmullb z0.q, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: pmullb z0.q, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
pmullb z0.q, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: pmullb z0.q, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/pmullb-128.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
// RUN: | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
pmullb z29.q, z30.d, z31.d
// CHECK-INST: pmullb z29.q, z30.d, z31.d
// CHECK-ENCODING: [0xdd,0x6b,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2-aes
// CHECK-UNKNOWN: dd 6b 1f 45 <unknown>

test/MC/AArch64/SVE2/pmullb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
pmullb z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: pmullb z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
pmullb z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: pmullb z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
pmullb z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: pmullb z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
pmullb z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: pmullb z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
pmullb z0.q, z0.q, z0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: pmullb z0.q, z0.q, z0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
pmullb z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: pmullb z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
pmullb z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: pmullb z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/pmullb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
pmullb z0.h, z1.b, z2.b
// CHECK-INST: pmullb z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x68,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 68 42 45 <unknown>
pmullb z31.d, z31.s, z31.s
// CHECK-INST: pmullb z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x6b,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 6b df 45 <unknown>

test/MC/AArch64/SVE2/pmullt-128-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
pmullt z0.q, z0.q, z0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: pmullt z0.q, z0.q, z0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
pmullt z0.q, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: pmullt z0.q, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
pmullt z0.q, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: pmullt z0.q, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/pmullt-128.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
// RUN: | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
pmullt z29.q, z30.d, z31.d
// CHECK-INST: pmullt z29.q, z30.d, z31.d
// CHECK-ENCODING: [0xdd,0x6f,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2-aes
// CHECK-UNKNOWN: dd 6f 1f 45 <unknown>

test/MC/AArch64/SVE2/pmullt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
pmullt z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: pmullt z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
pmullt z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: pmullt z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
pmullt z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: pmullt z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
pmullt z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: pmullt z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
pmullt z0.q, z0.q, z0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: pmullt z0.q, z0.q, z0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
pmullt z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: pmullt z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
pmullt z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: pmullt z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/pmullt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
pmullt z0.h, z1.b, z2.b
// CHECK-INST: pmullt z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x6c,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 6c 42 45 <unknown>
pmullt z31.d, z31.s, z31.s
// CHECK-INST: pmullt z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x6f,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 6f df 45 <unknown>

test/MC/AArch64/SVE2/raddhnb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
raddhnb z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: raddhnb z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
raddhnb z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: raddhnb z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
raddhnb z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: raddhnb z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
raddhnb z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: raddhnb z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
raddhnb z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: raddhnb z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
raddhnb z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: raddhnb z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/raddhnb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
raddhnb z0.b, z1.h, z31.h
// CHECK-INST: raddhnb z0.b, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x68,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 68 7f 45 <unknown>
raddhnb z0.h, z1.s, z31.s
// CHECK-INST: raddhnb z0.h, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x68,0xbf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 68 bf 45 <unknown>
raddhnb z0.s, z1.d, z31.d
// CHECK-INST: raddhnb z0.s, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x68,0xff,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 68 ff 45 <unknown>

test/MC/AArch64/SVE2/raddhnt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
raddhnt z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: raddhnt z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
raddhnt z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: raddhnt z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
raddhnt z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: raddhnt z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
raddhnt z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: raddhnt z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
raddhnt z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: raddhnt z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
raddhnt z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: raddhnt z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/raddhnt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
raddhnt z0.b, z1.h, z31.h
// CHECK-INST: raddhnt z0.b, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x6c,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 6c 7f 45 <unknown>
raddhnt z0.h, z1.s, z31.s
// CHECK-INST: raddhnt z0.h, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x6c,0xbf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 6c bf 45 <unknown>
raddhnt z0.s, z1.d, z31.d
// CHECK-INST: raddhnt z0.s, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x6c,0xff,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 6c ff 45 <unknown>

test/MC/AArch64/SVE2/rax1-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-sha3 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid element width
rax1 z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rax1 z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rax1 z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rax1 z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rax1 z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rax1 z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
rax1 z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: rax1 z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
rax1 z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: rax1 z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/rax1.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-sha3 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sha3 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2-sha3 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sha3 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
rax1 z0.d, z1.d, z31.d
// CHECK-INST: rax1 z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xf4,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2-sha3
// CHECK-UNKNOWN: 20 f4 3f 45 <unknown>

test/MC/AArch64/SVE2/rshrnb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
rshrnb z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: rshrnb z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnb z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: rshrnb z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnb z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: rshrnb z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnb z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: rshrnb z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnb z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: rshrnb z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnb z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: rshrnb z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
rshrnb z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rshrnb z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnb z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rshrnb z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnb z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rshrnb z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnb z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rshrnb z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
rshrnb z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: rshrnb z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/rshrnb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
rshrnb z0.b, z0.h, #1
// CHECK-INST: rshrnb z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x18,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 18 2f 45 <unknown>
rshrnb z31.b, z31.h, #8
// CHECK-INST: rshrnb z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x1b,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 1b 28 45 <unknown>
rshrnb z0.h, z0.s, #1
// CHECK-INST: rshrnb z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x18,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 18 3f 45 <unknown>
rshrnb z31.h, z31.s, #16
// CHECK-INST: rshrnb z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x1b,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 1b 30 45 <unknown>
rshrnb z0.s, z0.d, #1
// CHECK-INST: rshrnb z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x18,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 18 7f 45 <unknown>
rshrnb z31.s, z31.d, #32
// CHECK-INST: rshrnb z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x1b,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 1b 60 45 <unknown>

test/MC/AArch64/SVE2/rshrnt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
rshrnt z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: rshrnt z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnt z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: rshrnt z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnt z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: rshrnt z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnt z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: rshrnt z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnt z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: rshrnt z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnt z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: rshrnt z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
rshrnt z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rshrnt z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnt z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rshrnt z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnt z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rshrnt z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rshrnt z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rshrnt z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
rshrnt z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: rshrnt z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/rshrnt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
rshrnt z0.b, z0.h, #1
// CHECK-INST: rshrnt z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x1c,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 1c 2f 45 <unknown>
rshrnt z31.b, z31.h, #8
// CHECK-INST: rshrnt z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x1f,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 1f 28 45 <unknown>
rshrnt z0.h, z0.s, #1
// CHECK-INST: rshrnt z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x1c,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 1c 3f 45 <unknown>
rshrnt z31.h, z31.s, #16
// CHECK-INST: rshrnt z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x1f,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 1f 30 45 <unknown>
rshrnt z0.s, z0.d, #1
// CHECK-INST: rshrnt z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x1c,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 1c 7f 45 <unknown>
rshrnt z31.s, z31.d, #32
// CHECK-INST: rshrnt z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x1f,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 1f 60 45 <unknown>

test/MC/AArch64/SVE2/rsubhnb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
rsubhnb z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rsubhnb z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rsubhnb z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rsubhnb z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rsubhnb z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rsubhnb z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rsubhnb z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rsubhnb z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
rsubhnb z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: rsubhnb z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
rsubhnb z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: rsubhnb z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/rsubhnb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
rsubhnb z0.b, z1.h, z31.h
// CHECK-INST: rsubhnb z0.b, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x78,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 78 7f 45 <unknown>
rsubhnb z0.h, z1.s, z31.s
// CHECK-INST: rsubhnb z0.h, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x78,0xbf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 78 bf 45 <unknown>
rsubhnb z0.s, z1.d, z31.d
// CHECK-INST: rsubhnb z0.s, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x78,0xff,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 78 ff 45 <unknown>

test/MC/AArch64/SVE2/rsubhnt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
rsubhnt z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rsubhnt z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rsubhnt z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rsubhnt z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rsubhnt z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rsubhnt z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
rsubhnt z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rsubhnt z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
rsubhnt z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: rsubhnt z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
rsubhnt z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: rsubhnt z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/rsubhnt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
rsubhnt z0.b, z1.h, z31.h
// CHECK-INST: rsubhnt z0.b, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x7c,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 7c 7f 45 <unknown>
rsubhnt z0.h, z1.s, z31.s
// CHECK-INST: rsubhnt z0.h, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x7c,0xbf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 7c bf 45 <unknown>
rsubhnt z0.s, z1.d, z31.d
// CHECK-INST: rsubhnt z0.s, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x7c,0xff,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 7c ff 45 <unknown>

test/MC/AArch64/SVE2/saba-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
saba z0.b, z1.h, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saba z0.b, z1.h, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
saba z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: saba z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/saba.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
saba z0.b, z1.b, z31.b
// CHECK-INST: saba z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xf8,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 f8 1f 45 <unknown>
saba z0.h, z1.h, z31.h
// CHECK-INST: saba z0.h, z1.h, z31.h
// CHECK-ENCODING: [0x20,0xf8,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 f8 5f 45 <unknown>
saba z0.s, z1.s, z31.s
// CHECK-INST: saba z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xf8,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 f8 9f 45 <unknown>
saba z0.d, z1.d, z31.d
// CHECK-INST: saba z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xf8,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 f8 df 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
saba z0.d, z1.d, z31.d
// CHECK-INST: saba z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xf8,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 f8 df 45 <unknown>

test/MC/AArch64/SVE2/sabalb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
sabalb z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabalb z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sabalb z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabalb z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sabalb z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabalb z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sabalb z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabalb z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sabalb z0.d, z1.s, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sabalb z0.d, z1.s, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sabalb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sabalb z0.h, z1.b, z31.b
// CHECK-INST: sabalb z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xc0,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c0 5f 45 <unknown>
sabalb z0.s, z1.h, z31.h
// CHECK-INST: sabalb z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0xc0,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c0 9f 45 <unknown>
sabalb z0.d, z1.s, z31.s
// CHECK-INST: sabalb z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xc0,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c0 df 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
sabalb z21.d, z1.s, z31.s
// CHECK-INST: sabalb z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0xc0,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 c0 df 45 <unknown>

test/MC/AArch64/SVE2/sabalt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
sabalt z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabalt z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sabalt z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabalt z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sabalt z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabalt z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sabalt z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabalt z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sabalt z0.d, z1.s, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sabalt z0.d, z1.s, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sabalt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sabalt z0.h, z1.b, z31.b
// CHECK-INST: sabalt z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xc4,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c4 5f 45 <unknown>
sabalt z0.s, z1.h, z31.h
// CHECK-INST: sabalt z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0xc4,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c4 9f 45 <unknown>
sabalt z0.d, z1.s, z31.s
// CHECK-INST: sabalt z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xc4,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c4 df 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
sabalt z21.d, z1.s, z31.s
// CHECK-INST: sabalt z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0xc4,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 c4 df 45 <unknown>

test/MC/AArch64/SVE2/sabdlb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
sabdlb z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabdlb z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sabdlb z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabdlb z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sabdlb z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabdlb z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sabdlb z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabdlb z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
sabdlb z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sabdlb z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
sabdlb z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sabdlb z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sabdlb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sabdlb z0.h, z1.b, z2.b
// CHECK-INST: sabdlb z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x30,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 30 42 45 <unknown>
sabdlb z29.s, z30.h, z31.h
// CHECK-INST: sabdlb z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x33,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 33 9f 45 <unknown>
sabdlb z31.d, z31.s, z31.s
// CHECK-INST: sabdlb z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x33,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 33 df 45 <unknown>

test/MC/AArch64/SVE2/sabdlt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
sabdlt z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabdlt z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sabdlt z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabdlt z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sabdlt z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabdlt z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sabdlt z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sabdlt z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
sabdlt z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sabdlt z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
sabdlt z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sabdlt z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sabdlt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sabdlt z0.h, z1.b, z2.b
// CHECK-INST: sabdlt z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x34,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 34 42 45 <unknown>
sabdlt z29.s, z30.h, z31.h
// CHECK-INST: sabdlt z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x37,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 37 9f 45 <unknown>
sabdlt z31.d, z31.s, z31.s
// CHECK-INST: sabdlt z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x37,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 37 df 45 <unknown>

test/MC/AArch64/SVE2/sadalp-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Element sizes must match
sadalp z0.b, p0/m, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sadalp z0.b, p0/m, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sadalp z0.h, p0/m, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sadalp z0.h, p0/m, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sadalp z0.s, p0/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sadalp z0.s, p0/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sadalp z0.d, p0/m, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sadalp z0.d, p0/m, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
sadalp z0.h, p8/m, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sadalp z0.h, p8/m, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative movprfx tests
movprfx z31.s, p0/z, z6.s // element type of the source operand, rather than destination.
sadalp z31.d, p0/m, z30.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size
// CHECK-NEXT: sadalp z31.d, p0/m, z30.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sadalp.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sadalp z0.h, p0/m, z1.b
// CHECK-INST: sadalp z0.h, p0/m, z1.b
// CHECK-ENCODING: [0x20,0xa0,0x44,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 44 44 <unknown>
sadalp z29.s, p0/m, z30.h
// CHECK-INST: sadalp z29.s, p0/m, z30.h
// CHECK-ENCODING: [0xdd,0xa3,0x84,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd a3 84 44 <unknown>
sadalp z30.d, p7/m, z31.s
// CHECK-INST: sadalp z30.d, p7/m, z31.s
// CHECK-ENCODING: [0xfe,0xbf,0xc4,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fe bf c4 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
sadalp z31.d, p0/m, z30.s
// CHECK-INST: sadalp z31.d, p0/m, z30.s
// CHECK-ENCODING: [0xdf,0xa3,0xc4,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df a3 c4 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sadalp z31.d, p0/m, z30.s
// CHECK-INST: sadalp z31.d, p0/m, z30.s
// CHECK-ENCODING: [0xdf,0xa3,0xc4,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df a3 c4 44 <unknown>

test/MC/AArch64/SVE2/saddlb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
saddlb z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddlb z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
saddlb z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddlb z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
saddlb z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddlb z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
saddlb z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddlb z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
saddlb z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: saddlb z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
saddlb z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: saddlb z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/saddlb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
saddlb z0.h, z1.b, z2.b
// CHECK-INST: saddlb z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x00,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 00 42 45 <unknown>
saddlb z29.s, z30.h, z31.h
// CHECK-INST: saddlb z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x03,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 03 9f 45 <unknown>
saddlb z31.d, z31.s, z31.s
// CHECK-INST: saddlb z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x03,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 03 df 45 <unknown>

test/MC/AArch64/SVE2/saddlbt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
saddlbt z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddlbt z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
saddlbt z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddlbt z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
saddlbt z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddlbt z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
saddlbt z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddlbt z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
saddlbt z0.h, z1.b, z7.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: saddlbt z0.h, z1.b, z7.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.h, p0/z, z7.h
saddlbt z0.h, z1.b, z7.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: saddlbt z0.h, z1.b, z7.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/saddlbt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
saddlbt z0.h, z1.b, z31.b
// CHECK-INST: saddlbt z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x80,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 5f 45 <unknown>
saddlbt z0.s, z1.h, z31.h
// CHECK-INST: saddlbt z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x80,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 9f 45 <unknown>
saddlbt z0.d, z1.s, z31.s
// CHECK-INST: saddlbt z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x80,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 df 45 <unknown>

test/MC/AArch64/SVE2/saddlt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
saddlt z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddlt z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
saddlt z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddlt z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
saddlt z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddlt z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
saddlt z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddlt z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
saddlt z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: saddlt z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
saddlt z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: saddlt z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/saddlt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
saddlt z0.h, z1.b, z2.b
// CHECK-INST: saddlt z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x04,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 04 42 45 <unknown>
saddlt z29.s, z30.h, z31.h
// CHECK-INST: saddlt z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x07,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 07 9f 45 <unknown>
saddlt z31.d, z31.s, z31.s
// CHECK-INST: saddlt z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x07,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 07 df 45 <unknown>

test/MC/AArch64/SVE2/saddwb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
saddwb z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddwb z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
saddwb z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddwb z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
saddwb z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddwb z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
saddwb z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddwb z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
saddwb z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: saddwb z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
saddwb z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: saddwb z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/saddwb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
saddwb z0.h, z1.h, z2.b
// CHECK-INST: saddwb z0.h, z1.h, z2.b
// CHECK-ENCODING: [0x20,0x40,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 40 42 45 <unknown>
saddwb z29.s, z30.s, z31.h
// CHECK-INST: saddwb z29.s, z30.s, z31.h
// CHECK-ENCODING: [0xdd,0x43,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 43 9f 45 <unknown>
saddwb z31.d, z31.d, z31.s
// CHECK-INST: saddwb z31.d, z31.d, z31.s
// CHECK-ENCODING: [0xff,0x43,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 43 df 45 <unknown>

test/MC/AArch64/SVE2/saddwt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
saddwt z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddwt z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
saddwt z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddwt z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
saddwt z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddwt z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
saddwt z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: saddwt z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
saddwt z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: saddwt z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
saddwt z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: saddwt z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/saddwt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
saddwt z0.h, z1.h, z2.b
// CHECK-INST: saddwt z0.h, z1.h, z2.b
// CHECK-ENCODING: [0x20,0x44,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 44 42 45 <unknown>
saddwt z29.s, z30.s, z31.h
// CHECK-INST: saddwt z29.s, z30.s, z31.h
// CHECK-ENCODING: [0xdd,0x47,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 47 9f 45 <unknown>
saddwt z31.d, z31.d, z31.s
// CHECK-INST: saddwt z31.d, z31.d, z31.s
// CHECK-ENCODING: [0xff,0x47,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 47 df 45 <unknown>

test/MC/AArch64/SVE2/sbclb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
sbclb z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sbclb z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sbclb z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sbclb z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sbclb z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sbclb z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sbclb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sbclb z0.s, z1.s, z31.s
// CHECK-INST: sbclb z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xd0,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 d0 9f 45 <unknown>
sbclb z0.d, z1.d, z31.d
// CHECK-INST: sbclb z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xd0,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 d0 df 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sbclb z0.d, z1.d, z31.d
// CHECK-INST: sbclb z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xd0,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 d0 df 45 <unknown>

test/MC/AArch64/SVE2/sbclt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
sbclt z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sbclt z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sbclt z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sbclt z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sbclt z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sbclt z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sbclt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sbclt z0.s, z1.s, z31.s
// CHECK-INST: sbclt z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xd4,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 d4 9f 45 <unknown>
sbclt z0.d, z1.d, z31.d
// CHECK-INST: sbclt z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xd4,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 d4 df 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sbclt z0.d, z1.d, z31.d
// CHECK-INST: sbclt z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xd4,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 d4 df 45 <unknown>

test/MC/AArch64/SVE2/shadd-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
shadd z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: shadd z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
shadd z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: shadd z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shadd z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: shadd z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
shadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: shadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/shadd.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
shadd z0.b, p0/m, z0.b, z1.b
// CHECK-INST: shadd z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x10,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 10 44 <unknown>
shadd z0.h, p0/m, z0.h, z1.h
// CHECK-INST: shadd z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x50,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 50 44 <unknown>
shadd z29.s, p7/m, z29.s, z30.s
// CHECK-INST: shadd z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x90,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 90 44 <unknown>
shadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: shadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd0,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d0 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
shadd z31.d, p0/m, z31.d, z30.d
// CHECK-INST: shadd z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xd0,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 d0 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
shadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: shadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd0,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d0 44 <unknown>

test/MC/AArch64/SVE2/shrnb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
shrnb z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: shrnb z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnb z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: shrnb z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnb z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: shrnb z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnb z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: shrnb z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnb z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: shrnb z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnb z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: shrnb z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
shrnb z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: shrnb z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnb z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: shrnb z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnb z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: shrnb z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnb z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: shrnb z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
shrnb z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: shrnb z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/shrnb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
shrnb z0.b, z0.h, #1
// CHECK-INST: shrnb z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x10,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 10 2f 45 <unknown>
shrnb z31.b, z31.h, #8
// CHECK-INST: shrnb z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x13,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 13 28 45 <unknown>
shrnb z0.h, z0.s, #1
// CHECK-INST: shrnb z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x10,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 10 3f 45 <unknown>
shrnb z31.h, z31.s, #16
// CHECK-INST: shrnb z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x13,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 13 30 45 <unknown>
shrnb z0.s, z0.d, #1
// CHECK-INST: shrnb z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x10,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 10 7f 45 <unknown>
shrnb z31.s, z31.d, #32
// CHECK-INST: shrnb z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x13,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 13 60 45 <unknown>

test/MC/AArch64/SVE2/shrnt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
shrnt z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: shrnt z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnt z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: shrnt z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnt z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: shrnt z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnt z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: shrnt z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnt z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: shrnt z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnt z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: shrnt z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
shrnt z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: shrnt z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnt z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: shrnt z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnt z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: shrnt z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shrnt z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: shrnt z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
shrnt z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: shrnt z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/shrnt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
shrnt z0.b, z0.h, #1
// CHECK-INST: shrnt z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x14,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 14 2f 45 <unknown>
shrnt z31.b, z31.h, #8
// CHECK-INST: shrnt z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x17,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 17 28 45 <unknown>
shrnt z0.h, z0.s, #1
// CHECK-INST: shrnt z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x14,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 14 3f 45 <unknown>
shrnt z31.h, z31.s, #16
// CHECK-INST: shrnt z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x17,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 17 30 45 <unknown>
shrnt z0.s, z0.d, #1
// CHECK-INST: shrnt z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x14,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 14 7f 45 <unknown>
shrnt z31.s, z31.d, #32
// CHECK-INST: shrnt z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x17,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 17 60 45 <unknown>

test/MC/AArch64/SVE2/shsub-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
shsub z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: shsub z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
shsub z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: shsub z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shsub z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: shsub z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
shsub z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: shsub z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/shsub.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
shsub z0.b, p0/m, z0.b, z1.b
// CHECK-INST: shsub z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x12,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 12 44 <unknown>
shsub z0.h, p0/m, z0.h, z1.h
// CHECK-INST: shsub z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x52,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 52 44 <unknown>
shsub z29.s, p7/m, z29.s, z30.s
// CHECK-INST: shsub z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x92,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 92 44 <unknown>
shsub z31.d, p7/m, z31.d, z30.d
// CHECK-INST: shsub z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd2,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d2 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
shsub z31.d, p0/m, z31.d, z30.d
// CHECK-INST: shsub z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xd2,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 d2 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
shsub z31.d, p7/m, z31.d, z30.d
// CHECK-INST: shsub z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd2,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d2 44 <unknown>

test/MC/AArch64/SVE2/shsubr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
shsubr z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: shsubr z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
shsubr z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: shsubr z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shsubr z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: shsubr z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
shsubr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: shsubr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/shsubr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
shsubr z0.b, p0/m, z0.b, z1.b
// CHECK-INST: shsubr z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x16,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 16 44 <unknown>
shsubr z0.h, p0/m, z0.h, z1.h
// CHECK-INST: shsubr z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x56,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 56 44 <unknown>
shsubr z29.s, p7/m, z29.s, z30.s
// CHECK-INST: shsubr z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x96,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 96 44 <unknown>
shsubr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: shsubr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd6,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d6 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
shsubr z31.d, p0/m, z31.d, z30.d
// CHECK-INST: shsubr z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xd6,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 d6 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
shsubr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: shsubr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd6,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d6 44 <unknown>

test/MC/AArch64/SVE2/sli-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
sli z18.b, z28.b, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: sli z18.b, z28.b, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sli z1.b, z9.b, #8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: sli z1.b, z9.b, #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sli z21.h, z2.h, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: sli z21.h, z2.h, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sli z14.h, z30.h, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: sli z14.h, z30.h, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sli z6.s, z12.s, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: sli z6.s, z12.s, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sli z23.s, z19.s, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: sli z23.s, z19.s, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sli z3.d, z24.d, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
// CHECK-NEXT: sli z3.d, z24.d, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sli z25.d, z16.d, #64
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
// CHECK-NEXT: sli z25.d, z16.d, #64
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
sli z0.b, z0.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sli z0.b, z0.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
sli z31.d, z31.d, #63
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sli z31.d, z31.d, #63
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sli.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sli z0.b, z0.b, #0
// CHECK-INST: sli z0.b, z0.b, #0
// CHECK-ENCODING: [0x00,0xf4,0x08,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 f4 08 45 <unknown>
sli z31.b, z31.b, #7
// CHECK-INST: sli z31.b, z31.b, #7
// CHECK-ENCODING: [0xff,0xf7,0x0f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff f7 0f 45 <unknown>
sli z0.h, z0.h, #0
// CHECK-INST: sli z0.h, z0.h, #0
// CHECK-ENCODING: [0x00,0xf4,0x10,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 f4 10 45 <unknown>
sli z31.h, z31.h, #15
// CHECK-INST: sli z31.h, z31.h, #15
// CHECK-ENCODING: [0xff,0xf7,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff f7 1f 45 <unknown>
sli z0.s, z0.s, #0
// CHECK-INST: sli z0.s, z0.s, #0
// CHECK-ENCODING: [0x00,0xf4,0x40,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 f4 40 45 <unknown>
sli z31.s, z31.s, #31
// CHECK-INST: sli z31.s, z31.s, #31
// CHECK-ENCODING: [0xff,0xf7,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff f7 5f 45 <unknown>
sli z0.d, z0.d, #0
// CHECK-INST: sli z0.d, z0.d, #0
// CHECK-ENCODING: [0x00,0xf4,0x80,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 f4 80 45 <unknown>
sli z31.d, z31.d, #63
// CHECK-INST: sli z31.d, z31.d, #63
// CHECK-ENCODING: [0xff,0xf7,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff f7 df 45 <unknown>

test/MC/AArch64/SVE2/sm4e-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-sm4 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
sm4e z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sm4e z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
sm4e z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sm4e z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sm4e z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sm4e z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sm4e z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sm4e z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/z, z7.s
sm4e z0.s, z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sm4e z0.s, z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
sm4e z0.s, z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sm4e z0.s, z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sm4e.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-sm4 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sm4 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2-sm4 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sm4 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sm4e z0.s, z0.s, z31.s
// CHECK-INST: sm4e z0.s, z0.s, z31.s
// CHECK-ENCODING: [0xe0,0xe3,0x23,0x45]
// CHECK-ERROR: instruction requires: sve2-sm4
// CHECK-UNKNOWN: e0 e3 23 45 <unknown>

test/MC/AArch64/SVE2/sm4ekey-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-sm4 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid element width
sm4ekey z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sm4ekey z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sm4ekey z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sm4ekey z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sm4ekey z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sm4ekey z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/z, z7.s
sm4ekey z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sm4ekey z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
sm4ekey z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sm4ekey z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sm4ekey.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-sm4 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sm4 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2-sm4 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sm4 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sm4ekey z0.s, z1.s, z31.s
// CHECK-INST: sm4ekey z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xf0,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2-sm4
// CHECK-UNKNOWN: 20 f0 3f 45 <unknown>

test/MC/AArch64/SVE2/smaxp-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
smaxp z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: smaxp z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
smaxp z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smaxp z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smaxp z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smaxp z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
smaxp z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: smaxp z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/smaxp.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
smaxp z0.b, p0/m, z0.b, z1.b
// CHECK-INST: smaxp z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0xa0,0x14,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 14 44 <unknown>
smaxp z0.h, p0/m, z0.h, z1.h
// CHECK-INST: smaxp z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0xa0,0x54,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 54 44 <unknown>
smaxp z29.s, p7/m, z29.s, z30.s
// CHECK-INST: smaxp z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0xbf,0x94,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd bf 94 44 <unknown>
smaxp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: smaxp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0xbf,0xd4,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df bf d4 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
smaxp z31.d, p0/m, z31.d, z30.d
// CHECK-INST: smaxp z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0xa3,0xd4,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df a3 d4 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
smaxp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: smaxp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0xbf,0xd4,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df bf d4 44 <unknown>

test/MC/AArch64/SVE2/sminp-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
sminp z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sminp z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
sminp z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sminp z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sminp z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sminp z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
sminp z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sminp z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sminp.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sminp z0.b, p0/m, z0.b, z1.b
// CHECK-INST: sminp z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0xa0,0x16,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 16 44 <unknown>
sminp z0.h, p0/m, z0.h, z1.h
// CHECK-INST: sminp z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0xa0,0x56,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 56 44 <unknown>
sminp z29.s, p7/m, z29.s, z30.s
// CHECK-INST: sminp z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0xbf,0x96,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd bf 96 44 <unknown>
sminp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sminp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0xbf,0xd6,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df bf d6 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
sminp z31.d, p0/m, z31.d, z30.d
// CHECK-INST: sminp z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0xa3,0xd6,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df a3 d6 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sminp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sminp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0xbf,0xd6,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df bf d6 44 <unknown>

test/MC/AArch64/SVE2/smlalb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
smlalb z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smlalb z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalb z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smlalb z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
smlalb z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: smlalb z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalb z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: smlalb z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalb z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: smlalb z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalb z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: smlalb z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
smlalb z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlalb z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalb z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlalb z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalb z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlalb z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalb z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlalb z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalb z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlalb z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalb z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlalb z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
smlalb z0.d, z1.s, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: smlalb z0.d, z1.s, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
smlalb z0.d, z1.s, z15.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: smlalb z0.d, z1.s, z15.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/smlalb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
smlalb z0.h, z1.b, z31.b
// CHECK-INST: smlalb z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x40,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 40 5f 44 <unknown>
smlalb z0.s, z1.h, z31.h
// CHECK-INST: smlalb z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x40,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 40 9f 44 <unknown>
smlalb z0.d, z1.s, z31.s
// CHECK-INST: smlalb z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x40,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 40 df 44 <unknown>
smlalb z0.s, z1.h, z7.h[7]
// CHECK-INST: smlalb z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0x88,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 88 bf 44 <unknown>
smlalb z0.d, z1.s, z15.s[1]
// CHECK-INST: smlalb z0.d, z1.s, z15.s[1]
// CHECK-ENCODING: [0x20,0x88,0xef,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 88 ef 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
smlalb z21.d, z1.s, z31.s
// CHECK-INST: smlalb z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0x40,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 40 df 44 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
smlalb z21.d, z10.s, z5.s[1]
// CHECK-INST: smlalb z21.d, z10.s, z5.s[1]
// CHECK-ENCODING: [0x55,0x89,0xe5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 55 89 e5 44 <unknown>

test/MC/AArch64/SVE2/smlalt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
smlalt z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smlalt z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalt z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smlalt z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
smlalt z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: smlalt z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalt z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: smlalt z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalt z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: smlalt z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalt z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: smlalt z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
smlalt z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlalt z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalt z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlalt z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalt z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlalt z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalt z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlalt z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalt z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlalt z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlalt z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlalt z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
smlalt z0.d, z1.s, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: smlalt z0.d, z1.s, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
smlalt z0.d, z1.s, z15.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: smlalt z0.d, z1.s, z15.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/smlalt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
smlalt z0.h, z1.b, z31.b
// CHECK-INST: smlalt z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x44,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 44 5f 44 <unknown>
smlalt z0.s, z1.h, z31.h
// CHECK-INST: smlalt z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x44,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 44 9f 44 <unknown>
smlalt z0.d, z1.s, z31.s
// CHECK-INST: smlalt z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x44,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 44 df 44 <unknown>
smlalt z0.s, z1.h, z7.h[7]
// CHECK-INST: smlalt z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0x8c,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 8c bf 44 <unknown>
smlalt z0.d, z1.s, z15.s[1]
// CHECK-INST: smlalt z0.d, z1.s, z15.s[1]
// CHECK-ENCODING: [0x20,0x8c,0xef,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 8c ef 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
smlalt z21.d, z1.s, z31.s
// CHECK-INST: smlalt z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0x44,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 44 df 44 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
smlalt z21.d, z10.s, z5.s[1]
// CHECK-INST: smlalt z21.d, z10.s, z5.s[1]
// CHECK-ENCODING: [0x55,0x8d,0xe5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 55 8d e5 44 <unknown>

test/MC/AArch64/SVE2/smlslb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
smlslb z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smlslb z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslb z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smlslb z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
smlslb z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: smlslb z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslb z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: smlslb z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslb z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: smlslb z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslb z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: smlslb z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
smlslb z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlslb z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslb z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlslb z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslb z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlslb z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslb z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlslb z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslb z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlslb z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslb z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlslb z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
smlslb z0.d, z1.s, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: smlslb z0.d, z1.s, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
smlslb z0.d, z1.s, z15.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: smlslb z0.d, z1.s, z15.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/smlslb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
smlslb z0.h, z1.b, z31.b
// CHECK-INST: smlslb z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x50,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 50 5f 44 <unknown>
smlslb z0.s, z1.h, z31.h
// CHECK-INST: smlslb z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x50,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 50 9f 44 <unknown>
smlslb z0.d, z1.s, z31.s
// CHECK-INST: smlslb z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x50,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 50 df 44 <unknown>
smlslb z0.s, z1.h, z7.h[7]
// CHECK-INST: smlslb z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0xa8,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a8 bf 44 <unknown>
smlslb z0.d, z1.s, z15.s[1]
// CHECK-INST: smlslb z0.d, z1.s, z15.s[1]
// CHECK-ENCODING: [0x20,0xa8,0xef,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a8 ef 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
smlslb z21.d, z1.s, z31.s
// CHECK-INST: smlslb z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0x50,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 50 df 44 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
smlslb z21.d, z10.s, z5.s[1]
// CHECK-INST: smlslb z21.d, z10.s, z5.s[1]
// CHECK-ENCODING: [0x55,0xa9,0xe5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 55 a9 e5 44 <unknown>

test/MC/AArch64/SVE2/smlslt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
smlslt z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smlslt z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslt z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smlslt z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
smlslt z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: smlslt z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslt z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: smlslt z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslt z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: smlslt z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslt z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: smlslt z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
smlslt z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlslt z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslt z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlslt z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslt z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlslt z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslt z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlslt z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslt z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlslt z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smlslt z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smlslt z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
smlslt z0.d, z1.s, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: smlslt z0.d, z1.s, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
smlslt z0.d, z1.s, z15.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: smlslt z0.d, z1.s, z15.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/smlslt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
smlslt z0.h, z1.b, z31.b
// CHECK-INST: smlslt z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x54,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 54 5f 44 <unknown>
smlslt z0.s, z1.h, z31.h
// CHECK-INST: smlslt z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x54,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 54 9f 44 <unknown>
smlslt z0.d, z1.s, z31.s
// CHECK-INST: smlslt z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x54,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 54 df 44 <unknown>
smlslt z0.s, z1.h, z7.h[7]
// CHECK-INST: smlslt z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0xac,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 ac bf 44 <unknown>
smlslt z0.d, z1.s, z15.s[1]
// CHECK-INST: smlslt z0.d, z1.s, z15.s[1]
// CHECK-ENCODING: [0x20,0xac,0xef,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 ac ef 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
smlslt z21.d, z1.s, z31.s
// CHECK-INST: smlslt z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0x54,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 54 df 44 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
smlslt z21.d, z10.s, z5.s[1]
// CHECK-INST: smlslt z21.d, z10.s, z5.s[1]
// CHECK-ENCODING: [0x55,0xad,0xe5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 55 ad e5 44 <unknown>

test/MC/AArch64/SVE2/smulh-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
smulh z0.b, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smulh z0.b, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smulh z0.h, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smulh z0.h, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smulh z0.s, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smulh z0.s, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smulh z0.d, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smulh z0.d, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
smulh z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: smulh z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
smulh z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: smulh z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/smulh.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
smulh z0.b, z1.b, z2.b
// CHECK-INST: smulh z0.b, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x68,0x22,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 68 22 04 <unknown>
smulh z0.h, z1.h, z2.h
// CHECK-INST: smulh z0.h, z1.h, z2.h
// CHECK-ENCODING: [0x20,0x68,0x62,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 68 62 04 <unknown>
smulh z29.s, z30.s, z31.s
// CHECK-INST: smulh z29.s, z30.s, z31.s
// CHECK-ENCODING: [0xdd,0x6b,0xbf,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 6b bf 04 <unknown>
smulh z31.d, z31.d, z31.d
// CHECK-INST: smulh z31.d, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x6b,0xff,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 6b ff 04 <unknown>

test/MC/AArch64/SVE2/smullb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
smullb z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smullb z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullb z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smullb z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
smullb z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: smullb z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullb z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: smullb z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullb z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: smullb z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullb z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: smullb z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
smullb z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullb z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullb z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullb z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullb z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullb z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullb z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullb z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullb z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullb z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullb z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullb z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullb z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullb z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullb z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullb z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullb z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullb z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullb z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullb z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
smullb z31.d, z31.s, z15.s[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: smullb z31.d, z31.s, z15.s[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
smullb z31.d, z31.s, z15.s[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: smullb z31.d, z31.s, z15.s[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/smullb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
smullb z0.h, z1.b, z2.b
// CHECK-INST: smullb z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x70,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 70 42 45 <unknown>
smullb z29.s, z30.h, z31.h
// CHECK-INST: smullb z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x73,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 73 9f 45 <unknown>
smullb z31.d, z31.s, z31.s
// CHECK-INST: smullb z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x73,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 73 df 45 <unknown>
smullb z0.s, z1.h, z7.h[7]
// CHECK-INST: smullb z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0xc8,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c8 bf 44 <unknown>
smullb z0.d, z1.s, z15.s[1]
// CHECK-INST: smullb z0.d, z1.s, z15.s[1]
// CHECK-ENCODING: [0x20,0xc8,0xef,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c8 ef 44 <unknown>

test/MC/AArch64/SVE2/smullt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
smullt z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smullt z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullt z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smullt z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
smullt z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: smullt z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullt z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: smullt z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullt z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: smullt z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullt z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: smullt z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
smullt z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullt z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullt z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullt z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullt z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullt z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullt z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullt z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullt z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullt z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullt z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullt z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullt z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullt z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullt z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullt z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullt z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullt z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smullt z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smullt z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
smullt z31.d, z31.s, z15.s[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: smullt z31.d, z31.s, z15.s[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
smullt z31.d, z31.s, z15.s[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: smullt z31.d, z31.s, z15.s[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/smullt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
smullt z0.h, z1.b, z2.b
// CHECK-INST: smullt z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x74,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 74 42 45 <unknown>
smullt z29.s, z30.h, z31.h
// CHECK-INST: smullt z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x77,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 77 9f 45 <unknown>
smullt z31.d, z31.s, z31.s
// CHECK-INST: smullt z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x77,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 77 df 45 <unknown>
smullt z0.s, z1.h, z7.h[7]
// CHECK-INST: smullt z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0xcc,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 cc bf 44 <unknown>
smullt z0.d, z1.s, z15.s[1]
// CHECK-INST: smullt z0.d, z1.s, z15.s[1]
// CHECK-ENCODING: [0x20,0xcc,0xef,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 cc ef 44 <unknown>

test/MC/AArch64/SVE2/splice-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element widths.
splice z0.b, p0, { z1.h, z2.h }
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: splice z0.b, p0, { z1.h, z2.h }
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
splice z0.b, p0, { }
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: splice z0.b, p0, { }
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
splice z0.b, p0, { z1.b }
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: splice z0.b, p0, { z1.b }
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
splice z0.b, p0, { z1.b, z2.b, z3.b }
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: splice z0.b, p0, { z1.b, z2.b, z3.b }
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
splice z0.b, p0, { z1.b, z2.h }
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
// CHECK-NEXT: splice z0.b, p0, { z1.b, z2.h }
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
splice z0.b, p0, { z1.b, z31.b }
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: splice z0.b, p0, { z1.b, z31.b }
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
splice z0.b, p0, { v0.4b, v1.4b }
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: splice z0.b, p0, { v0.4b, v1.4b }
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
splice z0.b, p8, { z1.b, z2.b }
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]
// CHECK-NEXT: splice z0.b, p8, { z1.b, z2.b }
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
splice z31.b, p0, { z30.b, z31.b }
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: splice z31.b, p0, { z30.b, z31.b }
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.b, p0/z, z6.b
splice z31.b, p0, { z30.b, z31.b }
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: splice z31.b, p0, { z30.b, z31.b }
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/splice.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
splice z29.b, p7, { z30.b, z31.b }
// CHECK-INST: splice z29.b, p7, { z30.b, z31.b }
// CHECK-ENCODING: [0xdd,0x9f,0x2d,0x05]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 2d 05 <unknown>
splice z29.h, p7, { z30.h, z31.h }
// CHECK-INST: splice z29.h, p7, { z30.h, z31.h }
// CHECK-ENCODING: [0xdd,0x9f,0x6d,0x05]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 6d 05 <unknown>
splice z29.s, p7, { z30.s, z31.s }
// CHECK-INST: splice z29.s, p7, { z30.s, z31.s }
// CHECK-ENCODING: [0xdd,0x9f,0xad,0x05]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f ad 05 <unknown>
splice z29.d, p7, { z30.d, z31.d }
// CHECK-INST: splice z29.d, p7, { z30.d, z31.d }
// CHECK-ENCODING: [0xdd,0x9f,0xed,0x05]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f ed 05 <unknown>

test/MC/AArch64/SVE2/sqabs-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid predicate
sqabs z0.s, p8/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sqabs z0.s, p8/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
sqabs z0.b, p7/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqabs z0.b, p7/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqabs.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqabs z31.b, p7/m, z31.b
// CHECK-INST: sqabs z31.b, p7/m, z31.b
// CHECK-ENCODING: [0xff,0xbf,0x08,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 08 44 <unknown>
sqabs z31.h, p7/m, z31.h
// CHECK-INST: sqabs z31.h, p7/m, z31.h
// CHECK-ENCODING: [0xff,0xbf,0x48,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 48 44 <unknown>
sqabs z31.s, p7/m, z31.s
// CHECK-INST: sqabs z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x88,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 88 44 <unknown>
sqabs z31.d, p7/m, z31.d
// CHECK-INST: sqabs z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xc8,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf c8 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.s, p7/z, z6.s
// CHECK-INST: movprfx z4.s, p7/z, z6.s
// CHECK-ENCODING: [0xc4,0x3c,0x90,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c 90 04 <unknown>
sqabs z4.s, p7/m, z31.s
// CHECK-INST: sqabs z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x88,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 88 44 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
sqabs z4.s, p7/m, z31.s
// CHECK-INST: sqabs z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x88,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 88 44 <unknown>

test/MC/AArch64/SVE2/sqadd-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
sqadd z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sqadd z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
sqadd z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqadd z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqadd z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqadd z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
sqadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sqadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqadd.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqadd z0.b, p0/m, z0.b, z1.b
// CHECK-INST: sqadd z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x18,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 18 44 <unknown>
sqadd z0.h, p0/m, z0.h, z1.h
// CHECK-INST: sqadd z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x58,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 58 44 <unknown>
sqadd z29.s, p7/m, z29.s, z30.s
// CHECK-INST: sqadd z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x98,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 98 44 <unknown>
sqadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd8,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d8 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
sqadd z31.d, p0/m, z31.d, z30.d
// CHECK-INST: sqadd z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xd8,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 d8 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sqadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd8,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d8 44 <unknown>

test/MC/AArch64/SVE2/sqcadd-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
sqcadd z0.d, z1.d, z2.d, #90
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sqcadd z0.d, z1.d, z2.d, #90
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid rotation
sqcadd z0.d, z0.d, z1.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
// CHECK-NEXT: sqcadd z0.d, z0.d, z1.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqcadd z0.d, z0.d, z1.d, #180
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
// CHECK-NEXT: sqcadd z0.d, z0.d, z1.d, #180
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqcadd z0.d, z0.d, z1.d, #450
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
// CHECK-NEXT: sqcadd z0.d, z0.d, z1.d, #450
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sqcadd z0.d, z0.d, z31.d, #90
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqcadd z0.d, z0.d, z31.d, #90
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqcadd.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqcadd z0.b, z0.b, z0.b, #90
// CHECK-INST: sqcadd z0.b, z0.b, z0.b, #90
// CHECK-ENCODING: [0x00,0xd8,0x01,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 d8 01 45 <unknown>
sqcadd z0.h, z0.h, z0.h, #90
// CHECK-INST: sqcadd z0.h, z0.h, z0.h, #90
// CHECK-ENCODING: [0x00,0xd8,0x41,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 d8 41 45 <unknown>
sqcadd z0.s, z0.s, z0.s, #90
// CHECK-INST: sqcadd z0.s, z0.s, z0.s, #90
// CHECK-ENCODING: [0x00,0xd8,0x81,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 d8 81 45 <unknown>
sqcadd z0.d, z0.d, z0.d, #90
// CHECK-INST: sqcadd z0.d, z0.d, z0.d, #90
// CHECK-ENCODING: [0x00,0xd8,0xc1,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 d8 c1 45 <unknown>
sqcadd z31.b, z31.b, z31.b, #270
// CHECK-INST: sqcadd z31.b, z31.b, z31.b, #270
// CHECK-ENCODING: [0xff,0xdf,0x01,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 01 45 <unknown>
sqcadd z31.h, z31.h, z31.h, #270
// CHECK-INST: sqcadd z31.h, z31.h, z31.h, #270
// CHECK-ENCODING: [0xff,0xdf,0x41,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 41 45 <unknown>
sqcadd z31.s, z31.s, z31.s, #270
// CHECK-INST: sqcadd z31.s, z31.s, z31.s, #270
// CHECK-ENCODING: [0xff,0xdf,0x81,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df 81 45 <unknown>
sqcadd z31.d, z31.d, z31.d, #270
// CHECK-INST: sqcadd z31.d, z31.d, z31.d, #270
// CHECK-ENCODING: [0xff,0xdf,0xc1,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff df c1 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
sqcadd z4.d, z4.d, z31.d, #270
// CHECK-INST: sqcadd z4.d, z4.d, z31.d, #270
// CHECK-ENCODING: [0xe4,0xdf,0xc1,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 df c1 45 <unknown>

test/MC/AArch64/SVE2/sqdmlalb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
sqdmlalb z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmlalb z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalb z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmlalb z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
sqdmlalb z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqdmlalb z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalb z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqdmlalb z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalb z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqdmlalb z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalb z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqdmlalb z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
sqdmlalb z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalb z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalb z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalb z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalb z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalb z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalb z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalb z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalb z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalb z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalb z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalb z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sqdmlalb z0.d, z1.s, z15.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdmlalb z0.d, z1.s, z15.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
sqdmlalb z0.d, z1.s, z15.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdmlalb z0.d, z1.s, z15.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqdmlalb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqdmlalb z0.h, z1.b, z31.b
// CHECK-INST: sqdmlalb z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x60,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 60 5f 44 <unknown>
sqdmlalb z0.s, z1.h, z31.h
// CHECK-INST: sqdmlalb z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x60,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 60 9f 44 <unknown>
sqdmlalb z0.d, z1.s, z31.s
// CHECK-INST: sqdmlalb z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x60,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 60 df 44 <unknown>
sqdmlalb z0.s, z1.h, z7.h[7]
// CHECK-INST: sqdmlalb z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0x28,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 28 bf 44 <unknown>
sqdmlalb z0.d, z1.s, z15.s[3]
// CHECK-INST: sqdmlalb z0.d, z1.s, z15.s[3]
// CHECK-ENCODING: [0x20,0x28,0xff,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 28 ff 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
sqdmlalb z21.d, z1.s, z31.s
// CHECK-INST: sqdmlalb z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0x60,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 60 df 44 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
sqdmlalb z21.d, z10.s, z5.s[1]
// CHECK-INST: sqdmlalb z21.d, z10.s, z5.s[1]
// CHECK-ENCODING: [0x55,0x29,0xe5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 55 29 e5 44 <unknown>

test/MC/AArch64/SVE2/sqdmlalbt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
sqdmlalbt z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalbt z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalbt z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalbt z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalbt z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalbt z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalbt z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalbt z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sqdmlalbt z0.d, z1.s, z15.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdmlalbt z0.d, z1.s, z15.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqdmlalbt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqdmlalbt z0.h, z1.b, z31.b
// CHECK-INST: sqdmlalbt z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x08,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 08 5f 44 <unknown>
sqdmlalbt z0.s, z1.h, z31.h
// CHECK-INST: sqdmlalbt z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x08,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 08 9f 44 <unknown>
sqdmlalbt z0.d, z1.s, z31.s
// CHECK-INST: sqdmlalbt z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x08,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 08 df 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
sqdmlalbt z21.d, z1.s, z31.s
// CHECK-INST: sqdmlalbt z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0x08,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 08 df 44 <unknown>

test/MC/AArch64/SVE2/sqdmlalt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
sqdmlalt z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmlalt z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalt z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmlalt z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
sqdmlalt z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqdmlalt z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalt z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqdmlalt z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalt z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqdmlalt z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalt z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqdmlalt z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
sqdmlalt z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalt z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalt z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalt z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalt z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalt z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalt z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalt z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalt z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalt z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlalt z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlalt z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sqdmlalt z0.d, z1.s, z15.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdmlalt z0.d, z1.s, z15.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
sqdmlalt z0.d, z1.s, z15.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdmlalt z0.d, z1.s, z15.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqdmlalt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqdmlalt z0.h, z1.b, z31.b
// CHECK-INST: sqdmlalt z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x64,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 64 5f 44 <unknown>
sqdmlalt z0.s, z1.h, z31.h
// CHECK-INST: sqdmlalt z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x64,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 64 9f 44 <unknown>
sqdmlalt z0.d, z1.s, z31.s
// CHECK-INST: sqdmlalt z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x64,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 64 df 44 <unknown>
sqdmlalt z0.s, z1.h, z7.h[7]
// CHECK-INST: sqdmlalt z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0x2c,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 2c bf 44 <unknown>
sqdmlalt z0.d, z1.s, z15.s[3]
// CHECK-INST: sqdmlalt z0.d, z1.s, z15.s[3]
// CHECK-ENCODING: [0x20,0x2c,0xff,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 2c ff 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
sqdmlalt z21.d, z1.s, z31.s
// CHECK-INST: sqdmlalt z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0x64,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 64 df 44 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
sqdmlalt z21.d, z10.s, z5.s[1]
// CHECK-INST: sqdmlalt z21.d, z10.s, z5.s[1]
// CHECK-ENCODING: [0x55,0x2d,0xe5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 55 2d e5 44 <unknown>

test/MC/AArch64/SVE2/sqdmlslb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
sqdmlslb z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmlslb z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslb z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmlslb z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
sqdmlslb z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqdmlslb z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslb z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqdmlslb z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslb z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqdmlslb z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslb z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqdmlslb z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
sqdmlslb z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslb z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslb z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslb z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslb z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslb z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslb z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslb z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslb z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslb z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslb z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslb z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sqdmlslb z0.d, z1.s, z15.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdmlslb z0.d, z1.s, z15.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
sqdmlslb z0.d, z1.s, z15.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdmlslb z0.d, z1.s, z15.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqdmlslb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqdmlslb z0.h, z1.b, z31.b
// CHECK-INST: sqdmlslb z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x68,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 68 5f 44 <unknown>
sqdmlslb z0.s, z1.h, z31.h
// CHECK-INST: sqdmlslb z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x68,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 68 9f 44 <unknown>
sqdmlslb z0.d, z1.s, z31.s
// CHECK-INST: sqdmlslb z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x68,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 68 df 44 <unknown>
sqdmlslb z0.s, z1.h, z7.h[7]
// CHECK-INST: sqdmlslb z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0x38,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 38 bf 44 <unknown>
sqdmlslb z0.d, z1.s, z15.s[3]
// CHECK-INST: sqdmlslb z0.d, z1.s, z15.s[3]
// CHECK-ENCODING: [0x20,0x38,0xff,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 38 ff 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
sqdmlslb z21.d, z1.s, z31.s
// CHECK-INST: sqdmlslb z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0x68,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 68 df 44 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
sqdmlslb z21.d, z10.s, z5.s[1]
// CHECK-INST: sqdmlslb z21.d, z10.s, z5.s[1]
// CHECK-ENCODING: [0x55,0x39,0xe5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 55 39 e5 44 <unknown>

test/MC/AArch64/SVE2/sqdmlslbt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
sqdmlslbt z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslbt z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslbt z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslbt z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslbt z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslbt z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslbt z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslbt z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sqdmlslbt z0.d, z1.s, z15.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdmlslbt z0.d, z1.s, z15.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqdmlslbt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqdmlslbt z0.h, z1.b, z31.b
// CHECK-INST: sqdmlslbt z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x0c,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 0c 5f 44 <unknown>
sqdmlslbt z0.s, z1.h, z31.h
// CHECK-INST: sqdmlslbt z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x0c,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 0c 9f 44 <unknown>
sqdmlslbt z0.d, z1.s, z31.s
// CHECK-INST: sqdmlslbt z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x0c,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 0c df 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
sqdmlslbt z21.d, z1.s, z31.s
// CHECK-INST: sqdmlslbt z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0x0c,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 0c df 44 <unknown>

test/MC/AArch64/SVE2/sqdmlslt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
sqdmlslt z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmlslt z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslt z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmlslt z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
sqdmlslt z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqdmlslt z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslt z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqdmlslt z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslt z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqdmlslt z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslt z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqdmlslt z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
sqdmlslt z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslt z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslt z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslt z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslt z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslt z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslt z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslt z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslt z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslt z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmlslt z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmlslt z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sqdmlslt z0.d, z1.s, z15.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdmlslt z0.d, z1.s, z15.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
sqdmlslt z0.d, z1.s, z15.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqdmlslt z0.d, z1.s, z15.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqdmlslt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqdmlslt z0.h, z1.b, z31.b
// CHECK-INST: sqdmlslt z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x6c,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 6c 5f 44 <unknown>
sqdmlslt z0.s, z1.h, z31.h
// CHECK-INST: sqdmlslt z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x6c,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 6c 9f 44 <unknown>
sqdmlslt z0.d, z1.s, z31.s
// CHECK-INST: sqdmlslt z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x6c,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 6c df 44 <unknown>
sqdmlslt z0.s, z1.h, z7.h[7]
// CHECK-INST: sqdmlslt z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0x3c,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 3c bf 44 <unknown>
sqdmlslt z0.d, z1.s, z15.s[3]
// CHECK-INST: sqdmlslt z0.d, z1.s, z15.s[3]
// CHECK-ENCODING: [0x20,0x3c,0xff,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 3c ff 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
sqdmlslt z21.d, z1.s, z31.s
// CHECK-INST: sqdmlslt z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0x6c,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 6c df 44 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
sqdmlslt z21.d, z10.s, z5.s[1]
// CHECK-INST: sqdmlslt z21.d, z10.s, z5.s[1]
// CHECK-ENCODING: [0x55,0x3d,0xe5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 55 3d e5 44 <unknown>

test/MC/AArch64/SVE2/sqdmulh-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
sqdmulh z0.h, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmulh z0.h, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh z0.s, z1.s, z8.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmulh z0.s, z1.s, z8.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh z0.d, z1.d, z16.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmulh z0.d, z1.d, z16.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element index
sqdmulh z0.h, z1.h, z2.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqdmulh z0.h, z1.h, z2.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh z0.h, z1.h, z2.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqdmulh z0.h, z1.h, z2.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh z0.s, z1.s, z2.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqdmulh z0.s, z1.s, z2.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh z0.s, z1.s, z2.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqdmulh z0.s, z1.s, z2.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh z0.d, z1.d, z2.d[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: sqdmulh z0.d, z1.d, z2.d[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh z0.d, z1.d, z2.d[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: sqdmulh z0.d, z1.d, z2.d[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
sqdmulh z0.b, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmulh z0.b, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh z0.h, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmulh z0.h, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmulh z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmulh z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmulh z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
sqdmulh z31.d, z31.d, z15.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqdmulh z31.d, z31.d, z15.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
sqdmulh z31.d, z31.d, z15.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqdmulh z31.d, z31.d, z15.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.d, p0/z, z6.d
sqdmulh z31.d, z31.d, z15.d[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqdmulh z31.d, z31.d, z15.d[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
sqdmulh z31.d, z31.d, z15.d[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqdmulh z31.d, z31.d, z15.d[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqdmulh.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqdmulh z0.b, z1.b, z2.b
// CHECK-INST: sqdmulh z0.b, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x70,0x22,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 70 22 04 <unknown>
sqdmulh z0.h, z1.h, z2.h
// CHECK-INST: sqdmulh z0.h, z1.h, z2.h
// CHECK-ENCODING: [0x20,0x70,0x62,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 70 62 04 <unknown>
sqdmulh z29.s, z30.s, z31.s
// CHECK-INST: sqdmulh z29.s, z30.s, z31.s
// CHECK-ENCODING: [0xdd,0x73,0xbf,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 73 bf 04 <unknown>
sqdmulh z31.d, z31.d, z31.d
// CHECK-INST: sqdmulh z31.d, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x73,0xff,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 73 ff 04 <unknown>
sqdmulh z0.h, z1.h, z7.h[7]
// CHECK-INST: sqdmulh z0.h, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0xf0,0x7f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 f0 7f 44 <unknown>
sqdmulh z0.s, z1.s, z7.s[3]
// CHECK-INST: sqdmulh z0.s, z1.s, z7.s[3]
// CHECK-ENCODING: [0x20,0xf0,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 f0 bf 44 <unknown>
sqdmulh z0.d, z1.d, z15.d[1]
// CHECK-INST: sqdmulh z0.d, z1.d, z15.d[1]
// CHECK-ENCODING: [0x20,0xf0,0xff,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 f0 ff 44 <unknown>

test/MC/AArch64/SVE2/sqdmullb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
sqdmullb z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmullb z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullb z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmullb z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
sqdmullb z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqdmullb z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullb z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqdmullb z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullb z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqdmullb z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullb z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqdmullb z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
sqdmullb z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullb z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullb z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullb z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullb z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullb z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullb z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullb z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullb z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullb z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullb z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullb z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullb z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullb z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullb z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullb z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullb z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullb z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullb z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullb z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
sqdmullb z31.d, z31.s, z15.s[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqdmullb z31.d, z31.s, z15.s[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
sqdmullb z31.d, z31.s, z15.s[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqdmullb z31.d, z31.s, z15.s[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqdmullb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqdmullb z0.h, z1.b, z2.b
// CHECK-INST: sqdmullb z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x60,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 60 42 45 <unknown>
sqdmullb z29.s, z30.h, z31.h
// CHECK-INST: sqdmullb z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x63,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 63 9f 45 <unknown>
sqdmullb z31.d, z31.s, z31.s
// CHECK-INST: sqdmullb z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x63,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 63 df 45 <unknown>
sqdmullb z0.s, z1.h, z7.h[7]
// CHECK-INST: sqdmullb z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0xe8,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 e8 bf 44 <unknown>
sqdmullb z0.d, z1.s, z15.s[1]
// CHECK-INST: sqdmullb z0.d, z1.s, z15.s[1]
// CHECK-ENCODING: [0x20,0xe8,0xef,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 e8 ef 44 <unknown>

test/MC/AArch64/SVE2/sqdmullt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
sqdmullt z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmullt z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullt z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqdmullt z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
sqdmullt z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqdmullt z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullt z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqdmullt z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullt z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqdmullt z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullt z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqdmullt z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
sqdmullt z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullt z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullt z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullt z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullt z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullt z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullt z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullt z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullt z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullt z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullt z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullt z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullt z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullt z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullt z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullt z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullt z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullt z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqdmullt z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqdmullt z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
sqdmullt z31.d, z31.s, z15.s[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqdmullt z31.d, z31.s, z15.s[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
sqdmullt z31.d, z31.s, z15.s[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqdmullt z31.d, z31.s, z15.s[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqdmullt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqdmullt z0.h, z1.b, z2.b
// CHECK-INST: sqdmullt z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x64,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 64 42 45 <unknown>
sqdmullt z29.s, z30.h, z31.h
// CHECK-INST: sqdmullt z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x67,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 67 9f 45 <unknown>
sqdmullt z31.d, z31.s, z31.s
// CHECK-INST: sqdmullt z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x67,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 67 df 45 <unknown>
sqdmullt z0.s, z1.h, z7.h[7]
// CHECK-INST: sqdmullt z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0xec,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 ec bf 44 <unknown>
sqdmullt z0.d, z1.s, z15.s[1]
// CHECK-INST: sqdmullt z0.d, z1.s, z15.s[1]
// CHECK-ENCODING: [0x20,0xec,0xef,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 ec ef 44 <unknown>

test/MC/AArch64/SVE2/sqneg-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid predicate
sqneg z0.s, p8/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sqneg z0.s, p8/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
sqneg z0.b, p7/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqneg z0.b, p7/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqneg.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqneg z31.b, p7/m, z31.b
// CHECK-INST: sqneg z31.b, p7/m, z31.b
// CHECK-ENCODING: [0xff,0xbf,0x09,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 09 44 <unknown>
sqneg z31.h, p7/m, z31.h
// CHECK-INST: sqneg z31.h, p7/m, z31.h
// CHECK-ENCODING: [0xff,0xbf,0x49,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 49 44 <unknown>
sqneg z31.s, p7/m, z31.s
// CHECK-INST: sqneg z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x89,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 89 44 <unknown>
sqneg z31.d, p7/m, z31.d
// CHECK-INST: sqneg z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xc9,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf c9 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.s, p7/z, z6.s
// CHECK-INST: movprfx z4.s, p7/z, z6.s
// CHECK-ENCODING: [0xc4,0x3c,0x90,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c 90 04 <unknown>
sqneg z4.s, p7/m, z31.s
// CHECK-INST: sqneg z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x89,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 89 44 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
sqneg z4.s, p7/m, z31.s
// CHECK-INST: sqneg z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x89,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 89 44 <unknown>

test/MC/AArch64/SVE2/sqrdcmlah-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element size
sqrdcmlah z0.h, z1.b, z2.b[0], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrdcmlah z0.h, z1.b, z2.b[0], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdcmlah z0.h, z1.s, z2.s[0], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrdcmlah z0.h, z1.s, z2.s[0], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdcmlah z0.h, z1.d, z2.d[0], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrdcmlah z0.h, z1.d, z2.d[0], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdcmlah z0.s, z1.b, z2.b[0], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrdcmlah z0.s, z1.b, z2.b[0], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdcmlah z0.s, z1.h, z2.h[0], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrdcmlah z0.s, z1.h, z2.h[0], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdcmlah z0.s, z1.d, z2.d[0], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrdcmlah z0.s, z1.d, z2.d[0], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid restricted register for indexed vector.
sqrdcmlah z0.h, z1.h, z8.h[3], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrdcmlah z0.h, z1.h, z8.h[3], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdcmlah z0.s, z1.s, z16.s[1], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrdcmlah z0.s, z1.s, z16.s[1], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element index
sqrdcmlah z0.h, z1.h, z7.h[-1], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqrdcmlah z0.h, z1.h, z7.h[-1], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdcmlah z0.h, z1.h, z7.h[4], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqrdcmlah z0.h, z1.h, z7.h[4], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdcmlah z0.s, z1.s, z15.s[-1], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: sqrdcmlah z0.s, z1.s, z15.s[-1], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdcmlah z0.s, z1.s, z15.s[2], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: sqrdcmlah z0.s, z1.s, z15.s[2], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid rotation
sqrdcmlah z0.h, z1.h, z2.h[0], #360
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270.
// CHECK-NEXT: sqrdcmlah z0.h, z1.h, z2.h[0], #360
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdcmlah z0.s, z1.s, z2.s[0], #450
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270.
// CHECK-NEXT: sqrdcmlah z0.s, z1.s, z2.s[0], #450
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.b, p0/z, z7.b
sqrdcmlah z0.b, z1.b, z31.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqrdcmlah z0.b, z1.b, z31.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
sqrdcmlah z0.s, z1.s, z15.s[1], #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqrdcmlah z0.s, z1.s, z15.s[1], #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqrdcmlah.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqrdcmlah z0.b, z1.b, z2.b, #0
// CHECK-INST: sqrdcmlah z0.b, z1.b, z2.b, #0
// CHECK-ENCODING: [0x20,0x30,0x02,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 30 02 44 <unknown>
sqrdcmlah z0.h, z1.h, z2.h, #0
// CHECK-INST: sqrdcmlah z0.h, z1.h, z2.h, #0
// CHECK-ENCODING: [0x20,0x30,0x42,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 30 42 44 <unknown>
sqrdcmlah z0.s, z1.s, z2.s, #0
// CHECK-INST: sqrdcmlah z0.s, z1.s, z2.s, #0
// CHECK-ENCODING: [0x20,0x30,0x82,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 30 82 44 <unknown>
sqrdcmlah z0.d, z1.d, z2.d, #0
// CHECK-INST: sqrdcmlah z0.d, z1.d, z2.d, #0
// CHECK-ENCODING: [0x20,0x30,0xc2,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 30 c2 44 <unknown>
sqrdcmlah z29.b, z30.b, z31.b, #90
// CHECK-INST: sqrdcmlah z29.b, z30.b, z31.b, #90
// CHECK-ENCODING: [0xdd,0x37,0x1f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 37 1f 44 <unknown>
sqrdcmlah z29.h, z30.h, z31.h, #90
// CHECK-INST: sqrdcmlah z29.h, z30.h, z31.h, #90
// CHECK-ENCODING: [0xdd,0x37,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 37 5f 44 <unknown>
sqrdcmlah z29.s, z30.s, z31.s, #90
// CHECK-INST: sqrdcmlah z29.s, z30.s, z31.s, #90
// CHECK-ENCODING: [0xdd,0x37,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 37 9f 44 <unknown>
sqrdcmlah z29.d, z30.d, z31.d, #90
// CHECK-INST: sqrdcmlah z29.d, z30.d, z31.d, #90
// CHECK-ENCODING: [0xdd,0x37,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 37 df 44 <unknown>
sqrdcmlah z31.b, z31.b, z31.b, #180
// CHECK-INST: sqrdcmlah z31.b, z31.b, z31.b, #180
// CHECK-ENCODING: [0xff,0x3b,0x1f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3b 1f 44 <unknown>
sqrdcmlah z31.h, z31.h, z31.h, #180
// CHECK-INST: sqrdcmlah z31.h, z31.h, z31.h, #180
// CHECK-ENCODING: [0xff,0x3b,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3b 5f 44 <unknown>
sqrdcmlah z31.s, z31.s, z31.s, #180
// CHECK-INST: sqrdcmlah z31.s, z31.s, z31.s, #180
// CHECK-ENCODING: [0xff,0x3b,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3b 9f 44 <unknown>
sqrdcmlah z31.d, z31.d, z31.d, #180
// CHECK-INST: sqrdcmlah z31.d, z31.d, z31.d, #180
// CHECK-ENCODING: [0xff,0x3b,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3b df 44 <unknown>
sqrdcmlah z15.b, z16.b, z17.b, #270
// CHECK-INST: sqrdcmlah z15.b, z16.b, z17.b, #270
// CHECK-ENCODING: [0x0f,0x3e,0x11,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 3e 11 44 <unknown>
sqrdcmlah z15.h, z16.h, z17.h, #270
// CHECK-INST: sqrdcmlah z15.h, z16.h, z17.h, #270
// CHECK-ENCODING: [0x0f,0x3e,0x51,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 3e 51 44 <unknown>
sqrdcmlah z15.s, z16.s, z17.s, #270
// CHECK-INST: sqrdcmlah z15.s, z16.s, z17.s, #270
// CHECK-ENCODING: [0x0f,0x3e,0x91,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 3e 91 44 <unknown>
sqrdcmlah z15.d, z16.d, z17.d, #270
// CHECK-INST: sqrdcmlah z15.d, z16.d, z17.d, #270
// CHECK-ENCODING: [0x0f,0x3e,0xd1,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 3e d1 44 <unknown>
sqrdcmlah z0.h, z1.h, z2.h[0], #0
// CHECK-INST: sqrdcmlah z0.h, z1.h, z2.h[0], #0
// CHECK-ENCODING: [0x20,0x70,0xa2,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 70 a2 44 <unknown>
sqrdcmlah z0.s, z1.s, z2.s[0], #0
// CHECK-INST: sqrdcmlah z0.s, z1.s, z2.s[0], #0
// CHECK-ENCODING: [0x20,0x70,0xe2,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 70 e2 44 <unknown>
sqrdcmlah z31.h, z30.h, z7.h[0], #180
// CHECK-INST: sqrdcmlah z31.h, z30.h, z7.h[0], #180
// CHECK-ENCODING: [0xdf,0x7b,0xa7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 7b a7 44 <unknown>
sqrdcmlah z31.s, z30.s, z7.s[0], #180
// CHECK-INST: sqrdcmlah z31.s, z30.s, z7.s[0], #180
// CHECK-ENCODING: [0xdf,0x7b,0xe7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 7b e7 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
sqrdcmlah z4.d, z31.d, z31.d, #270
// CHECK-INST: sqrdcmlah z4.d, z31.d, z31.d, #270
// CHECK-ENCODING: [0xe4,0x3f,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 3f df 44 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
sqrdcmlah z21.s, z10.s, z5.s[1], #90
// CHECK-INST: sqrdcmlah z21.s, z10.s, z5.s[1], #90
// CHECK-ENCODING: [0x55,0x75,0xf5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 55 75 f5 44 <unknown>

test/MC/AArch64/SVE2/sqrdmlah-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
sqrdmlah z0.h, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrdmlah z0.h, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmlah z0.s, z1.s, z8.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrdmlah z0.s, z1.s, z8.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmlah z0.d, z1.d, z16.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrdmlah z0.d, z1.d, z16.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element index
sqrdmlah z0.h, z1.h, z2.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqrdmlah z0.h, z1.h, z2.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmlah z0.h, z1.h, z2.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqrdmlah z0.h, z1.h, z2.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmlah z0.s, z1.s, z2.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqrdmlah z0.s, z1.s, z2.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmlah z0.s, z1.s, z2.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqrdmlah z0.s, z1.s, z2.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmlah z0.d, z1.d, z2.d[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: sqrdmlah z0.d, z1.d, z2.d[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmlah z0.d, z1.d, z2.d[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: sqrdmlah z0.d, z1.d, z2.d[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sqrdmlah z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqrdmlah z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
sqrdmlah z0.d, z1.d, z7.d[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqrdmlah z0.d, z1.d, z7.d[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqrdmlah.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqrdmlah z0.b, z1.b, z31.b
// CHECK-INST: sqrdmlah z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x70,0x1f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 70 1f 44 <unknown>
sqrdmlah z0.h, z1.h, z31.h
// CHECK-INST: sqrdmlah z0.h, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x70,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 70 5f 44 <unknown>
sqrdmlah z0.s, z1.s, z31.s
// CHECK-INST: sqrdmlah z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x70,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 70 9f 44 <unknown>
sqrdmlah z0.d, z1.d, z31.d
// CHECK-INST: sqrdmlah z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x70,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 70 df 44 <unknown>
sqrdmlah z0.h, z1.h, z7.h[7]
// CHECK-INST: sqrdmlah z0.h, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0x10,0x7f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 10 7f 44 <unknown>
sqrdmlah z0.s, z1.s, z7.s[3]
// CHECK-INST: sqrdmlah z0.s, z1.s, z7.s[3]
// CHECK-ENCODING: [0x20,0x10,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 10 bf 44 <unknown>
sqrdmlah z0.d, z1.d, z15.d[1]
// CHECK-INST: sqrdmlah z0.d, z1.d, z15.d[1]
// CHECK-ENCODING: [0x20,0x10,0xff,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 10 ff 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqrdmlah z0.d, z1.d, z31.d
// CHECK-INST: sqrdmlah z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x70,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 70 df 44 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqrdmlah z0.d, z1.d, z15.d[1]
// CHECK-INST: sqrdmlah z0.d, z1.d, z15.d[1]
// CHECK-ENCODING: [0x20,0x10,0xff,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 10 ff 44 <unknown>

test/MC/AArch64/SVE2/sqrdmlsh-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
sqrdmlsh z0.h, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrdmlsh z0.h, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmlsh z0.s, z1.s, z8.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrdmlsh z0.s, z1.s, z8.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmlsh z0.d, z1.d, z16.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrdmlsh z0.d, z1.d, z16.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element index
sqrdmlsh z0.h, z1.h, z2.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqrdmlsh z0.h, z1.h, z2.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmlsh z0.h, z1.h, z2.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqrdmlsh z0.h, z1.h, z2.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmlsh z0.s, z1.s, z2.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqrdmlsh z0.s, z1.s, z2.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmlsh z0.s, z1.s, z2.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqrdmlsh z0.s, z1.s, z2.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmlsh z0.d, z1.d, z2.d[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: sqrdmlsh z0.d, z1.d, z2.d[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmlsh z0.d, z1.d, z2.d[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: sqrdmlsh z0.d, z1.d, z2.d[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
sqrdmlsh z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqrdmlsh z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
sqrdmlsh z0.d, z1.d, z7.d[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: sqrdmlsh z0.d, z1.d, z7.d[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqrdmlsh.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqrdmlsh z0.b, z1.b, z31.b
// CHECK-INST: sqrdmlsh z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x74,0x1f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 74 1f 44 <unknown>
sqrdmlsh z0.h, z1.h, z31.h
// CHECK-INST: sqrdmlsh z0.h, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x74,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 74 5f 44 <unknown>
sqrdmlsh z0.s, z1.s, z31.s
// CHECK-INST: sqrdmlsh z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x74,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 74 9f 44 <unknown>
sqrdmlsh z0.d, z1.d, z31.d
// CHECK-INST: sqrdmlsh z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x74,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 74 df 44 <unknown>
sqrdmlsh z0.h, z1.h, z7.h[7]
// CHECK-INST: sqrdmlsh z0.h, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0x14,0x7f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 14 7f 44 <unknown>
sqrdmlsh z0.s, z1.s, z7.s[3]
// CHECK-INST: sqrdmlsh z0.s, z1.s, z7.s[3]
// CHECK-ENCODING: [0x20,0x14,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 14 bf 44 <unknown>
sqrdmlsh z0.d, z1.d, z15.d[1]
// CHECK-INST: sqrdmlsh z0.d, z1.d, z15.d[1]
// CHECK-ENCODING: [0x20,0x14,0xff,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 14 ff 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqrdmlsh z0.d, z1.d, z31.d
// CHECK-INST: sqrdmlsh z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x74,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 74 df 44 <unknown>
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqrdmlsh z0.d, z1.d, z15.d[1]
// CHECK-INST: sqrdmlsh z0.d, z1.d, z15.d[1]
// CHECK-ENCODING: [0x20,0x14,0xff,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 14 ff 44 <unknown>

test/MC/AArch64/SVE2/sqrdmulh-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
sqrdmulh z0.h, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrdmulh z0.h, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmulh z0.s, z1.s, z8.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrdmulh z0.s, z1.s, z8.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmulh z0.d, z1.d, z16.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrdmulh z0.d, z1.d, z16.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element index
sqrdmulh z0.h, z1.h, z2.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqrdmulh z0.h, z1.h, z2.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmulh z0.h, z1.h, z2.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: sqrdmulh z0.h, z1.h, z2.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmulh z0.s, z1.s, z2.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqrdmulh z0.s, z1.s, z2.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmulh z0.s, z1.s, z2.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: sqrdmulh z0.s, z1.s, z2.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmulh z0.d, z1.d, z2.d[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: sqrdmulh z0.d, z1.d, z2.d[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmulh z0.d, z1.d, z2.d[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: sqrdmulh z0.d, z1.d, z2.d[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
sqrdmulh z0.b, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrdmulh z0.b, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmulh z0.h, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrdmulh z0.h, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmulh z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrdmulh z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrdmulh z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrdmulh z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
sqrdmulh z31.d, z31.d, z15.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqrdmulh z31.d, z31.d, z15.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
sqrdmulh z31.d, z31.d, z15.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqrdmulh z31.d, z31.d, z15.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.d, p0/z, z6.d
sqrdmulh z31.d, z31.d, z15.d[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqrdmulh z31.d, z31.d, z15.d[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
sqrdmulh z31.d, z31.d, z15.d[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqrdmulh z31.d, z31.d, z15.d[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqrdmulh.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqrdmulh z0.b, z1.b, z2.b
// CHECK-INST: sqrdmulh z0.b, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x74,0x22,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 74 22 04 <unknown>
sqrdmulh z0.h, z1.h, z2.h
// CHECK-INST: sqrdmulh z0.h, z1.h, z2.h
// CHECK-ENCODING: [0x20,0x74,0x62,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 74 62 04 <unknown>
sqrdmulh z29.s, z30.s, z31.s
// CHECK-INST: sqrdmulh z29.s, z30.s, z31.s
// CHECK-ENCODING: [0xdd,0x77,0xbf,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 77 bf 04 <unknown>
sqrdmulh z31.d, z31.d, z31.d
// CHECK-INST: sqrdmulh z31.d, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x77,0xff,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 77 ff 04 <unknown>
sqrdmulh z0.h, z1.h, z7.h[7]
// CHECK-INST: sqrdmulh z0.h, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0xf4,0x7f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 f4 7f 44 <unknown>
sqrdmulh z0.s, z1.s, z7.s[3]
// CHECK-INST: sqrdmulh z0.s, z1.s, z7.s[3]
// CHECK-ENCODING: [0x20,0xf4,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 f4 bf 44 <unknown>
sqrdmulh z0.d, z1.d, z15.d[1]
// CHECK-INST: sqrdmulh z0.d, z1.d, z15.d[1]
// CHECK-ENCODING: [0x20,0xf4,0xff,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 f4 ff 44 <unknown>

test/MC/AArch64/SVE2/sqrshl-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
sqrshl z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sqrshl z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
sqrshl z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshl z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshl z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshl z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
sqrshl z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sqrshl z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqrshl.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqrshl z0.b, p0/m, z0.b, z1.b
// CHECK-INST: sqrshl z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x0a,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 0a 44 <unknown>
sqrshl z0.h, p0/m, z0.h, z1.h
// CHECK-INST: sqrshl z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x4a,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 4a 44 <unknown>
sqrshl z29.s, p7/m, z29.s, z30.s
// CHECK-INST: sqrshl z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x8a,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 8a 44 <unknown>
sqrshl z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqrshl z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xca,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f ca 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
sqrshl z31.d, p0/m, z31.d, z30.d
// CHECK-INST: sqrshl z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xca,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 ca 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sqrshl z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqrshl z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xca,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f ca 44 <unknown>

test/MC/AArch64/SVE2/sqrshlr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
sqrshlr z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sqrshlr z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
sqrshlr z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshlr z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshlr z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshlr z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
sqrshlr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sqrshlr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqrshlr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqrshlr z0.b, p0/m, z0.b, z1.b
// CHECK-INST: sqrshlr z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x0e,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 0e 44 <unknown>
sqrshlr z0.h, p0/m, z0.h, z1.h
// CHECK-INST: sqrshlr z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x4e,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 4e 44 <unknown>
sqrshlr z29.s, p7/m, z29.s, z30.s
// CHECK-INST: sqrshlr z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x8e,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 8e 44 <unknown>
sqrshlr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqrshlr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xce,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f ce 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
sqrshlr z31.d, p0/m, z31.d, z30.d
// CHECK-INST: sqrshlr z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xce,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 ce 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sqrshlr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqrshlr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xce,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f ce 44 <unknown>

test/MC/AArch64/SVE2/sqrshrnb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
sqrshrnb z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqrshrnb z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnb z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqrshrnb z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnb z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqrshrnb z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnb z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqrshrnb z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnb z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqrshrnb z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnb z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqrshrnb z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
sqrshrnb z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrnb z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnb z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrnb z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnb z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrnb z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnb z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrnb z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
sqrshrnb z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqrshrnb z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqrshrnb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqrshrnb z0.b, z0.h, #1
// CHECK-INST: sqrshrnb z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x28,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 28 2f 45 <unknown>
sqrshrnb z31.b, z31.h, #8
// CHECK-INST: sqrshrnb z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x2b,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 2b 28 45 <unknown>
sqrshrnb z0.h, z0.s, #1
// CHECK-INST: sqrshrnb z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x28,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 28 3f 45 <unknown>
sqrshrnb z31.h, z31.s, #16
// CHECK-INST: sqrshrnb z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x2b,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 2b 30 45 <unknown>
sqrshrnb z0.s, z0.d, #1
// CHECK-INST: sqrshrnb z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x28,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 28 7f 45 <unknown>
sqrshrnb z31.s, z31.d, #32
// CHECK-INST: sqrshrnb z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x2b,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 2b 60 45 <unknown>

test/MC/AArch64/SVE2/sqrshrnt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
sqrshrnt z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqrshrnt z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnt z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqrshrnt z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnt z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqrshrnt z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnt z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqrshrnt z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnt z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqrshrnt z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnt z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqrshrnt z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
sqrshrnt z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrnt z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnt z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrnt z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnt z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrnt z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrnt z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrnt z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
sqrshrnt z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqrshrnt z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqrshrnt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqrshrnt z0.b, z0.h, #1
// CHECK-INST: sqrshrnt z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x2c,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 2c 2f 45 <unknown>
sqrshrnt z31.b, z31.h, #8
// CHECK-INST: sqrshrnt z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x2f,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 2f 28 45 <unknown>
sqrshrnt z0.h, z0.s, #1
// CHECK-INST: sqrshrnt z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x2c,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 2c 3f 45 <unknown>
sqrshrnt z31.h, z31.s, #16
// CHECK-INST: sqrshrnt z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x2f,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 2f 30 45 <unknown>
sqrshrnt z0.s, z0.d, #1
// CHECK-INST: sqrshrnt z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x2c,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 2c 7f 45 <unknown>
sqrshrnt z31.s, z31.d, #32
// CHECK-INST: sqrshrnt z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x2f,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 2f 60 45 <unknown>

test/MC/AArch64/SVE2/sqrshrunb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
sqrshrunb z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqrshrunb z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunb z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqrshrunb z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunb z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqrshrunb z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunb z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqrshrunb z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunb z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqrshrunb z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunb z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqrshrunb z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
sqrshrunb z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrunb z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunb z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrunb z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunb z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrunb z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunb z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrunb z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
sqrshrunb z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqrshrunb z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqrshrunb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqrshrunb z0.b, z0.h, #1
// CHECK-INST: sqrshrunb z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x08,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 08 2f 45 <unknown>
sqrshrunb z31.b, z31.h, #8
// CHECK-INST: sqrshrunb z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x0b,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 0b 28 45 <unknown>
sqrshrunb z0.h, z0.s, #1
// CHECK-INST: sqrshrunb z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x08,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 08 3f 45 <unknown>
sqrshrunb z31.h, z31.s, #16
// CHECK-INST: sqrshrunb z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x0b,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 0b 30 45 <unknown>
sqrshrunb z0.s, z0.d, #1
// CHECK-INST: sqrshrunb z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x08,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 08 7f 45 <unknown>
sqrshrunb z31.s, z31.d, #32
// CHECK-INST: sqrshrunb z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x0b,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 0b 60 45 <unknown>

test/MC/AArch64/SVE2/sqrshrunt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
sqrshrunt z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqrshrunt z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunt z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqrshrunt z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunt z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqrshrunt z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunt z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqrshrunt z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunt z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqrshrunt z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunt z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqrshrunt z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
sqrshrunt z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrunt z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunt z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrunt z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunt z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrunt z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrunt z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrunt z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
sqrshrunt z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqrshrunt z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqrshrunt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqrshrunt z0.b, z0.h, #1
// CHECK-INST: sqrshrunt z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x0c,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 0c 2f 45 <unknown>
sqrshrunt z31.b, z31.h, #8
// CHECK-INST: sqrshrunt z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x0f,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 0f 28 45 <unknown>
sqrshrunt z0.h, z0.s, #1
// CHECK-INST: sqrshrunt z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x0c,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 0c 3f 45 <unknown>
sqrshrunt z31.h, z31.s, #16
// CHECK-INST: sqrshrunt z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x0f,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 0f 30 45 <unknown>
sqrshrunt z0.s, z0.d, #1
// CHECK-INST: sqrshrunt z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x0c,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 0c 7f 45 <unknown>
sqrshrunt z31.s, z31.d, #32
// CHECK-INST: sqrshrunt z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x0f,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 0f 60 45 <unknown>

test/MC/AArch64/SVE2/sqshl-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
sqshl z0.b, p0/m, z0.b, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: sqshl z0.b, p0/m, z0.b, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshl z0.b, p0/m, z0.b, #8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: sqshl z0.b, p0/m, z0.b, #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshl z0.h, p0/m, z0.h, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: sqshl z0.h, p0/m, z0.h, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshl z0.h, p0/m, z0.h, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: sqshl z0.h, p0/m, z0.h, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshl z0.s, p0/m, z0.s, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: sqshl z0.s, p0/m, z0.s, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshl z0.s, p0/m, z0.s, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: sqshl z0.s, p0/m, z0.s, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshl z0.d, p0/m, z0.d, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
// CHECK-NEXT: sqshl z0.d, p0/m, z0.d, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshl z0.d, p0/m, z0.d, #64
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
// CHECK-NEXT: sqshl z0.d, p0/m, z0.d, #64
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
sqshl z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sqshl z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshl z0.b, p0/m, z1.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sqshl z0.b, p0/m, z1.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
sqshl z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshl z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshl z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshl z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshl z0.b, p0/m, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshl z0.b, p0/m, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshl z0.d, p0/m, z0.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshl z0.d, p0/m, z0.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
sqshl z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sqshl z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshl z0.b, p8/m, z0.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sqshl z0.b, p8/m, z0.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqshl.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqshl z0.b, p0/m, z0.b, z1.b
// CHECK-INST: sqshl z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x08,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 08 44 <unknown>
sqshl z0.h, p0/m, z0.h, z1.h
// CHECK-INST: sqshl z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x48,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 48 44 <unknown>
sqshl z29.s, p7/m, z29.s, z30.s
// CHECK-INST: sqshl z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x88,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 88 44 <unknown>
sqshl z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqshl z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xc8,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f c8 44 <unknown>
sqshl z0.b, p0/m, z0.b, #0
// CHECK-INST: sqshl z0.b, p0/m, z0.b, #0
// CHECK-ENCODING: [0x00,0x81,0x06,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 81 06 04 <unknown>
sqshl z31.b, p0/m, z31.b, #7
// CHECK-INST: sqshl z31.b, p0/m, z31.b, #7
// CHECK-ENCODING: [0xff,0x81,0x06,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 81 06 04 <unknown>
sqshl z0.h, p0/m, z0.h, #0
// CHECK-INST: sqshl z0.h, p0/m, z0.h, #0
// CHECK-ENCODING: [0x00,0x82,0x06,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 82 06 04 <unknown>
sqshl z31.h, p0/m, z31.h, #15
// CHECK-INST: sqshl z31.h, p0/m, z31.h, #15
// CHECK-ENCODING: [0xff,0x83,0x06,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 06 04 <unknown>
sqshl z0.s, p0/m, z0.s, #0
// CHECK-INST: sqshl z0.s, p0/m, z0.s, #0
// CHECK-ENCODING: [0x00,0x80,0x46,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 80 46 04 <unknown>
sqshl z31.s, p0/m, z31.s, #31
// CHECK-INST: sqshl z31.s, p0/m, z31.s, #31
// CHECK-ENCODING: [0xff,0x83,0x46,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 46 04 <unknown>
sqshl z0.d, p0/m, z0.d, #0
// CHECK-INST: sqshl z0.d, p0/m, z0.d, #0
// CHECK-ENCODING: [0x00,0x80,0x86,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 80 86 04 <unknown>
sqshl z31.d, p0/m, z31.d, #63
// CHECK-INST: sqshl z31.d, p0/m, z31.d, #63
// CHECK-ENCODING: [0xff,0x83,0xc6,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 c6 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
sqshl z31.d, p0/m, z31.d, z30.d
// CHECK-INST: sqshl z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xc8,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 c8 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sqshl z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqshl z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xc8,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f c8 44 <unknown>
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
sqshl z31.d, p0/m, z31.d, #63
// CHECK-INST: sqshl z31.d, p0/m, z31.d, #63
// CHECK-ENCODING: [0xff,0x83,0xc6,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 c6 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sqshl z31.d, p0/m, z31.d, #63
// CHECK-INST: sqshl z31.d, p0/m, z31.d, #63
// CHECK-ENCODING: [0xff,0x83,0xc6,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 c6 04 <unknown>

test/MC/AArch64/SVE2/sqshlr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
sqshlr z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sqshlr z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
sqshlr z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshlr z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshlr z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshlr z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
sqshlr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sqshlr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqshlr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqshlr z0.b, p0/m, z0.b, z1.b
// CHECK-INST: sqshlr z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x0c,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 0c 44 <unknown>
sqshlr z0.h, p0/m, z0.h, z1.h
// CHECK-INST: sqshlr z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x4c,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 4c 44 <unknown>
sqshlr z29.s, p7/m, z29.s, z30.s
// CHECK-INST: sqshlr z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x8c,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 8c 44 <unknown>
sqshlr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqshlr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xcc,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f cc 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
sqshlr z31.d, p0/m, z31.d, z30.d
// CHECK-INST: sqshlr z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xcc,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 cc 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sqshlr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqshlr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xcc,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f cc 44 <unknown>

test/MC/AArch64/SVE2/sqshlu-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
sqshlu z0.b, p0/m, z0.b, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: sqshlu z0.b, p0/m, z0.b, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshlu z0.b, p0/m, z0.b, #8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: sqshlu z0.b, p0/m, z0.b, #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshlu z0.h, p0/m, z0.h, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: sqshlu z0.h, p0/m, z0.h, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshlu z0.h, p0/m, z0.h, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: sqshlu z0.h, p0/m, z0.h, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshlu z0.s, p0/m, z0.s, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: sqshlu z0.s, p0/m, z0.s, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshlu z0.s, p0/m, z0.s, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: sqshlu z0.s, p0/m, z0.s, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshlu z0.d, p0/m, z0.d, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
// CHECK-NEXT: sqshlu z0.d, p0/m, z0.d, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshlu z0.d, p0/m, z0.d, #64
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
// CHECK-NEXT: sqshlu z0.d, p0/m, z0.d, #64
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
sqshlu z0.b, p0/m, z1.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sqshlu z0.b, p0/m, z1.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
sqshlu z0.b, p0/m, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshlu z0.b, p0/m, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshlu z0.d, p0/m, z0.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshlu z0.d, p0/m, z0.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
sqshlu z0.b, p8/m, z0.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sqshlu z0.b, p8/m, z0.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqshlu.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqshlu z0.b, p0/m, z0.b, #0
// CHECK-INST: sqshlu z0.b, p0/m, z0.b, #0
// CHECK-ENCODING: [0x00,0x81,0x0f,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 81 0f 04 <unknown>
sqshlu z31.b, p0/m, z31.b, #7
// CHECK-INST: sqshlu z31.b, p0/m, z31.b, #7
// CHECK-ENCODING: [0xff,0x81,0x0f,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 81 0f 04 <unknown>
sqshlu z0.h, p0/m, z0.h, #0
// CHECK-INST: sqshlu z0.h, p0/m, z0.h, #0
// CHECK-ENCODING: [0x00,0x82,0x0f,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 82 0f 04 <unknown>
sqshlu z31.h, p0/m, z31.h, #15
// CHECK-INST: sqshlu z31.h, p0/m, z31.h, #15
// CHECK-ENCODING: [0xff,0x83,0x0f,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 0f 04 <unknown>
sqshlu z0.s, p0/m, z0.s, #0
// CHECK-INST: sqshlu z0.s, p0/m, z0.s, #0
// CHECK-ENCODING: [0x00,0x80,0x4f,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 80 4f 04 <unknown>
sqshlu z31.s, p0/m, z31.s, #31
// CHECK-INST: sqshlu z31.s, p0/m, z31.s, #31
// CHECK-ENCODING: [0xff,0x83,0x4f,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 4f 04 <unknown>
sqshlu z0.d, p0/m, z0.d, #0
// CHECK-INST: sqshlu z0.d, p0/m, z0.d, #0
// CHECK-ENCODING: [0x00,0x80,0x8f,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 80 8f 04 <unknown>
sqshlu z31.d, p0/m, z31.d, #63
// CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63
// CHECK-ENCODING: [0xff,0x83,0xcf,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 cf 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
sqshlu z31.d, p0/m, z31.d, #63
// CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63
// CHECK-ENCODING: [0xff,0x83,0xcf,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 cf 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sqshlu z31.d, p0/m, z31.d, #63
// CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63
// CHECK-ENCODING: [0xff,0x83,0xcf,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 cf 04 <unknown>

test/MC/AArch64/SVE2/sqshrnb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
sqshrnb z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqshrnb z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnb z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqshrnb z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnb z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqshrnb z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnb z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqshrnb z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnb z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqshrnb z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnb z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqshrnb z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
sqshrnb z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrnb z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnb z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrnb z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnb z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrnb z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnb z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrnb z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
sqshrnb z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqshrnb z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqshrnb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqshrnb z0.b, z0.h, #1
// CHECK-INST: sqshrnb z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x20,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 20 2f 45 <unknown>
sqshrnb z31.b, z31.h, #8
// CHECK-INST: sqshrnb z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x23,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 23 28 45 <unknown>
sqshrnb z0.h, z0.s, #1
// CHECK-INST: sqshrnb z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x20,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 20 3f 45 <unknown>
sqshrnb z31.h, z31.s, #16
// CHECK-INST: sqshrnb z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x23,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 23 30 45 <unknown>
sqshrnb z0.s, z0.d, #1
// CHECK-INST: sqshrnb z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x20,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 20 7f 45 <unknown>
sqshrnb z31.s, z31.d, #32
// CHECK-INST: sqshrnb z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x23,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 23 60 45 <unknown>

test/MC/AArch64/SVE2/sqshrnt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
sqshrnt z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqshrnt z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnt z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqshrnt z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnt z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqshrnt z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnt z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqshrnt z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnt z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqshrnt z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnt z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqshrnt z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
sqshrnt z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrnt z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnt z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrnt z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnt z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrnt z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrnt z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrnt z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
sqshrnt z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqshrnt z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqshrnt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqshrnt z0.b, z0.h, #1
// CHECK-INST: sqshrnt z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x24,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 24 2f 45 <unknown>
sqshrnt z31.b, z31.h, #8
// CHECK-INST: sqshrnt z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x27,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 27 28 45 <unknown>
sqshrnt z0.h, z0.s, #1
// CHECK-INST: sqshrnt z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x24,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 24 3f 45 <unknown>
sqshrnt z31.h, z31.s, #16
// CHECK-INST: sqshrnt z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x27,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 27 30 45 <unknown>
sqshrnt z0.s, z0.d, #1
// CHECK-INST: sqshrnt z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x24,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 24 7f 45 <unknown>
sqshrnt z31.s, z31.d, #32
// CHECK-INST: sqshrnt z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x27,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 27 60 45 <unknown>

test/MC/AArch64/SVE2/sqshrunb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
sqshrunb z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqshrunb z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunb z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqshrunb z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunb z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqshrunb z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunb z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqshrunb z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunb z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqshrunb z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunb z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqshrunb z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
sqshrunb z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrunb z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunb z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrunb z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunb z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrunb z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunb z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrunb z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
sqshrunb z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqshrunb z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqshrunb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqshrunb z0.b, z0.h, #1
// CHECK-INST: sqshrunb z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x00,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 00 2f 45 <unknown>
sqshrunb z31.b, z31.h, #8
// CHECK-INST: sqshrunb z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x03,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 03 28 45 <unknown>
sqshrunb z0.h, z0.s, #1
// CHECK-INST: sqshrunb z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x00,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 00 3f 45 <unknown>
sqshrunb z31.h, z31.s, #16
// CHECK-INST: sqshrunb z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x03,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 03 30 45 <unknown>
sqshrunb z0.s, z0.d, #1
// CHECK-INST: sqshrunb z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x00,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 00 7f 45 <unknown>
sqshrunb z31.s, z31.d, #32
// CHECK-INST: sqshrunb z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x03,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 03 60 45 <unknown>

test/MC/AArch64/SVE2/sqshrunt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
sqshrunt z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqshrunt z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunt z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sqshrunt z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunt z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqshrunt z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunt z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqshrunt z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunt z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqshrunt z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunt z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sqshrunt z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
sqshrunt z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrunt z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunt z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrunt z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunt z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrunt z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshrunt z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqshrunt z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
sqshrunt z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqshrunt z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqshrunt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqshrunt z0.b, z0.h, #1
// CHECK-INST: sqshrunt z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x04,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 04 2f 45 <unknown>
sqshrunt z31.b, z31.h, #8
// CHECK-INST: sqshrunt z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x07,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 07 28 45 <unknown>
sqshrunt z0.h, z0.s, #1
// CHECK-INST: sqshrunt z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x04,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 04 3f 45 <unknown>
sqshrunt z31.h, z31.s, #16
// CHECK-INST: sqshrunt z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x07,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 07 30 45 <unknown>
sqshrunt z0.s, z0.d, #1
// CHECK-INST: sqshrunt z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x04,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 04 7f 45 <unknown>
sqshrunt z31.s, z31.d, #32
// CHECK-INST: sqshrunt z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x07,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 07 60 45 <unknown>

test/MC/AArch64/SVE2/sqsub-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
sqsub z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sqsub z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
sqsub z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqsub z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqsub z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqsub z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
sqsub z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sqsub z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqsub.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqsub z0.b, p0/m, z0.b, z1.b
// CHECK-INST: sqsub z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x1a,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 1a 44 <unknown>
sqsub z0.h, p0/m, z0.h, z1.h
// CHECK-INST: sqsub z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x5a,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 5a 44 <unknown>
sqsub z29.s, p7/m, z29.s, z30.s
// CHECK-INST: sqsub z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x9a,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 9a 44 <unknown>
sqsub z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqsub z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xda,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f da 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
sqsub z31.d, p0/m, z31.d, z30.d
// CHECK-INST: sqsub z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xda,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 da 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sqsub z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqsub z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xda,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f da 44 <unknown>

test/MC/AArch64/SVE2/sqsubr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
sqsubr z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sqsubr z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
sqsubr z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqsubr z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqsubr z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqsubr z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
sqsubr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sqsubr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqsubr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqsubr z0.b, p0/m, z0.b, z1.b
// CHECK-INST: sqsubr z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x1e,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 1e 44 <unknown>
sqsubr z0.h, p0/m, z0.h, z1.h
// CHECK-INST: sqsubr z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x5e,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 5e 44 <unknown>
sqsubr z29.s, p7/m, z29.s, z30.s
// CHECK-INST: sqsubr z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x9e,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 9e 44 <unknown>
sqsubr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqsubr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xde,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f de 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
sqsubr z31.d, p0/m, z31.d, z30.d
// CHECK-INST: sqsubr z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xde,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 de 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
sqsubr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: sqsubr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xde,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f de 44 <unknown>

test/MC/AArch64/SVE2/sqxtnb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
sqxtnb z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtnb z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqxtnb z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtnb z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqxtnb z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtnb z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqxtnb z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtnb z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
sqxtnb z0.s, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqxtnb z0.s, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
sqxtnb z0.s, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqxtnb z0.s, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqxtnb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqxtnb z0.b, z31.h
// CHECK-INST: sqxtnb z0.b, z31.h
// CHECK-ENCODING: [0xe0,0x43,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 43 28 45 <unknown>
sqxtnb z0.h, z31.s
// CHECK-INST: sqxtnb z0.h, z31.s
// CHECK-ENCODING: [0xe0,0x43,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 43 30 45 <unknown>
sqxtnb z0.s, z31.d
// CHECK-INST: sqxtnb z0.s, z31.d
// CHECK-ENCODING: [0xe0,0x43,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 43 60 45 <unknown>

test/MC/AArch64/SVE2/sqxtnt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
sqxtnt z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtnt z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqxtnt z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtnt z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqxtnt z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtnt z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqxtnt z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtnt z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
sqxtnt z0.s, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqxtnt z0.s, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
sqxtnt z0.s, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqxtnt z0.s, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqxtnt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqxtnt z0.b, z31.h
// CHECK-INST: sqxtnt z0.b, z31.h
// CHECK-ENCODING: [0xe0,0x47,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 47 28 45 <unknown>
sqxtnt z0.h, z31.s
// CHECK-INST: sqxtnt z0.h, z31.s
// CHECK-ENCODING: [0xe0,0x47,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 47 30 45 <unknown>
sqxtnt z0.s, z31.d
// CHECK-INST: sqxtnt z0.s, z31.d
// CHECK-ENCODING: [0xe0,0x47,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 47 60 45 <unknown>

test/MC/AArch64/SVE2/sqxtunb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
sqxtunb z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtunb z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqxtunb z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtunb z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqxtunb z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtunb z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqxtunb z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtunb z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
sqxtunb z0.s, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqxtunb z0.s, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
sqxtunb z0.s, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqxtunb z0.s, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqxtunb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqxtunb z0.b, z31.h
// CHECK-INST: sqxtunb z0.b, z31.h
// CHECK-ENCODING: [0xe0,0x53,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 53 28 45 <unknown>
sqxtunb z0.h, z31.s
// CHECK-INST: sqxtunb z0.h, z31.s
// CHECK-ENCODING: [0xe0,0x53,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 53 30 45 <unknown>
sqxtunb z0.s, z31.d
// CHECK-INST: sqxtunb z0.s, z31.d
// CHECK-ENCODING: [0xe0,0x53,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 53 60 45 <unknown>

test/MC/AArch64/SVE2/sqxtunt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
sqxtunt z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtunt z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqxtunt z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtunt z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqxtunt z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtunt z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqxtunt z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqxtunt z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
sqxtunt z0.s, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqxtunt z0.s, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
sqxtunt z0.s, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sqxtunt z0.s, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqxtunt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqxtunt z0.b, z31.h
// CHECK-INST: sqxtunt z0.b, z31.h
// CHECK-ENCODING: [0xe0,0x57,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 57 28 45 <unknown>
sqxtunt z0.h, z31.s
// CHECK-INST: sqxtunt z0.h, z31.s
// CHECK-ENCODING: [0xe0,0x57,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 57 30 45 <unknown>
sqxtunt z0.s, z31.d
// CHECK-INST: sqxtunt z0.s, z31.d
// CHECK-ENCODING: [0xe0,0x57,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 57 60 45 <unknown>

test/MC/AArch64/SVE2/srhadd-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
srhadd z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: srhadd z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
srhadd z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: srhadd z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srhadd z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: srhadd z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
srhadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: srhadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/srhadd.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
srhadd z0.b, p0/m, z0.b, z1.b
// CHECK-INST: srhadd z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x14,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 14 44 <unknown>
srhadd z0.h, p0/m, z0.h, z1.h
// CHECK-INST: srhadd z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x54,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 54 44 <unknown>
srhadd z29.s, p7/m, z29.s, z30.s
// CHECK-INST: srhadd z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x94,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 94 44 <unknown>
srhadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: srhadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd4,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d4 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
srhadd z31.d, p0/m, z31.d, z30.d
// CHECK-INST: srhadd z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xd4,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 d4 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
srhadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: srhadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd4,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d4 44 <unknown>

test/MC/AArch64/SVE2/sri-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
sri z30.b, z10.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sri z30.b, z10.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sri z18.b, z27.b, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: sri z18.b, z27.b, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sri z26.h, z4.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sri z26.h, z4.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sri z25.h, z10.h, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sri z25.h, z10.h, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sri z17.s, z0.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sri z17.s, z0.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sri z0.s, z15.s, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: sri z0.s, z15.s, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sri z4.d, z13.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: sri z4.d, z13.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sri z26.d, z26.d, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: sri z26.d, z26.d, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
sri z0.b, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sri z0.b, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
sri z31.d, z31.d, #64
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sri z31.d, z31.d, #64
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sri.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sri z0.b, z0.b, #1
// CHECK-INST: sri z0.b, z0.b, #1
// CHECK-ENCODING: [0x00,0xf0,0x0f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 f0 0f 45 <unknown>
sri z31.b, z31.b, #8
// CHECK-INST: sri z31.b, z31.b, #8
// CHECK-ENCODING: [0xff,0xf3,0x08,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff f3 08 45 <unknown>
sri z0.h, z0.h, #1
// CHECK-INST: sri z0.h, z0.h, #1
// CHECK-ENCODING: [0x00,0xf0,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 f0 1f 45 <unknown>
sri z31.h, z31.h, #16
// CHECK-INST: sri z31.h, z31.h, #16
// CHECK-ENCODING: [0xff,0xf3,0x10,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff f3 10 45 <unknown>
sri z0.s, z0.s, #1
// CHECK-INST: sri z0.s, z0.s, #1
// CHECK-ENCODING: [0x00,0xf0,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 f0 5f 45 <unknown>
sri z31.s, z31.s, #32
// CHECK-INST: sri z31.s, z31.s, #32
// CHECK-ENCODING: [0xff,0xf3,0x40,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff f3 40 45 <unknown>
sri z0.d, z0.d, #1
// CHECK-INST: sri z0.d, z0.d, #1
// CHECK-ENCODING: [0x00,0xf0,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 f0 df 45 <unknown>
sri z31.d, z31.d, #64
// CHECK-INST: sri z31.d, z31.d, #64
// CHECK-ENCODING: [0xff,0xf3,0x80,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff f3 80 45 <unknown>

test/MC/AArch64/SVE2/srshl-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
srshl z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: srshl z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
srshl z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: srshl z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srshl z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: srshl z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
srshl z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: srshl z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/srshl.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
srshl z0.b, p0/m, z0.b, z1.b
// CHECK-INST: srshl z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x02,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 02 44 <unknown>
srshl z0.h, p0/m, z0.h, z1.h
// CHECK-INST: srshl z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x42,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 42 44 <unknown>
srshl z29.s, p7/m, z29.s, z30.s
// CHECK-INST: srshl z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x82,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 82 44 <unknown>
srshl z31.d, p7/m, z31.d, z30.d
// CHECK-INST: srshl z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xc2,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f c2 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
srshl z31.d, p0/m, z31.d, z30.d
// CHECK-INST: srshl z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xc2,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 c2 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
srshl z31.d, p7/m, z31.d, z30.d
// CHECK-INST: srshl z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xc2,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f c2 44 <unknown>

test/MC/AArch64/SVE2/srshlr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
srshlr z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: srshlr z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
srshlr z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: srshlr z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srshlr z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: srshlr z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
srshlr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: srshlr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/srshlr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
srshlr z0.b, p0/m, z0.b, z1.b
// CHECK-INST: srshlr z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x06,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 06 44 <unknown>
srshlr z0.h, p0/m, z0.h, z1.h
// CHECK-INST: srshlr z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x46,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 46 44 <unknown>
srshlr z29.s, p7/m, z29.s, z30.s
// CHECK-INST: srshlr z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x86,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 86 44 <unknown>
srshlr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: srshlr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xc6,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f c6 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
srshlr z31.d, p0/m, z31.d, z30.d
// CHECK-INST: srshlr z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xc6,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 c6 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
srshlr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: srshlr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xc6,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f c6 44 <unknown>

test/MC/AArch64/SVE2/srshr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
srshr z18.b, p0/m, z18.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: srshr z18.b, p0/m, z18.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srshr z1.b, p0/m, z1.b, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: srshr z1.b, p0/m, z1.b, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srshr z21.h, p0/m, z21.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: srshr z21.h, p0/m, z21.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srshr z14.h, p0/m, z14.h, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: srshr z14.h, p0/m, z14.h, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srshr z6.s, p0/m, z6.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: srshr z6.s, p0/m, z6.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srshr z23.s, p0/m, z23.s, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: srshr z23.s, p0/m, z23.s, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srshr z3.d, p0/m, z3.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: srshr z3.d, p0/m, z3.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srshr z25.d, p0/m, z25.d, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: srshr z25.d, p0/m, z25.d, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/srshr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
srshr z0.b, p0/m, z0.b, #1
// CHECK-INST: srshr z0.b, p0/m, z0.b, #1
// CHECK-ENCODING: [0xe0,0x81,0x0c,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 81 0c 04 <unknown>
srshr z31.b, p0/m, z31.b, #8
// CHECK-INST: srshr z31.b, p0/m, z31.b, #8
// CHECK-ENCODING: [0x1f,0x81,0x0c,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 81 0c 04 <unknown>
srshr z0.h, p0/m, z0.h, #1
// CHECK-INST: srshr z0.h, p0/m, z0.h, #1
// CHECK-ENCODING: [0xe0,0x83,0x0c,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 83 0c 04 <unknown>
srshr z31.h, p0/m, z31.h, #16
// CHECK-INST: srshr z31.h, p0/m, z31.h, #16
// CHECK-ENCODING: [0x1f,0x82,0x0c,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 82 0c 04 <unknown>
srshr z0.s, p0/m, z0.s, #1
// CHECK-INST: srshr z0.s, p0/m, z0.s, #1
// CHECK-ENCODING: [0xe0,0x83,0x4c,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 83 4c 04 <unknown>
srshr z31.s, p0/m, z31.s, #32
// CHECK-INST: srshr z31.s, p0/m, z31.s, #32
// CHECK-ENCODING: [0x1f,0x80,0x4c,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 80 4c 04 <unknown>
srshr z0.d, p0/m, z0.d, #1
// CHECK-INST: srshr z0.d, p0/m, z0.d, #1
// CHECK-ENCODING: [0xe0,0x83,0xcc,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 83 cc 04 <unknown>
srshr z31.d, p0/m, z31.d, #64
// CHECK-INST: srshr z31.d, p0/m, z31.d, #64
// CHECK-ENCODING: [0x1f,0x80,0x8c,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 80 8c 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
srshr z31.d, p0/m, z31.d, #64
// CHECK-INST: srshr z31.d, p0/m, z31.d, #64
// CHECK-ENCODING: [0x1f,0x80,0x8c,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 80 8c 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
srshr z31.d, p0/m, z31.d, #64
// CHECK-INST: srshr z31.d, p0/m, z31.d, #64
// CHECK-ENCODING: [0x1f,0x80,0x8c,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 80 8c 04 <unknown>

test/MC/AArch64/SVE2/srsra-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
srsra z30.b, z10.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: srsra z30.b, z10.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srsra z18.b, z27.b, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: srsra z18.b, z27.b, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srsra z26.h, z4.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: srsra z26.h, z4.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srsra z25.h, z10.h, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: srsra z25.h, z10.h, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srsra z17.s, z0.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: srsra z17.s, z0.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srsra z0.s, z15.s, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: srsra z0.s, z15.s, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srsra z4.d, z13.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: srsra z4.d, z13.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srsra z26.d, z26.d, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: srsra z26.d, z26.d, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
srsra z0.b, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: srsra z0.b, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
srsra z0.d, z1.d, #64
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: srsra z0.d, z1.d, #64
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/srsra.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
srsra z0.b, z0.b, #1
// CHECK-INST: srsra z0.b, z0.b, #1
// CHECK-ENCODING: [0x00,0xe8,0x0f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 e8 0f 45 <unknown>
srsra z31.b, z31.b, #8
// CHECK-INST: srsra z31.b, z31.b, #8
// CHECK-ENCODING: [0xff,0xeb,0x08,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff eb 08 45 <unknown>
srsra z0.h, z0.h, #1
// CHECK-INST: srsra z0.h, z0.h, #1
// CHECK-ENCODING: [0x00,0xe8,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 e8 1f 45 <unknown>
srsra z31.h, z31.h, #16
// CHECK-INST: srsra z31.h, z31.h, #16
// CHECK-ENCODING: [0xff,0xeb,0x10,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff eb 10 45 <unknown>
srsra z0.s, z0.s, #1
// CHECK-INST: srsra z0.s, z0.s, #1
// CHECK-ENCODING: [0x00,0xe8,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 e8 5f 45 <unknown>
srsra z31.s, z31.s, #32
// CHECK-INST: srsra z31.s, z31.s, #32
// CHECK-ENCODING: [0xff,0xeb,0x40,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff eb 40 45 <unknown>
srsra z0.d, z0.d, #1
// CHECK-INST: srsra z0.d, z0.d, #1
// CHECK-ENCODING: [0x00,0xe8,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 e8 df 45 <unknown>
srsra z31.d, z31.d, #64
// CHECK-INST: srsra z31.d, z31.d, #64
// CHECK-ENCODING: [0xff,0xeb,0x80,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff eb 80 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
srsra z0.d, z1.d, #1
// CHECK-INST: srsra z0.d, z1.d, #1
// CHECK-ENCODING: [0x20,0xe8,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 e8 df 45 <unknown>

test/MC/AArch64/SVE2/sshllb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
sshllb z18.h, z28.b, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: sshllb z18.h, z28.b, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllb z1.h, z9.b, #8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: sshllb z1.h, z9.b, #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllb z21.s, z2.h, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: sshllb z21.s, z2.h, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllb z14.s, z30.h, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: sshllb z14.s, z30.h, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllb z6.d, z12.s, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: sshllb z6.d, z12.s, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllb z23.d, z19.s, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: sshllb z23.d, z19.s, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
sshllb z0.b, z0.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sshllb z0.b, z0.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllb z0.h, z0.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sshllb z0.h, z0.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllb z0.s, z0.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sshllb z0.s, z0.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllb z0.d, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sshllb z0.d, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
sshllb z31.d, z31.s, #31
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sshllb z31.d, z31.s, #31
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.d, p0/m, z6.d
sshllb z31.d, z31.s, #31
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sshllb z31.d, z31.s, #31
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sshllb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sshllb z0.h, z0.b, #0
// CHECK-INST: sshllb z0.h, z0.b, #0
// CHECK-ENCODING: [0x00,0xa0,0x08,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 a0 08 45 <unknown>
sshllb z31.h, z31.b, #7
// CHECK-INST: sshllb z31.h, z31.b, #7
// CHECK-ENCODING: [0xff,0xa3,0x0f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff a3 0f 45 <unknown>
sshllb z0.s, z0.h, #0
// CHECK-INST: sshllb z0.s, z0.h, #0
// CHECK-ENCODING: [0x00,0xa0,0x10,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 a0 10 45 <unknown>
sshllb z31.s, z31.h, #15
// CHECK-INST: sshllb z31.s, z31.h, #15
// CHECK-ENCODING: [0xff,0xa3,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff a3 1f 45 <unknown>
sshllb z0.d, z0.s, #0
// CHECK-INST: sshllb z0.d, z0.s, #0
// CHECK-ENCODING: [0x00,0xa0,0x40,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 a0 40 45 <unknown>
sshllb z31.d, z31.s, #31
// CHECK-INST: sshllb z31.d, z31.s, #31
// CHECK-ENCODING: [0xff,0xa3,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff a3 5f 45 <unknown>

test/MC/AArch64/SVE2/sshllt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
sshllt z18.h, z28.b, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: sshllt z18.h, z28.b, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllt z1.h, z9.b, #8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: sshllt z1.h, z9.b, #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllt z21.s, z2.h, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: sshllt z21.s, z2.h, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllt z14.s, z30.h, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: sshllt z14.s, z30.h, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllt z6.d, z12.s, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: sshllt z6.d, z12.s, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllt z23.d, z19.s, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: sshllt z23.d, z19.s, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
sshllt z0.b, z0.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sshllt z0.b, z0.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllt z0.h, z0.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sshllt z0.h, z0.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllt z0.s, z0.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sshllt z0.s, z0.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sshllt z0.d, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sshllt z0.d, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
sshllt z31.d, z31.s, #31
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sshllt z31.d, z31.s, #31
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.d, p0/m, z6.d
sshllt z31.d, z31.s, #31
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sshllt z31.d, z31.s, #31
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sshllt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sshllt z0.h, z0.b, #0
// CHECK-INST: sshllt z0.h, z0.b, #0
// CHECK-ENCODING: [0x00,0xa4,0x08,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 a4 08 45 <unknown>
sshllt z31.h, z31.b, #7
// CHECK-INST: sshllt z31.h, z31.b, #7
// CHECK-ENCODING: [0xff,0xa7,0x0f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff a7 0f 45 <unknown>
sshllt z0.s, z0.h, #0
// CHECK-INST: sshllt z0.s, z0.h, #0
// CHECK-ENCODING: [0x00,0xa4,0x10,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 a4 10 45 <unknown>
sshllt z31.s, z31.h, #15
// CHECK-INST: sshllt z31.s, z31.h, #15
// CHECK-ENCODING: [0xff,0xa7,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff a7 1f 45 <unknown>
sshllt z0.d, z0.s, #0
// CHECK-INST: sshllt z0.d, z0.s, #0
// CHECK-ENCODING: [0x00,0xa4,0x40,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 a4 40 45 <unknown>
sshllt z31.d, z31.s, #31
// CHECK-INST: sshllt z31.d, z31.s, #31
// CHECK-ENCODING: [0xff,0xa7,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff a7 5f 45 <unknown>

test/MC/AArch64/SVE2/ssra-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
ssra z30.b, z10.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: ssra z30.b, z10.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssra z18.b, z27.b, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: ssra z18.b, z27.b, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssra z26.h, z4.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: ssra z26.h, z4.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssra z25.h, z10.h, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: ssra z25.h, z10.h, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssra z17.s, z0.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: ssra z17.s, z0.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssra z0.s, z15.s, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: ssra z0.s, z15.s, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssra z4.d, z13.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: ssra z4.d, z13.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssra z26.d, z26.d, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: ssra z26.d, z26.d, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
ssra z0.b, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssra z0.b, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ssra z0.d, z1.d, #64
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: ssra z0.d, z1.d, #64
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ssra.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ssra z0.b, z0.b, #1
// CHECK-INST: ssra z0.b, z0.b, #1
// CHECK-ENCODING: [0x00,0xe0,0x0f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 e0 0f 45 <unknown>
ssra z31.b, z31.b, #8
// CHECK-INST: ssra z31.b, z31.b, #8
// CHECK-ENCODING: [0xff,0xe3,0x08,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff e3 08 45 <unknown>
ssra z0.h, z0.h, #1
// CHECK-INST: ssra z0.h, z0.h, #1
// CHECK-ENCODING: [0x00,0xe0,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 e0 1f 45 <unknown>
ssra z31.h, z31.h, #16
// CHECK-INST: ssra z31.h, z31.h, #16
// CHECK-ENCODING: [0xff,0xe3,0x10,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff e3 10 45 <unknown>
ssra z0.s, z0.s, #1
// CHECK-INST: ssra z0.s, z0.s, #1
// CHECK-ENCODING: [0x00,0xe0,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 e0 5f 45 <unknown>
ssra z31.s, z31.s, #32
// CHECK-INST: ssra z31.s, z31.s, #32
// CHECK-ENCODING: [0xff,0xe3,0x40,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff e3 40 45 <unknown>
ssra z0.d, z0.d, #1
// CHECK-INST: ssra z0.d, z0.d, #1
// CHECK-ENCODING: [0x00,0xe0,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 e0 df 45 <unknown>
ssra z31.d, z31.d, #64
// CHECK-INST: ssra z31.d, z31.d, #64
// CHECK-ENCODING: [0xff,0xe3,0x80,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff e3 80 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
ssra z0.d, z1.d, #1
// CHECK-INST: ssra z0.d, z1.d, #1
// CHECK-ENCODING: [0x20,0xe0,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 e0 df 45 <unknown>

test/MC/AArch64/SVE2/ssublb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
ssublb z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssublb z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssublb z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssublb z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssublb z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssublb z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssublb z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssublb z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
ssublb z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ssublb z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
ssublb z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ssublb z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ssublb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ssublb z0.h, z1.b, z2.b
// CHECK-INST: ssublb z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x10,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 10 42 45 <unknown>
ssublb z29.s, z30.h, z31.h
// CHECK-INST: ssublb z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x13,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 13 9f 45 <unknown>
ssublb z31.d, z31.s, z31.s
// CHECK-INST: ssublb z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x13,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 13 df 45 <unknown>

test/MC/AArch64/SVE2/ssublbt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
ssublbt z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssublbt z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssublbt z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssublbt z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssublbt z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssublbt z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssublbt z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssublbt z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
ssublbt z0.h, z1.b, z7.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ssublbt z0.h, z1.b, z7.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.h, p0/z, z7.h
ssublbt z0.h, z1.b, z7.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ssublbt z0.h, z1.b, z7.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ssublbt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ssublbt z0.h, z1.b, z31.b
// CHECK-INST: ssublbt z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x88,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 88 5f 45 <unknown>
ssublbt z0.s, z1.h, z31.h
// CHECK-INST: ssublbt z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x88,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 88 9f 45 <unknown>
ssublbt z0.d, z1.s, z31.s
// CHECK-INST: ssublbt z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x88,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 88 df 45 <unknown>

test/MC/AArch64/SVE2/ssublt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
ssublt z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssublt z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssublt z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssublt z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssublt z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssublt z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssublt z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssublt z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
ssublt z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ssublt z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
ssublt z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ssublt z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ssublt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ssublt z0.h, z1.b, z2.b
// CHECK-INST: ssublt z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x14,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 14 42 45 <unknown>
ssublt z29.s, z30.h, z31.h
// CHECK-INST: ssublt z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x17,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 17 9f 45 <unknown>
ssublt z31.d, z31.s, z31.s
// CHECK-INST: ssublt z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x17,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 17 df 45 <unknown>

test/MC/AArch64/SVE2/ssubltb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
ssubltb z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssubltb z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssubltb z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssubltb z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssubltb z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssubltb z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssubltb z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssubltb z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
ssubltb z0.h, z1.b, z7.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ssubltb z0.h, z1.b, z7.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.h, p0/z, z7.h
ssubltb z0.h, z1.b, z7.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ssubltb z0.h, z1.b, z7.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ssubltb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ssubltb z0.h, z1.b, z31.b
// CHECK-INST: ssubltb z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x8c,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 8c 5f 45 <unknown>
ssubltb z0.s, z1.h, z31.h
// CHECK-INST: ssubltb z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x8c,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 8c 9f 45 <unknown>
ssubltb z0.d, z1.s, z31.s
// CHECK-INST: ssubltb z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x8c,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 8c df 45 <unknown>

test/MC/AArch64/SVE2/ssubwb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
ssubwb z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssubwb z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssubwb z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssubwb z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssubwb z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssubwb z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssubwb z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssubwb z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
ssubwb z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ssubwb z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
ssubwb z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ssubwb z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ssubwb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ssubwb z0.h, z1.h, z2.b
// CHECK-INST: ssubwb z0.h, z1.h, z2.b
// CHECK-ENCODING: [0x20,0x50,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 50 42 45 <unknown>
ssubwb z29.s, z30.s, z31.h
// CHECK-INST: ssubwb z29.s, z30.s, z31.h
// CHECK-ENCODING: [0xdd,0x53,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 53 9f 45 <unknown>
ssubwb z31.d, z31.d, z31.s
// CHECK-INST: ssubwb z31.d, z31.d, z31.s
// CHECK-ENCODING: [0xff,0x53,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 53 df 45 <unknown>

test/MC/AArch64/SVE2/ssubwt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
ssubwt z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssubwt z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssubwt z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssubwt z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssubwt z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssubwt z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ssubwt z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ssubwt z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
ssubwt z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ssubwt z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
ssubwt z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ssubwt z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ssubwt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ssubwt z0.h, z1.h, z2.b
// CHECK-INST: ssubwt z0.h, z1.h, z2.b
// CHECK-ENCODING: [0x20,0x54,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 54 42 45 <unknown>
ssubwt z29.s, z30.s, z31.h
// CHECK-INST: ssubwt z29.s, z30.s, z31.h
// CHECK-ENCODING: [0xdd,0x57,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 57 9f 45 <unknown>
ssubwt z31.d, z31.d, z31.s
// CHECK-INST: ssubwt z31.d, z31.d, z31.s
// CHECK-ENCODING: [0xff,0x57,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 57 df 45 <unknown>

test/MC/AArch64/SVE2/stnt1b-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid result type.
stnt1b { z0.b }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1b { z0.b }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1b { z0.h }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1b { z0.h }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid base vector.
stnt1b { z0.s }, p0, [z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1b { z0.s }, p0, [z0.b]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1b { z0.d }, p0, [z0.h]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1b { z0.d }, p0, [z0.h]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid offset type.
stnt1b { z0.d }, p0, [z0.d, z1.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1b { z0.d }, p0, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// restricted predicate has range [0, 7].
stnt1b { z27.d }, p8, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: stnt1b { z27.d }, p8, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
stnt1b { }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: stnt1b { }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1b { z0.d, z1.d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1b { z0.d, z1.d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1b { v0.2d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1b { v0.2d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
stnt1b { z0.d }, p0, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1b { z0.d }, p0, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
stnt1b { z0.s }, p0, [z0.s, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1b { z0.s }, p0, [z0.s, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/stnt1b.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
stnt1b z0.s, p0, [z1.s]
// CHECK-INST: stnt1b { z0.s }, p0, [z1.s]
// CHECK-ENCODING: [0x20,0x20,0x5f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 5f e4 <unknown>
stnt1b z31.s, p7, [z31.s, xzr]
// CHECK-INST: stnt1b { z31.s }, p7, [z31.s]
// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 5f e4 <unknown>
stnt1b z31.s, p7, [z31.s, x0]
// CHECK-INST: stnt1b { z31.s }, p7, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x3f,0x40,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 40 e4 <unknown>
stnt1b z0.d, p0, [z1.d]
// CHECK-INST: stnt1b { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x1f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 1f e4 <unknown>
stnt1b z31.d, p7, [z31.d, xzr]
// CHECK-INST: stnt1b { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 1f e4 <unknown>
stnt1b z31.d, p7, [z31.d, x0]
// CHECK-INST: stnt1b { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x00,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 00 e4 <unknown>
stnt1b { z0.s }, p0, [z1.s]
// CHECK-INST: stnt1b { z0.s }, p0, [z1.s]
// CHECK-ENCODING: [0x20,0x20,0x5f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 5f e4 <unknown>
stnt1b { z31.s }, p7, [z31.s, xzr]
// CHECK-INST: stnt1b { z31.s }, p7, [z31.s]
// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 5f e4 <unknown>
stnt1b { z31.s }, p7, [z31.s, x0]
// CHECK-INST: stnt1b { z31.s }, p7, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x3f,0x40,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 40 e4 <unknown>
stnt1b { z0.d }, p0, [z1.d]
// CHECK-INST: stnt1b { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x1f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 1f e4 <unknown>
stnt1b { z31.d }, p7, [z31.d, xzr]
// CHECK-INST: stnt1b { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 1f e4 <unknown>
stnt1b { z31.d }, p7, [z31.d, x0]
// CHECK-INST: stnt1b { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x00,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 00 e4 <unknown>

test/MC/AArch64/SVE2/stnt1d-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid result type.
stnt1d { z0.b }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1d { z0.b }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1d { z0.h }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1d { z0.h }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1d { z0.s }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1d { z0.s }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid base vector.
stnt1d { z0.d }, p0, [z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.b]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid offset type.
stnt1d { z0.d }, p0, [z0.d, z1.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// restricted predicate has range [0, 7].
stnt1d { z27.d }, p8, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: stnt1d { z27.d }, p8, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
stnt1d { }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: stnt1d { }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1d { z0.d, z1.d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1d { z0.d, z1.d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1d { v0.2d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1d { v0.2d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
stnt1d { z0.d }, p0, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
stnt1d { z0.d }, p0, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/stnt1d.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
stnt1d z0.d, p0, [z1.d]
// CHECK-INST: stnt1d { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x9f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 9f e5 <unknown>
stnt1d z31.d, p7, [z31.d, xzr]
// CHECK-INST: stnt1d { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 9f e5 <unknown>
stnt1d z31.d, p7, [z31.d, x0]
// CHECK-INST: stnt1d { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x80,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 80 e5 <unknown>
stnt1d { z0.d }, p0, [z1.d]
// CHECK-INST: stnt1d { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x9f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 9f e5 <unknown>
stnt1d { z31.d }, p7, [z31.d, xzr]
// CHECK-INST: stnt1d { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 9f e5 <unknown>
stnt1d { z31.d }, p7, [z31.d, x0]
// CHECK-INST: stnt1d { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x80,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 80 e5 <unknown>

test/MC/AArch64/SVE2/stnt1h-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid result type.
stnt1h { z0.b }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1h { z0.b }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1h { z0.h }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1h { z0.h }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid base vector.
stnt1h { z0.s }, p0, [z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1h { z0.s }, p0, [z0.b]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1h { z0.d }, p0, [z0.h]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1h { z0.d }, p0, [z0.h]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid offset type.
stnt1h { z0.d }, p0, [z0.d, z1.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1h { z0.d }, p0, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// restricted predicate has range [0, 7].
stnt1h { z27.d }, p8, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: stnt1h { z27.d }, p8, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
stnt1h { }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: stnt1h { }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1h { z0.d, z1.d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1h { z0.d, z1.d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1h { v0.2d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1h { v0.2d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
stnt1h { z0.d }, p0, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1h { z0.d }, p0, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
stnt1h { z0.s }, p0, [z0.s, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1h { z0.s }, p0, [z0.s, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/stnt1h.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
stnt1h z0.s, p0, [z1.s]
// CHECK-INST: stnt1h { z0.s }, p0, [z1.s]
// CHECK-ENCODING: [0x20,0x20,0xdf,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 df e4 <unknown>
stnt1h z31.s, p7, [z31.s, xzr]
// CHECK-INST: stnt1h { z31.s }, p7, [z31.s]
// CHECK-ENCODING: [0xff,0x3f,0xdf,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f df e4 <unknown>
stnt1h z31.s, p7, [z31.s, x0]
// CHECK-INST: stnt1h { z31.s }, p7, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x3f,0xc0,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f c0 e4 <unknown>
stnt1h z0.d, p0, [z1.d]
// CHECK-INST: stnt1h { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x9f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 9f e4 <unknown>
stnt1h z31.d, p7, [z31.d, xzr]
// CHECK-INST: stnt1h { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 9f e4 <unknown>
stnt1h z31.d, p7, [z31.d, x0]
// CHECK-INST: stnt1h { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x80,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 80 e4 <unknown>
stnt1h { z0.s }, p0, [z1.s]
// CHECK-INST: stnt1h { z0.s }, p0, [z1.s]
// CHECK-ENCODING: [0x20,0x20,0xdf,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 df e4 <unknown>
stnt1h { z31.s }, p7, [z31.s, xzr]
// CHECK-INST: stnt1h { z31.s }, p7, [z31.s]
// CHECK-ENCODING: [0xff,0x3f,0xdf,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f df e4 <unknown>
stnt1h { z31.s }, p7, [z31.s, x0]
// CHECK-INST: stnt1h { z31.s }, p7, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x3f,0xc0,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f c0 e4 <unknown>
stnt1h { z0.d }, p0, [z1.d]
// CHECK-INST: stnt1h { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x9f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 9f e4 <unknown>
stnt1h { z31.d }, p7, [z31.d, xzr]
// CHECK-INST: stnt1h { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 9f e4 <unknown>
stnt1h { z31.d }, p7, [z31.d, x0]
// CHECK-INST: stnt1h { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x80,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 80 e4 <unknown>

test/MC/AArch64/SVE2/stnt1w-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid result type.
stnt1w { z0.b }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1w { z0.b }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1w { z0.h }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1w { z0.h }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid base vector.
stnt1w { z0.s }, p0, [z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1w { z0.s }, p0, [z0.b]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1w { z0.d }, p0, [z0.h]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1w { z0.d }, p0, [z0.h]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid offset type.
stnt1w { z0.d }, p0, [z0.d, z1.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1w { z0.d }, p0, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// restricted predicate has range [0, 7].
stnt1w { z27.d }, p8, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: stnt1w { z27.d }, p8, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
stnt1w { }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: stnt1w { }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1w { z0.d, z1.d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1w { z0.d, z1.d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1w { v0.2d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1w { v0.2d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
stnt1w { z0.d }, p0, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1w { z0.d }, p0, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
stnt1w { z0.s }, p0, [z0.s, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1w { z0.s }, p0, [z0.s, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/stnt1w.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
stnt1w z0.s, p0, [z1.s]
// CHECK-INST: stnt1w { z0.s }, p0, [z1.s]
// CHECK-ENCODING: [0x20,0x20,0x5f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 5f e5 <unknown>
stnt1w z31.s, p7, [z31.s, xzr]
// CHECK-INST: stnt1w { z31.s }, p7, [z31.s]
// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 5f e5 <unknown>
stnt1w z31.s, p7, [z31.s, x0]
// CHECK-INST: stnt1w { z31.s }, p7, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x3f,0x40,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 40 e5 <unknown>
stnt1w z0.d, p0, [z1.d]
// CHECK-INST: stnt1w { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x1f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 1f e5 <unknown>
stnt1w z31.d, p7, [z31.d, xzr]
// CHECK-INST: stnt1w { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 1f e5 <unknown>
stnt1w z31.d, p7, [z31.d, x0]
// CHECK-INST: stnt1w { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x00,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 00 e5 <unknown>
stnt1w { z0.s }, p0, [z1.s]
// CHECK-INST: stnt1w { z0.s }, p0, [z1.s]
// CHECK-ENCODING: [0x20,0x20,0x5f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 5f e5 <unknown>
stnt1w { z31.s }, p7, [z31.s, xzr]
// CHECK-INST: stnt1w { z31.s }, p7, [z31.s]
// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 5f e5 <unknown>
stnt1w { z31.s }, p7, [z31.s, x0]
// CHECK-INST: stnt1w { z31.s }, p7, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x3f,0x40,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 40 e5 <unknown>
stnt1w { z0.d }, p0, [z1.d]
// CHECK-INST: stnt1w { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x1f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 1f e5 <unknown>
stnt1w { z31.d }, p7, [z31.d, xzr]
// CHECK-INST: stnt1w { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 1f e5 <unknown>
stnt1w { z31.d }, p7, [z31.d, x0]
// CHECK-INST: stnt1w { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x00,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 00 e5 <unknown>

test/MC/AArch64/SVE2/subhnb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
subhnb z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: subhnb z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subhnb z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: subhnb z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subhnb z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: subhnb z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subhnb z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: subhnb z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
subhnb z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: subhnb z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
subhnb z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: subhnb z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/subhnb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
subhnb z0.b, z1.h, z31.h
// CHECK-INST: subhnb z0.b, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x70,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 70 7f 45 <unknown>
subhnb z0.h, z1.s, z31.s
// CHECK-INST: subhnb z0.h, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x70,0xbf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 70 bf 45 <unknown>
subhnb z0.s, z1.d, z31.d
// CHECK-INST: subhnb z0.s, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x70,0xff,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 70 ff 45 <unknown>

test/MC/AArch64/SVE2/subhnt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
subhnt z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: subhnt z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subhnt z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: subhnt z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subhnt z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: subhnt z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subhnt z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: subhnt z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
subhnt z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: subhnt z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
subhnt z0.s, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: subhnt z0.s, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/subhnt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
subhnt z0.b, z1.h, z31.h
// CHECK-INST: subhnt z0.b, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x74,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 74 7f 45 <unknown>
subhnt z0.h, z1.s, z31.s
// CHECK-INST: subhnt z0.h, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x74,0xbf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 74 bf 45 <unknown>
subhnt z0.s, z1.d, z31.d
// CHECK-INST: subhnt z0.s, z1.d, z31.d
// CHECK-ENCODING: [0x20,0x74,0xff,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 74 ff 45 <unknown>

test/MC/AArch64/SVE2/suqadd-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
suqadd z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: suqadd z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
suqadd z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: suqadd z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
suqadd z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: suqadd z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
suqadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: suqadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/suqadd.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
suqadd z0.b, p0/m, z0.b, z1.b
// CHECK-INST: suqadd z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x1c,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 1c 44 <unknown>
suqadd z0.h, p0/m, z0.h, z1.h
// CHECK-INST: suqadd z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x5c,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 5c 44 <unknown>
suqadd z29.s, p7/m, z29.s, z30.s
// CHECK-INST: suqadd z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x9c,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 9c 44 <unknown>
suqadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: suqadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xdc,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f dc 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
suqadd z31.d, p0/m, z31.d, z30.d
// CHECK-INST: suqadd z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xdc,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 dc 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
suqadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: suqadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xdc,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f dc 44 <unknown>

test/MC/AArch64/SVE2/tbl-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
tbl z0.b, { z1.b, z2.b }, z3.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: tbl z0.b, { z1.b, z2.b }, z3.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
tbl z0.d, { }, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: tbl z0.d, { }, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
tbl z0.d, { z1.d, z2.d, z3.d }, z4.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: tbl z0.d, { z1.d, z2.d, z3.d }, z4.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
tbl z0.d, { z1.d, z2.b }, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
// CHECK-NEXT: tbl z0.d, { z1.d, z2.b }, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
tbl z0.d, { z1.d, z21.d }, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: tbl z0.d, { z1.d, z21.d }, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
tbl z0.d, { v0.2d, v1.2d }, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: tbl z0.d, { v0.2d, v1.2d }, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
tbl z31.d, { z30.d, z31.d }, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: tbl z31.d, { z30.d, z31.d }, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
tbl z31.d, { z30.d, z31.d }, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: tbl z31.d, { z30.d, z31.d }, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/tbl.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
tbl z28.b, { z29.b, z30.b }, z31.b
// CHECK-INST: tbl z28.b, { z29.b, z30.b }, z31.b
// CHECK-ENCODING: [0xbc,0x2b,0x3f,0x05]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bc 2b 3f 05 <unknown>
tbl z28.h, { z29.h, z30.h }, z31.h
// CHECK-INST: tbl z28.h, { z29.h, z30.h }, z31.h
// CHECK-ENCODING: [0xbc,0x2b,0x7f,0x05]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bc 2b 7f 05 <unknown>
tbl z28.s, { z29.s, z30.s }, z31.s
// CHECK-INST: tbl z28.s, { z29.s, z30.s }, z31.s
// CHECK-ENCODING: [0xbc,0x2b,0xbf,0x05]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bc 2b bf 05 <unknown>
tbl z28.d, { z29.d, z30.d }, z31.d
// CHECK-INST: tbl z28.d, { z29.d, z30.d }, z31.d
// CHECK-ENCODING: [0xbc,0x2b,0xff,0x05]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: bc 2b ff 05 <unknown>

test/MC/AArch64/SVE2/tbx-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
tbx z0.b, z1.b, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: tbx z0.b, z1.b, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
tbx z31.d, z31.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: tbx z31.d, z31.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
tbx z31.d, z31.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: tbx z31.d, z31.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/tbx.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
tbx z31.b, z31.b, z31.b
// CHECK-INST: tbx z31.b, z31.b, z31.b
// CHECK-ENCODING: [0xff,0x2f,0x3f,0x05]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 2f 3f 05 <unknown>
tbx z31.h, z31.h, z31.h
// CHECK-INST: tbx z31.h, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x2f,0x7f,0x05]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 2f 7f 05 <unknown>
tbx z31.s, z31.s, z31.s
// CHECK-INST: tbx z31.s, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x2f,0xbf,0x05]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 2f bf 05 <unknown>
tbx z31.d, z31.d, z31.d
// CHECK-INST: tbx z31.d, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x2f,0xff,0x05]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 2f ff 05 <unknown>

test/MC/AArch64/SVE2/uaba-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
uaba z0.b, z1.h, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaba z0.b, z1.h, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
uaba z0.d, z1.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uaba z0.d, z1.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uaba.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uaba z0.b, z1.b, z31.b
// CHECK-INST: uaba z0.b, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xfc,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 fc 1f 45 <unknown>
uaba z0.h, z1.h, z31.h
// CHECK-INST: uaba z0.h, z1.h, z31.h
// CHECK-ENCODING: [0x20,0xfc,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 fc 5f 45 <unknown>
uaba z0.s, z1.s, z31.s
// CHECK-INST: uaba z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xfc,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 fc 9f 45 <unknown>
uaba z0.d, z1.d, z31.d
// CHECK-INST: uaba z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xfc,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 fc df 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uaba z0.d, z1.d, z31.d
// CHECK-INST: uaba z0.d, z1.d, z31.d
// CHECK-ENCODING: [0x20,0xfc,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 fc df 45 <unknown>

test/MC/AArch64/SVE2/uabalb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
uabalb z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabalb z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uabalb z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabalb z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uabalb z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabalb z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uabalb z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabalb z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
uabalb z0.d, z1.s, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uabalb z0.d, z1.s, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uabalb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uabalb z0.h, z1.b, z31.b
// CHECK-INST: uabalb z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xc8,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c8 5f 45 <unknown>
uabalb z0.s, z1.h, z31.h
// CHECK-INST: uabalb z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0xc8,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c8 9f 45 <unknown>
uabalb z0.d, z1.s, z31.s
// CHECK-INST: uabalb z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xc8,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 c8 df 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
uabalb z21.d, z1.s, z31.s
// CHECK-INST: uabalb z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0xc8,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 c8 df 45 <unknown>

test/MC/AArch64/SVE2/uabalt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
uabalt z0.b, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabalt z0.b, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uabalt z0.h, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabalt z0.h, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uabalt z0.s, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabalt z0.s, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uabalt z0.d, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabalt z0.d, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
uabalt z0.d, z1.s, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: uabalt z0.d, z1.s, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uabalt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uabalt z0.h, z1.b, z31.b
// CHECK-INST: uabalt z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0xcc,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 cc 5f 45 <unknown>
uabalt z0.s, z1.h, z31.h
// CHECK-INST: uabalt z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0xcc,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 cc 9f 45 <unknown>
uabalt z0.d, z1.s, z31.s
// CHECK-INST: uabalt z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xcc,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 cc df 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
uabalt z21.d, z1.s, z31.s
// CHECK-INST: uabalt z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0xcc,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 cc df 45 <unknown>

test/MC/AArch64/SVE2/uabdlb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
uabdlb z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabdlb z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uabdlb z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabdlb z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uabdlb z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabdlb z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uabdlb z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabdlb z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
uabdlb z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uabdlb z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
uabdlb z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uabdlb z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uabdlb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uabdlb z0.h, z1.b, z2.b
// CHECK-INST: uabdlb z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x38,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 38 42 45 <unknown>
uabdlb z29.s, z30.h, z31.h
// CHECK-INST: uabdlb z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x3b,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 3b 9f 45 <unknown>
uabdlb z31.d, z31.s, z31.s
// CHECK-INST: uabdlb z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x3b,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3b df 45 <unknown>

test/MC/AArch64/SVE2/uabdlt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
uabdlt z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabdlt z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uabdlt z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabdlt z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uabdlt z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabdlt z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uabdlt z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uabdlt z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
uabdlt z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uabdlt z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
uabdlt z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uabdlt z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uabdlt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uabdlt z0.h, z1.b, z2.b
// CHECK-INST: uabdlt z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x3c,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 3c 42 45 <unknown>
uabdlt z29.s, z30.h, z31.h
// CHECK-INST: uabdlt z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x3f,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 3f 9f 45 <unknown>
uabdlt z31.d, z31.s, z31.s
// CHECK-INST: uabdlt z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x3f,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f df 45 <unknown>

test/MC/AArch64/SVE2/uadalp-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Element sizes must match
uadalp z0.b, p0/m, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uadalp z0.b, p0/m, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uadalp z0.h, p0/m, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uadalp z0.h, p0/m, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uadalp z0.s, p0/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uadalp z0.s, p0/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uadalp z0.d, p0/m, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uadalp z0.d, p0/m, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
uadalp z0.h, p8/m, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: uadalp z0.h, p8/m, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative movprfx tests
movprfx z31.s, p0/z, z6.s // element type of the source operand, rather than destination.
uadalp z31.d, p0/m, z30.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size
// CHECK-NEXT: uadalp z31.d, p0/m, z30.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uadalp.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uadalp z0.h, p0/m, z1.b
// CHECK-INST: uadalp z0.h, p0/m, z1.b
// CHECK-ENCODING: [0x20,0xa0,0x45,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 45 44 <unknown>
uadalp z29.s, p0/m, z30.h
// CHECK-INST: uadalp z29.s, p0/m, z30.h
// CHECK-ENCODING: [0xdd,0xa3,0x85,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd a3 85 44 <unknown>
uadalp z30.d, p7/m, z31.s
// CHECK-INST: uadalp z30.d, p7/m, z31.s
// CHECK-ENCODING: [0xfe,0xbf,0xc5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fe bf c5 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
uadalp z31.d, p0/m, z30.s
// CHECK-INST: uadalp z31.d, p0/m, z30.s
// CHECK-ENCODING: [0xdf,0xa3,0xc5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df a3 c5 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
uadalp z31.d, p0/m, z30.s
// CHECK-INST: uadalp z31.d, p0/m, z30.s
// CHECK-ENCODING: [0xdf,0xa3,0xc5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df a3 c5 44 <unknown>

test/MC/AArch64/SVE2/uaddlb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
uaddlb z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddlb z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uaddlb z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddlb z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uaddlb z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddlb z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uaddlb z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddlb z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
uaddlb z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uaddlb z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
uaddlb z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uaddlb z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uaddlb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uaddlb z0.h, z1.b, z2.b
// CHECK-INST: uaddlb z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x08,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 08 42 45 <unknown>
uaddlb z29.s, z30.h, z31.h
// CHECK-INST: uaddlb z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x0b,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 0b 9f 45 <unknown>
uaddlb z31.d, z31.s, z31.s
// CHECK-INST: uaddlb z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x0b,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 0b df 45 <unknown>

test/MC/AArch64/SVE2/uaddlt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
uaddlt z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddlt z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uaddlt z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddlt z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uaddlt z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddlt z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uaddlt z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddlt z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
uaddlt z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uaddlt z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
uaddlt z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uaddlt z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uaddlt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uaddlt z0.h, z1.b, z2.b
// CHECK-INST: uaddlt z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x0c,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 0c 42 45 <unknown>
uaddlt z29.s, z30.h, z31.h
// CHECK-INST: uaddlt z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x0f,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 0f 9f 45 <unknown>
uaddlt z31.d, z31.s, z31.s
// CHECK-INST: uaddlt z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x0f,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 0f df 45 <unknown>

test/MC/AArch64/SVE2/uaddwb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
uaddwb z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddwb z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uaddwb z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddwb z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uaddwb z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddwb z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uaddwb z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddwb z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
uaddwb z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uaddwb z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
uaddwb z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uaddwb z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uaddwb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uaddwb z0.h, z1.h, z2.b
// CHECK-INST: uaddwb z0.h, z1.h, z2.b
// CHECK-ENCODING: [0x20,0x48,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 48 42 45 <unknown>
uaddwb z29.s, z30.s, z31.h
// CHECK-INST: uaddwb z29.s, z30.s, z31.h
// CHECK-ENCODING: [0xdd,0x4b,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 4b 9f 45 <unknown>
uaddwb z31.d, z31.d, z31.s
// CHECK-INST: uaddwb z31.d, z31.d, z31.s
// CHECK-ENCODING: [0xff,0x4b,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 4b df 45 <unknown>

test/MC/AArch64/SVE2/uaddwt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
uaddwt z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddwt z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uaddwt z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddwt z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uaddwt z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddwt z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uaddwt z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uaddwt z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
uaddwt z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uaddwt z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
uaddwt z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uaddwt z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uaddwt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uaddwt z0.h, z1.h, z2.b
// CHECK-INST: uaddwt z0.h, z1.h, z2.b
// CHECK-ENCODING: [0x20,0x4c,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 4c 42 45 <unknown>
uaddwt z29.s, z30.s, z31.h
// CHECK-INST: uaddwt z29.s, z30.s, z31.h
// CHECK-ENCODING: [0xdd,0x4f,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 4f 9f 45 <unknown>
uaddwt z31.d, z31.d, z31.s
// CHECK-INST: uaddwt z31.d, z31.d, z31.s
// CHECK-ENCODING: [0xff,0x4f,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 4f df 45 <unknown>

test/MC/AArch64/SVE2/uhadd-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
uhadd z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: uhadd z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
uhadd z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uhadd z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uhadd z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uhadd z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
uhadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: uhadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uhadd.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uhadd z0.b, p0/m, z0.b, z1.b
// CHECK-INST: uhadd z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x11,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 11 44 <unknown>
uhadd z0.h, p0/m, z0.h, z1.h
// CHECK-INST: uhadd z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x51,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 51 44 <unknown>
uhadd z29.s, p7/m, z29.s, z30.s
// CHECK-INST: uhadd z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x91,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 91 44 <unknown>
uhadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uhadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd1,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d1 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
uhadd z31.d, p0/m, z31.d, z30.d
// CHECK-INST: uhadd z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xd1,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 d1 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
uhadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uhadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd1,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d1 44 <unknown>

test/MC/AArch64/SVE2/uhsub-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
uhsub z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: uhsub z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
uhsub z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uhsub z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uhsub z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uhsub z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
uhsub z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: uhsub z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uhsub.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uhsub z0.b, p0/m, z0.b, z1.b
// CHECK-INST: uhsub z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x13,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 13 44 <unknown>
uhsub z0.h, p0/m, z0.h, z1.h
// CHECK-INST: uhsub z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x53,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 53 44 <unknown>
uhsub z29.s, p7/m, z29.s, z30.s
// CHECK-INST: uhsub z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x93,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 93 44 <unknown>
uhsub z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uhsub z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd3,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d3 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
uhsub z31.d, p0/m, z31.d, z30.d
// CHECK-INST: uhsub z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xd3,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 d3 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
uhsub z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uhsub z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd3,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d3 44 <unknown>

test/MC/AArch64/SVE2/uhsubr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
uhsubr z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: uhsubr z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
uhsubr z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uhsubr z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uhsubr z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uhsubr z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
uhsubr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: uhsubr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uhsubr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uhsubr z0.b, p0/m, z0.b, z1.b
// CHECK-INST: uhsubr z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x17,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 17 44 <unknown>
uhsubr z0.h, p0/m, z0.h, z1.h
// CHECK-INST: uhsubr z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x57,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 57 44 <unknown>
uhsubr z29.s, p7/m, z29.s, z30.s
// CHECK-INST: uhsubr z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x97,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 97 44 <unknown>
uhsubr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uhsubr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d7 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
uhsubr z31.d, p0/m, z31.d, z30.d
// CHECK-INST: uhsubr z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xd7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 d7 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
uhsubr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uhsubr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d7 44 <unknown>

test/MC/AArch64/SVE2/umaxp-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
umaxp z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: umaxp z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
umaxp z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umaxp z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umaxp z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umaxp z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
umaxp z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: umaxp z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/umaxp.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
umaxp z0.b, p0/m, z0.b, z1.b
// CHECK-INST: umaxp z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0xa0,0x15,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 15 44 <unknown>
umaxp z0.h, p0/m, z0.h, z1.h
// CHECK-INST: umaxp z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0xa0,0x55,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 55 44 <unknown>
umaxp z29.s, p7/m, z29.s, z30.s
// CHECK-INST: umaxp z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0xbf,0x95,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd bf 95 44 <unknown>
umaxp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: umaxp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0xbf,0xd5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df bf d5 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
umaxp z31.d, p0/m, z31.d, z30.d
// CHECK-INST: umaxp z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0xa3,0xd5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df a3 d5 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
umaxp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: umaxp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0xbf,0xd5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df bf d5 44 <unknown>

test/MC/AArch64/SVE2/uminp-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
uminp z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: uminp z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
uminp z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uminp z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uminp z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uminp z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
uminp z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: uminp z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uminp.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uminp z0.b, p0/m, z0.b, z1.b
// CHECK-INST: uminp z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0xa0,0x17,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 17 44 <unknown>
uminp z0.h, p0/m, z0.h, z1.h
// CHECK-INST: uminp z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0xa0,0x57,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 a0 57 44 <unknown>
uminp z29.s, p7/m, z29.s, z30.s
// CHECK-INST: uminp z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0xbf,0x97,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd bf 97 44 <unknown>
uminp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uminp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0xbf,0xd7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df bf d7 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
uminp z31.d, p0/m, z31.d, z30.d
// CHECK-INST: uminp z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0xa3,0xd7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df a3 d7 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
uminp z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uminp z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0xbf,0xd7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df bf d7 44 <unknown>

test/MC/AArch64/SVE2/umlalb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
umlalb z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umlalb z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalb z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umlalb z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
umlalb z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: umlalb z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalb z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: umlalb z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalb z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: umlalb z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalb z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: umlalb z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
umlalb z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlalb z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalb z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlalb z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalb z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlalb z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalb z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlalb z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalb z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlalb z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalb z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlalb z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
umlalb z0.d, z1.s, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: umlalb z0.d, z1.s, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
umlalb z0.d, z1.s, z15.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: umlalb z0.d, z1.s, z15.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/umlalb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
umlalb z0.h, z1.b, z31.b
// CHECK-INST: umlalb z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x48,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 48 5f 44 <unknown>
umlalb z0.s, z1.h, z31.h
// CHECK-INST: umlalb z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x48,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 48 9f 44 <unknown>
umlalb z0.d, z1.s, z31.s
// CHECK-INST: umlalb z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x48,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 48 df 44 <unknown>
umlalb z0.s, z1.h, z7.h[7]
// CHECK-INST: umlalb z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0x98,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 98 bf 44 <unknown>
umlalb z0.d, z1.s, z15.s[1]
// CHECK-INST: umlalb z0.d, z1.s, z15.s[1]
// CHECK-ENCODING: [0x20,0x98,0xef,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 98 ef 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
umlalb z21.d, z1.s, z31.s
// CHECK-INST: umlalb z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0x48,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 48 df 44 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
umlalb z21.d, z10.s, z5.s[1]
// CHECK-INST: umlalb z21.d, z10.s, z5.s[1]
// CHECK-ENCODING: [0x55,0x99,0xe5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 55 99 e5 44 <unknown>

test/MC/AArch64/SVE2/umlalt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
umlalt z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umlalt z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalt z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umlalt z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
umlalt z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: umlalt z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalt z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: umlalt z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalt z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: umlalt z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalt z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: umlalt z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
umlalt z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlalt z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalt z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlalt z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalt z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlalt z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalt z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlalt z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalt z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlalt z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlalt z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlalt z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
umlalt z0.d, z1.s, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: umlalt z0.d, z1.s, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
umlalt z0.d, z1.s, z15.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: umlalt z0.d, z1.s, z15.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/umlalt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
umlalt z0.h, z1.b, z31.b
// CHECK-INST: umlalt z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x4c,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 4c 5f 44 <unknown>
umlalt z0.s, z1.h, z31.h
// CHECK-INST: umlalt z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x4c,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 4c 9f 44 <unknown>
umlalt z0.d, z1.s, z31.s
// CHECK-INST: umlalt z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x4c,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 4c df 44 <unknown>
umlalt z0.s, z1.h, z7.h[7]
// CHECK-INST: umlalt z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0x9c,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 9c bf 44 <unknown>
umlalt z0.d, z1.s, z15.s[1]
// CHECK-INST: umlalt z0.d, z1.s, z15.s[1]
// CHECK-ENCODING: [0x20,0x9c,0xef,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 9c ef 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
umlalt z21.d, z1.s, z31.s
// CHECK-INST: umlalt z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0x4c,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 4c df 44 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
umlalt z21.d, z10.s, z5.s[1]
// CHECK-INST: umlalt z21.d, z10.s, z5.s[1]
// CHECK-ENCODING: [0x55,0x9d,0xe5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 55 9d e5 44 <unknown>

test/MC/AArch64/SVE2/umlslb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
umlslb z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umlslb z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslb z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umlslb z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
umlslb z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: umlslb z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslb z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: umlslb z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslb z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: umlslb z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslb z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: umlslb z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
umlslb z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlslb z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslb z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlslb z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslb z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlslb z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslb z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlslb z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslb z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlslb z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslb z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlslb z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
umlslb z0.d, z1.s, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: umlslb z0.d, z1.s, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
umlslb z0.d, z1.s, z15.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: umlslb z0.d, z1.s, z15.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/umlslb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
umlslb z0.h, z1.b, z31.b
// CHECK-INST: umlslb z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x58,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 58 5f 44 <unknown>
umlslb z0.s, z1.h, z31.h
// CHECK-INST: umlslb z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x58,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 58 9f 44 <unknown>
umlslb z0.d, z1.s, z31.s
// CHECK-INST: umlslb z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x58,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 58 df 44 <unknown>
umlslb z0.s, z1.h, z7.h[7]
// CHECK-INST: umlslb z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0xb8,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 b8 bf 44 <unknown>
umlslb z0.d, z1.s, z15.s[1]
// CHECK-INST: umlslb z0.d, z1.s, z15.s[1]
// CHECK-ENCODING: [0x20,0xb8,0xef,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 b8 ef 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
umlslb z21.d, z1.s, z31.s
// CHECK-INST: umlslb z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0x58,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 58 df 44 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
umlslb z21.d, z10.s, z5.s[1]
// CHECK-INST: umlslb z21.d, z10.s, z5.s[1]
// CHECK-ENCODING: [0x55,0xb9,0xe5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 55 b9 e5 44 <unknown>

test/MC/AArch64/SVE2/umlslt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
umlslt z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umlslt z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslt z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umlslt z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
umlslt z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: umlslt z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslt z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: umlslt z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslt z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: umlslt z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslt z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: umlslt z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
umlslt z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlslt z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslt z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlslt z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslt z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlslt z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslt z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlslt z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslt z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlslt z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umlslt z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umlslt z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
umlslt z0.d, z1.s, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: umlslt z0.d, z1.s, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.d, p0/z, z7.d
umlslt z0.d, z1.s, z15.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: umlslt z0.d, z1.s, z15.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/umlslt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
umlslt z0.h, z1.b, z31.b
// CHECK-INST: umlslt z0.h, z1.b, z31.b
// CHECK-ENCODING: [0x20,0x5c,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 5c 5f 44 <unknown>
umlslt z0.s, z1.h, z31.h
// CHECK-INST: umlslt z0.s, z1.h, z31.h
// CHECK-ENCODING: [0x20,0x5c,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 5c 9f 44 <unknown>
umlslt z0.d, z1.s, z31.s
// CHECK-INST: umlslt z0.d, z1.s, z31.s
// CHECK-ENCODING: [0x20,0x5c,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 5c df 44 <unknown>
umlslt z0.s, z1.h, z7.h[7]
// CHECK-INST: umlslt z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0xbc,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 bc bf 44 <unknown>
umlslt z0.d, z1.s, z15.s[1]
// CHECK-INST: umlslt z0.d, z1.s, z15.s[1]
// CHECK-ENCODING: [0x20,0xbc,0xef,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 bc ef 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
umlslt z21.d, z1.s, z31.s
// CHECK-INST: umlslt z21.d, z1.s, z31.s
// CHECK-ENCODING: [0x35,0x5c,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 35 5c df 44 <unknown>
movprfx z21, z28
// CHECK-INST: movprfx z21, z28
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
umlslt z21.d, z10.s, z5.s[1]
// CHECK-INST: umlslt z21.d, z10.s, z5.s[1]
// CHECK-ENCODING: [0x55,0xbd,0xe5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 55 bd e5 44 <unknown>

test/MC/AArch64/SVE2/umulh-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
umulh z0.b, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umulh z0.b, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umulh z0.h, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umulh z0.h, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umulh z0.s, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umulh z0.s, z1.d, z2.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umulh z0.d, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umulh z0.d, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
umulh z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: umulh z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
umulh z0.d, z1.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: umulh z0.d, z1.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/umulh.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
umulh z0.b, z1.b, z2.b
// CHECK-INST: umulh z0.b, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x6c,0x22,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 6c 22 04 <unknown>
umulh z0.h, z1.h, z2.h
// CHECK-INST: umulh z0.h, z1.h, z2.h
// CHECK-ENCODING: [0x20,0x6c,0x62,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 6c 62 04 <unknown>
umulh z29.s, z30.s, z31.s
// CHECK-INST: umulh z29.s, z30.s, z31.s
// CHECK-ENCODING: [0xdd,0x6f,0xbf,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 6f bf 04 <unknown>
umulh z31.d, z31.d, z31.d
// CHECK-INST: umulh z31.d, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x6f,0xff,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 6f ff 04 <unknown>

test/MC/AArch64/SVE2/umullb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
umullb z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umullb z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullb z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umullb z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
umullb z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: umullb z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullb z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: umullb z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullb z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: umullb z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullb z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: umullb z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
umullb z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullb z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullb z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullb z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullb z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullb z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullb z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullb z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullb z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullb z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullb z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullb z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullb z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullb z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullb z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullb z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullb z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullb z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullb z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullb z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
umullb z31.d, z31.s, z15.s[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: umullb z31.d, z31.s, z15.s[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
umullb z31.d, z31.s, z15.s[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: umullb z31.d, z31.s, z15.s[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/umullb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
umullb z0.h, z1.b, z2.b
// CHECK-INST: umullb z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x78,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 78 42 45 <unknown>
umullb z29.s, z30.h, z31.h
// CHECK-INST: umullb z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x7b,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 7b 9f 45 <unknown>
umullb z31.d, z31.s, z31.s
// CHECK-INST: umullb z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x7b,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 7b df 45 <unknown>
umullb z0.s, z1.h, z7.h[7]
// CHECK-INST: umullb z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0xd8,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 d8 bf 44 <unknown>
umullb z0.d, z1.s, z15.s[1]
// CHECK-INST: umullb z0.d, z1.s, z15.s[1]
// CHECK-ENCODING: [0x20,0xd8,0xef,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 d8 ef 44 <unknown>

test/MC/AArch64/SVE2/umullt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// z register out of range for index
umullt z0.s, z1.h, z8.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umullt z0.s, z1.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullt z0.d, z1.s, z16.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umullt z0.d, z1.s, z16.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Index out of bounds
umullt z0.s, z1.h, z7.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: umullt z0.s, z1.h, z7.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullt z0.s, z1.h, z7.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: umullt z0.s, z1.h, z7.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullt z0.d, z1.s, z15.s[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: umullt z0.d, z1.s, z15.s[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullt z0.d, z1.s, z15.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: umullt z0.d, z1.s, z15.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
umullt z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullt z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullt z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullt z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullt z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullt z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullt z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullt z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullt z0.s, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullt z0.s, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullt z0.s, z1.s, z2.s[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullt z0.s, z1.s, z2.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullt z0.s, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullt z0.s, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullt z0.d, z1.b, z2.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullt z0.d, z1.b, z2.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullt z0.d, z1.h, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullt z0.d, z1.h, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umullt z0.d, z1.d, z2.d[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umullt z0.d, z1.d, z2.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
umullt z31.d, z31.s, z15.s[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: umullt z31.d, z31.s, z15.s[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
umullt z31.d, z31.s, z15.s[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: umullt z31.d, z31.s, z15.s[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/umullt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
umullt z0.h, z1.b, z2.b
// CHECK-INST: umullt z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x7c,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 7c 42 45 <unknown>
umullt z29.s, z30.h, z31.h
// CHECK-INST: umullt z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x7f,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 7f 9f 45 <unknown>
umullt z31.d, z31.s, z31.s
// CHECK-INST: umullt z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x7f,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 7f df 45 <unknown>
umullt z0.s, z1.h, z7.h[7]
// CHECK-INST: umullt z0.s, z1.h, z7.h[7]
// CHECK-ENCODING: [0x20,0xdc,0xbf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 dc bf 44 <unknown>
umullt z0.d, z1.s, z15.s[1]
// CHECK-INST: umullt z0.d, z1.s, z15.s[1]
// CHECK-ENCODING: [0x20,0xdc,0xef,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 dc ef 44 <unknown>

test/MC/AArch64/SVE2/uqadd-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
uqadd z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: uqadd z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
uqadd z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqadd z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqadd z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqadd z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
uqadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: uqadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uqadd.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uqadd z0.b, p0/m, z0.b, z1.b
// CHECK-INST: uqadd z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x19,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 19 44 <unknown>
uqadd z0.h, p0/m, z0.h, z1.h
// CHECK-INST: uqadd z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x59,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 59 44 <unknown>
uqadd z29.s, p7/m, z29.s, z30.s
// CHECK-INST: uqadd z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x99,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 99 44 <unknown>
uqadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uqadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd9,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d9 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
uqadd z31.d, p0/m, z31.d, z30.d
// CHECK-INST: uqadd z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xd9,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 d9 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
uqadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uqadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd9,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d9 44 <unknown>

test/MC/AArch64/SVE2/uqrshl-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
uqrshl z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: uqrshl z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
uqrshl z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqrshl z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshl z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqrshl z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
uqrshl z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: uqrshl z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uqrshl.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uqrshl z0.b, p0/m, z0.b, z1.b
// CHECK-INST: uqrshl z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x0b,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 0b 44 <unknown>
uqrshl z0.h, p0/m, z0.h, z1.h
// CHECK-INST: uqrshl z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x4b,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 4b 44 <unknown>
uqrshl z29.s, p7/m, z29.s, z30.s
// CHECK-INST: uqrshl z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x8b,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 8b 44 <unknown>
uqrshl z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uqrshl z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xcb,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f cb 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
uqrshl z31.d, p0/m, z31.d, z30.d
// CHECK-INST: uqrshl z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xcb,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 cb 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
uqrshl z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uqrshl z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xcb,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f cb 44 <unknown>

test/MC/AArch64/SVE2/uqrshlr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
uqrshlr z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: uqrshlr z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
uqrshlr z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqrshlr z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshlr z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqrshlr z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
uqrshlr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: uqrshlr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uqrshlr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uqrshlr z0.b, p0/m, z0.b, z1.b
// CHECK-INST: uqrshlr z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x0f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 0f 44 <unknown>
uqrshlr z0.h, p0/m, z0.h, z1.h
// CHECK-INST: uqrshlr z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x4f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 4f 44 <unknown>
uqrshlr z29.s, p7/m, z29.s, z30.s
// CHECK-INST: uqrshlr z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x8f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 8f 44 <unknown>
uqrshlr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uqrshlr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xcf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f cf 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
uqrshlr z31.d, p0/m, z31.d, z30.d
// CHECK-INST: uqrshlr z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xcf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 cf 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
uqrshlr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uqrshlr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xcf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f cf 44 <unknown>

test/MC/AArch64/SVE2/uqrshrnb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
uqrshrnb z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: uqrshrnb z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnb z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: uqrshrnb z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnb z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: uqrshrnb z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnb z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: uqrshrnb z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnb z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: uqrshrnb z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnb z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: uqrshrnb z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
uqrshrnb z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqrshrnb z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnb z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqrshrnb z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnb z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqrshrnb z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnb z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqrshrnb z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
uqrshrnb z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uqrshrnb z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uqrshrnb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uqrshrnb z0.b, z0.h, #1
// CHECK-INST: uqrshrnb z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x38,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 38 2f 45 <unknown>
uqrshrnb z31.b, z31.h, #8
// CHECK-INST: uqrshrnb z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x3b,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3b 28 45 <unknown>
uqrshrnb z0.h, z0.s, #1
// CHECK-INST: uqrshrnb z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x38,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 38 3f 45 <unknown>
uqrshrnb z31.h, z31.s, #16
// CHECK-INST: uqrshrnb z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x3b,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3b 30 45 <unknown>
uqrshrnb z0.s, z0.d, #1
// CHECK-INST: uqrshrnb z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x38,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 38 7f 45 <unknown>
uqrshrnb z31.s, z31.d, #32
// CHECK-INST: uqrshrnb z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x3b,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3b 60 45 <unknown>

test/MC/AArch64/SVE2/uqrshrnt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
uqrshrnt z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: uqrshrnt z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnt z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: uqrshrnt z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnt z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: uqrshrnt z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnt z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: uqrshrnt z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnt z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: uqrshrnt z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnt z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: uqrshrnt z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
uqrshrnt z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqrshrnt z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnt z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqrshrnt z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnt z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqrshrnt z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrnt z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqrshrnt z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
uqrshrnt z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uqrshrnt z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uqrshrnt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uqrshrnt z0.b, z0.h, #1
// CHECK-INST: uqrshrnt z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x3c,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 3c 2f 45 <unknown>
uqrshrnt z31.b, z31.h, #8
// CHECK-INST: uqrshrnt z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x3f,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 28 45 <unknown>
uqrshrnt z0.h, z0.s, #1
// CHECK-INST: uqrshrnt z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x3c,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 3c 3f 45 <unknown>
uqrshrnt z31.h, z31.s, #16
// CHECK-INST: uqrshrnt z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x3f,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 30 45 <unknown>
uqrshrnt z0.s, z0.d, #1
// CHECK-INST: uqrshrnt z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x3c,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 3c 7f 45 <unknown>
uqrshrnt z31.s, z31.d, #32
// CHECK-INST: uqrshrnt z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x3f,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 60 45 <unknown>

test/MC/AArch64/SVE2/uqshl-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
uqshl z0.b, p0/m, z0.b, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: uqshl z0.b, p0/m, z0.b, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshl z0.b, p0/m, z0.b, #8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: uqshl z0.b, p0/m, z0.b, #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshl z0.h, p0/m, z0.h, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: uqshl z0.h, p0/m, z0.h, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshl z0.h, p0/m, z0.h, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: uqshl z0.h, p0/m, z0.h, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshl z0.s, p0/m, z0.s, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: uqshl z0.s, p0/m, z0.s, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshl z0.s, p0/m, z0.s, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: uqshl z0.s, p0/m, z0.s, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshl z0.d, p0/m, z0.d, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
// CHECK-NEXT: uqshl z0.d, p0/m, z0.d, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshl z0.d, p0/m, z0.d, #64
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
// CHECK-NEXT: uqshl z0.d, p0/m, z0.d, #64
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
uqshl z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: uqshl z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshl z0.b, p0/m, z1.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: uqshl z0.b, p0/m, z1.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
uqshl z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqshl z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshl z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqshl z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshl z0.b, p0/m, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqshl z0.b, p0/m, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshl z0.d, p0/m, z0.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqshl z0.d, p0/m, z0.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
uqshl z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: uqshl z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshl z0.b, p8/m, z0.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: uqshl z0.b, p8/m, z0.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uqshl.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uqshl z0.b, p0/m, z0.b, z1.b
// CHECK-INST: uqshl z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x09,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 09 44 <unknown>
uqshl z0.h, p0/m, z0.h, z1.h
// CHECK-INST: uqshl z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x49,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 49 44 <unknown>
uqshl z29.s, p7/m, z29.s, z30.s
// CHECK-INST: uqshl z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x89,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 89 44 <unknown>
uqshl z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uqshl z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xc9,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f c9 44 <unknown>
uqshl z0.b, p0/m, z0.b, #0
// CHECK-INST: uqshl z0.b, p0/m, z0.b, #0
// CHECK-ENCODING: [0x00,0x81,0x07,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 81 07 04 <unknown>
uqshl z31.b, p0/m, z31.b, #7
// CHECK-INST: uqshl z31.b, p0/m, z31.b, #7
// CHECK-ENCODING: [0xff,0x81,0x07,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 81 07 04 <unknown>
uqshl z0.h, p0/m, z0.h, #0
// CHECK-INST: uqshl z0.h, p0/m, z0.h, #0
// CHECK-ENCODING: [0x00,0x82,0x07,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 82 07 04 <unknown>
uqshl z31.h, p0/m, z31.h, #15
// CHECK-INST: uqshl z31.h, p0/m, z31.h, #15
// CHECK-ENCODING: [0xff,0x83,0x07,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 07 04 <unknown>
uqshl z0.s, p0/m, z0.s, #0
// CHECK-INST: uqshl z0.s, p0/m, z0.s, #0
// CHECK-ENCODING: [0x00,0x80,0x47,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 80 47 04 <unknown>
uqshl z31.s, p0/m, z31.s, #31
// CHECK-INST: uqshl z31.s, p0/m, z31.s, #31
// CHECK-ENCODING: [0xff,0x83,0x47,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 47 04 <unknown>
uqshl z0.d, p0/m, z0.d, #0
// CHECK-INST: uqshl z0.d, p0/m, z0.d, #0
// CHECK-ENCODING: [0x00,0x80,0x87,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 80 87 04 <unknown>
uqshl z31.d, p0/m, z31.d, #63
// CHECK-INST: uqshl z31.d, p0/m, z31.d, #63
// CHECK-ENCODING: [0xff,0x83,0xc7,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 c7 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
uqshl z31.d, p0/m, z31.d, z30.d
// CHECK-INST: uqshl z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xc9,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 c9 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
uqshl z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uqshl z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xc9,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f c9 44 <unknown>
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
uqshl z31.d, p0/m, z31.d, #63
// CHECK-INST: uqshl z31.d, p0/m, z31.d, #63
// CHECK-ENCODING: [0xff,0x83,0xc7,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 c7 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
uqshl z31.d, p0/m, z31.d, #63
// CHECK-INST: uqshl z31.d, p0/m, z31.d, #63
// CHECK-ENCODING: [0xff,0x83,0xc7,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 83 c7 04 <unknown>

test/MC/AArch64/SVE2/uqshlr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
uqshlr z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: uqshlr z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
uqshlr z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqshlr z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshlr z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqshlr z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
uqshlr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: uqshlr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uqshlr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uqshlr z0.b, p0/m, z0.b, z1.b
// CHECK-INST: uqshlr z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x0d,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 0d 44 <unknown>
uqshlr z0.h, p0/m, z0.h, z1.h
// CHECK-INST: uqshlr z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x4d,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 4d 44 <unknown>
uqshlr z29.s, p7/m, z29.s, z30.s
// CHECK-INST: uqshlr z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x8d,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 8d 44 <unknown>
uqshlr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uqshlr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xcd,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f cd 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
uqshlr z31.d, p0/m, z31.d, z30.d
// CHECK-INST: uqshlr z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xcd,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 cd 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
uqshlr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uqshlr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xcd,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f cd 44 <unknown>

test/MC/AArch64/SVE2/uqshrnb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
uqshrnb z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: uqshrnb z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnb z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: uqshrnb z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnb z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: uqshrnb z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnb z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: uqshrnb z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnb z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: uqshrnb z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnb z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: uqshrnb z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
uqshrnb z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqshrnb z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnb z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqshrnb z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnb z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqshrnb z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnb z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqshrnb z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
uqshrnb z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uqshrnb z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uqshrnb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uqshrnb z0.b, z0.h, #1
// CHECK-INST: uqshrnb z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x30,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 30 2f 45 <unknown>
uqshrnb z31.b, z31.h, #8
// CHECK-INST: uqshrnb z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x33,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 33 28 45 <unknown>
uqshrnb z0.h, z0.s, #1
// CHECK-INST: uqshrnb z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x30,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 30 3f 45 <unknown>
uqshrnb z31.h, z31.s, #16
// CHECK-INST: uqshrnb z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x33,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 33 30 45 <unknown>
uqshrnb z0.s, z0.d, #1
// CHECK-INST: uqshrnb z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x30,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 30 7f 45 <unknown>
uqshrnb z31.s, z31.d, #32
// CHECK-INST: uqshrnb z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x33,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 33 60 45 <unknown>

test/MC/AArch64/SVE2/uqshrnt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
uqshrnt z30.b, z10.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: uqshrnt z30.b, z10.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnt z18.b, z27.h, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: uqshrnt z18.b, z27.h, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnt z26.h, z4.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: uqshrnt z26.h, z4.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnt z25.h, z10.s, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: uqshrnt z25.h, z10.s, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnt z17.s, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: uqshrnt z17.s, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnt z0.s, z15.d, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: uqshrnt z0.s, z15.d, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
uqshrnt z0.b, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqshrnt z0.b, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnt z0.h, z0.h, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqshrnt z0.h, z0.h, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnt z0.s, z0.s, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqshrnt z0.s, z0.s, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshrnt z0.d, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqshrnt z0.d, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
uqshrnt z31.s, z31.d, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uqshrnt z31.s, z31.d, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uqshrnt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uqshrnt z0.b, z0.h, #1
// CHECK-INST: uqshrnt z0.b, z0.h, #1
// CHECK-ENCODING: [0x00,0x34,0x2f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 34 2f 45 <unknown>
uqshrnt z31.b, z31.h, #8
// CHECK-INST: uqshrnt z31.b, z31.h, #8
// CHECK-ENCODING: [0xff,0x37,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 37 28 45 <unknown>
uqshrnt z0.h, z0.s, #1
// CHECK-INST: uqshrnt z0.h, z0.s, #1
// CHECK-ENCODING: [0x00,0x34,0x3f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 34 3f 45 <unknown>
uqshrnt z31.h, z31.s, #16
// CHECK-INST: uqshrnt z31.h, z31.s, #16
// CHECK-ENCODING: [0xff,0x37,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 37 30 45 <unknown>
uqshrnt z0.s, z0.d, #1
// CHECK-INST: uqshrnt z0.s, z0.d, #1
// CHECK-ENCODING: [0x00,0x34,0x7f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 34 7f 45 <unknown>
uqshrnt z31.s, z31.d, #32
// CHECK-INST: uqshrnt z31.s, z31.d, #32
// CHECK-ENCODING: [0xff,0x37,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 37 60 45 <unknown>

test/MC/AArch64/SVE2/uqsub-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
uqsub z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: uqsub z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
uqsub z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqsub z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqsub z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqsub z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
uqsub z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: uqsub z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uqsub.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uqsub z0.b, p0/m, z0.b, z1.b
// CHECK-INST: uqsub z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x1b,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 1b 44 <unknown>
uqsub z0.h, p0/m, z0.h, z1.h
// CHECK-INST: uqsub z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x5b,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 5b 44 <unknown>
uqsub z29.s, p7/m, z29.s, z30.s
// CHECK-INST: uqsub z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x9b,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 9b 44 <unknown>
uqsub z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uqsub z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xdb,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f db 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
uqsub z31.d, p0/m, z31.d, z30.d
// CHECK-INST: uqsub z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xdb,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 db 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
uqsub z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uqsub z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xdb,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f db 44 <unknown>

test/MC/AArch64/SVE2/uqsubr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
uqsubr z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: uqsubr z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
uqsubr z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqsubr z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqsubr z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqsubr z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
uqsubr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: uqsubr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uqsubr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uqsubr z0.b, p0/m, z0.b, z1.b
// CHECK-INST: uqsubr z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x1f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 1f 44 <unknown>
uqsubr z0.h, p0/m, z0.h, z1.h
// CHECK-INST: uqsubr z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x5f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 5f 44 <unknown>
uqsubr z29.s, p7/m, z29.s, z30.s
// CHECK-INST: uqsubr z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x9f,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 9f 44 <unknown>
uqsubr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uqsubr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f df 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
uqsubr z31.d, p0/m, z31.d, z30.d
// CHECK-INST: uqsubr z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 df 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
uqsubr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: uqsubr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xdf,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f df 44 <unknown>

test/MC/AArch64/SVE2/uqxtnb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
uqxtnb z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqxtnb z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqxtnb z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqxtnb z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqxtnb z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqxtnb z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqxtnb z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqxtnb z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
uqxtnb z0.s, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uqxtnb z0.s, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
uqxtnb z0.s, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uqxtnb z0.s, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uqxtnb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uqxtnb z0.b, z31.h
// CHECK-INST: uqxtnb z0.b, z31.h
// CHECK-ENCODING: [0xe0,0x4b,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 4b 28 45 <unknown>
uqxtnb z0.h, z31.s
// CHECK-INST: uqxtnb z0.h, z31.s
// CHECK-ENCODING: [0xe0,0x4b,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 4b 30 45 <unknown>
uqxtnb z0.s, z31.d
// CHECK-INST: uqxtnb z0.s, z31.d
// CHECK-ENCODING: [0xe0,0x4b,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 4b 60 45 <unknown>

test/MC/AArch64/SVE2/uqxtnt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
uqxtnt z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqxtnt z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqxtnt z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqxtnt z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqxtnt z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqxtnt z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqxtnt z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqxtnt z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0, z7
uqxtnt z0.s, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uqxtnt z0.s, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0.s, p0/z, z7.s
uqxtnt z0.s, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: uqxtnt z0.s, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uqxtnt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uqxtnt z0.b, z31.h
// CHECK-INST: uqxtnt z0.b, z31.h
// CHECK-ENCODING: [0xe0,0x4f,0x28,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 4f 28 45 <unknown>
uqxtnt z0.h, z31.s
// CHECK-INST: uqxtnt z0.h, z31.s
// CHECK-ENCODING: [0xe0,0x4f,0x30,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 4f 30 45 <unknown>
uqxtnt z0.s, z31.d
// CHECK-INST: uqxtnt z0.s, z31.d
// CHECK-ENCODING: [0xe0,0x4f,0x60,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 4f 60 45 <unknown>

test/MC/AArch64/SVE2/urecpe-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid predicate
urecpe z0.s, p8/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: urecpe z0.s, p8/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
urecpe z0.b, p7/m, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: urecpe z0.b, p7/m, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urecpe z0.h, p7/m, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: urecpe z0.h, p7/m, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urecpe z0.d, p7/m, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: urecpe z0.d, p7/m, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/urecpe.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
urecpe z31.s, p7/m, z31.s
// CHECK-INST: urecpe z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x80,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 80 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.s, p7/z, z6.s
// CHECK-INST: movprfx z4.s, p7/z, z6.s
// CHECK-ENCODING: [0xc4,0x3c,0x90,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c 90 04 <unknown>
urecpe z4.s, p7/m, z31.s
// CHECK-INST: urecpe z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x80,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 80 44 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
urecpe z4.s, p7/m, z31.s
// CHECK-INST: urecpe z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x80,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 80 44 <unknown>

test/MC/AArch64/SVE2/urhadd-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
urhadd z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: urhadd z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
urhadd z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: urhadd z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urhadd z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: urhadd z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
urhadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: urhadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/urhadd.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
urhadd z0.b, p0/m, z0.b, z1.b
// CHECK-INST: urhadd z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x15,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 15 44 <unknown>
urhadd z0.h, p0/m, z0.h, z1.h
// CHECK-INST: urhadd z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x55,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 55 44 <unknown>
urhadd z29.s, p7/m, z29.s, z30.s
// CHECK-INST: urhadd z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x95,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 95 44 <unknown>
urhadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: urhadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d5 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
urhadd z31.d, p0/m, z31.d, z30.d
// CHECK-INST: urhadd z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xd5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 d5 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
urhadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: urhadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xd5,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f d5 44 <unknown>

test/MC/AArch64/SVE2/urshl-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
urshl z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: urshl z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
urshl z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: urshl z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urshl z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: urshl z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
urshl z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: urshl z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/urshl.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
urshl z0.b, p0/m, z0.b, z1.b
// CHECK-INST: urshl z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x03,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 03 44 <unknown>
urshl z0.h, p0/m, z0.h, z1.h
// CHECK-INST: urshl z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x43,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 43 44 <unknown>
urshl z29.s, p7/m, z29.s, z30.s
// CHECK-INST: urshl z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x83,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 83 44 <unknown>
urshl z31.d, p7/m, z31.d, z30.d
// CHECK-INST: urshl z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xc3,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f c3 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
urshl z31.d, p0/m, z31.d, z30.d
// CHECK-INST: urshl z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xc3,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 c3 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
urshl z31.d, p7/m, z31.d, z30.d
// CHECK-INST: urshl z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xc3,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f c3 44 <unknown>

test/MC/AArch64/SVE2/urshlr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
urshlr z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: urshlr z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
urshlr z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: urshlr z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urshlr z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: urshlr z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
urshlr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: urshlr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/urshlr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
urshlr z0.b, p0/m, z0.b, z1.b
// CHECK-INST: urshlr z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x07,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 07 44 <unknown>
urshlr z0.h, p0/m, z0.h, z1.h
// CHECK-INST: urshlr z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x47,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 47 44 <unknown>
urshlr z29.s, p7/m, z29.s, z30.s
// CHECK-INST: urshlr z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x87,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 87 44 <unknown>
urshlr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: urshlr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xc7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f c7 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
urshlr z31.d, p0/m, z31.d, z30.d
// CHECK-INST: urshlr z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xc7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 c7 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
urshlr z31.d, p7/m, z31.d, z30.d
// CHECK-INST: urshlr z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xc7,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f c7 44 <unknown>

test/MC/AArch64/SVE2/urshr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
urshr z18.b, p0/m, z18.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: urshr z18.b, p0/m, z18.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urshr z1.b, p0/m, z1.b, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: urshr z1.b, p0/m, z1.b, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urshr z21.h, p0/m, z21.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: urshr z21.h, p0/m, z21.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urshr z14.h, p0/m, z14.h, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: urshr z14.h, p0/m, z14.h, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urshr z6.s, p0/m, z6.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: urshr z6.s, p0/m, z6.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urshr z23.s, p0/m, z23.s, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: urshr z23.s, p0/m, z23.s, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urshr z3.d, p0/m, z3.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: urshr z3.d, p0/m, z3.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urshr z25.d, p0/m, z25.d, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: urshr z25.d, p0/m, z25.d, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/urshr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
urshr z0.b, p0/m, z0.b, #1
// CHECK-INST: urshr z0.b, p0/m, z0.b, #1
// CHECK-ENCODING: [0xe0,0x81,0x0d,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 81 0d 04 <unknown>
urshr z31.b, p0/m, z31.b, #8
// CHECK-INST: urshr z31.b, p0/m, z31.b, #8
// CHECK-ENCODING: [0x1f,0x81,0x0d,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 81 0d 04 <unknown>
urshr z0.h, p0/m, z0.h, #1
// CHECK-INST: urshr z0.h, p0/m, z0.h, #1
// CHECK-ENCODING: [0xe0,0x83,0x0d,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 83 0d 04 <unknown>
urshr z31.h, p0/m, z31.h, #16
// CHECK-INST: urshr z31.h, p0/m, z31.h, #16
// CHECK-ENCODING: [0x1f,0x82,0x0d,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 82 0d 04 <unknown>
urshr z0.s, p0/m, z0.s, #1
// CHECK-INST: urshr z0.s, p0/m, z0.s, #1
// CHECK-ENCODING: [0xe0,0x83,0x4d,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 83 4d 04 <unknown>
urshr z31.s, p0/m, z31.s, #32
// CHECK-INST: urshr z31.s, p0/m, z31.s, #32
// CHECK-ENCODING: [0x1f,0x80,0x4d,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 80 4d 04 <unknown>
urshr z0.d, p0/m, z0.d, #1
// CHECK-INST: urshr z0.d, p0/m, z0.d, #1
// CHECK-ENCODING: [0xe0,0x83,0xcd,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e0 83 cd 04 <unknown>
urshr z31.d, p0/m, z31.d, #64
// CHECK-INST: urshr z31.d, p0/m, z31.d, #64
// CHECK-ENCODING: [0x1f,0x80,0x8d,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 80 8d 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
urshr z31.d, p0/m, z31.d, #64
// CHECK-INST: urshr z31.d, p0/m, z31.d, #64
// CHECK-ENCODING: [0x1f,0x80,0x8d,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 80 8d 04 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
urshr z31.d, p0/m, z31.d, #64
// CHECK-INST: urshr z31.d, p0/m, z31.d, #64
// CHECK-ENCODING: [0x1f,0x80,0x8d,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 80 8d 04 <unknown>

test/MC/AArch64/SVE2/ursqrte-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid predicate
ursqrte z0.s, p8/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ursqrte z0.s, p8/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
ursqrte z0.b, p7/m, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ursqrte z0.b, p7/m, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ursqrte z0.h, p7/m, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ursqrte z0.h, p7/m, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ursqrte z0.d, p7/m, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ursqrte z0.d, p7/m, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ursqrte.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ursqrte z31.s, p7/m, z31.s
// CHECK-INST: ursqrte z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x81,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 81 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.s, p7/z, z6.s
// CHECK-INST: movprfx z4.s, p7/z, z6.s
// CHECK-ENCODING: [0xc4,0x3c,0x90,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c 90 04 <unknown>
ursqrte z4.s, p7/m, z31.s
// CHECK-INST: ursqrte z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x81,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 81 44 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
ursqrte z4.s, p7/m, z31.s
// CHECK-INST: ursqrte z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x81,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 81 44 <unknown>

test/MC/AArch64/SVE2/ursra-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
ursra z30.b, z10.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: ursra z30.b, z10.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ursra z18.b, z27.b, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: ursra z18.b, z27.b, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ursra z26.h, z4.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: ursra z26.h, z4.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ursra z25.h, z10.h, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: ursra z25.h, z10.h, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ursra z17.s, z0.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: ursra z17.s, z0.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ursra z0.s, z15.s, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: ursra z0.s, z15.s, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ursra z4.d, z13.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: ursra z4.d, z13.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ursra z26.d, z26.d, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: ursra z26.d, z26.d, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
ursra z0.b, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ursra z0.b, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
ursra z0.d, z1.d, #64
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: ursra z0.d, z1.d, #64
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ursra.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ursra z0.b, z0.b, #1
// CHECK-INST: ursra z0.b, z0.b, #1
// CHECK-ENCODING: [0x00,0xec,0x0f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 ec 0f 45 <unknown>
ursra z31.b, z31.b, #8
// CHECK-INST: ursra z31.b, z31.b, #8
// CHECK-ENCODING: [0xff,0xef,0x08,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff ef 08 45 <unknown>
ursra z0.h, z0.h, #1
// CHECK-INST: ursra z0.h, z0.h, #1
// CHECK-ENCODING: [0x00,0xec,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 ec 1f 45 <unknown>
ursra z31.h, z31.h, #16
// CHECK-INST: ursra z31.h, z31.h, #16
// CHECK-ENCODING: [0xff,0xef,0x10,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff ef 10 45 <unknown>
ursra z0.s, z0.s, #1
// CHECK-INST: ursra z0.s, z0.s, #1
// CHECK-ENCODING: [0x00,0xec,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 ec 5f 45 <unknown>
ursra z31.s, z31.s, #32
// CHECK-INST: ursra z31.s, z31.s, #32
// CHECK-ENCODING: [0xff,0xef,0x40,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff ef 40 45 <unknown>
ursra z0.d, z0.d, #1
// CHECK-INST: ursra z0.d, z0.d, #1
// CHECK-ENCODING: [0x00,0xec,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 ec df 45 <unknown>
ursra z31.d, z31.d, #64
// CHECK-INST: ursra z31.d, z31.d, #64
// CHECK-ENCODING: [0xff,0xef,0x80,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff ef 80 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
ursra z0.d, z1.d, #1
// CHECK-INST: ursra z0.d, z1.d, #1
// CHECK-ENCODING: [0x20,0xec,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 ec df 45 <unknown>

test/MC/AArch64/SVE2/ushllb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
ushllb z18.h, z28.b, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: ushllb z18.h, z28.b, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllb z1.h, z9.b, #8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: ushllb z1.h, z9.b, #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllb z21.s, z2.h, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: ushllb z21.s, z2.h, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllb z14.s, z30.h, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: ushllb z14.s, z30.h, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllb z6.d, z12.s, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: ushllb z6.d, z12.s, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllb z23.d, z19.s, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: ushllb z23.d, z19.s, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
ushllb z0.b, z0.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ushllb z0.b, z0.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllb z0.h, z0.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ushllb z0.h, z0.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllb z0.s, z0.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ushllb z0.s, z0.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllb z0.d, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ushllb z0.d, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
ushllb z31.d, z31.s, #31
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ushllb z31.d, z31.s, #31
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.d, p0/m, z6.d
ushllb z31.d, z31.s, #31
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ushllb z31.d, z31.s, #31
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ushllb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ushllb z0.h, z0.b, #0
// CHECK-INST: ushllb z0.h, z0.b, #0
// CHECK-ENCODING: [0x00,0xa8,0x08,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 a8 08 45 <unknown>
ushllb z31.h, z31.b, #7
// CHECK-INST: ushllb z31.h, z31.b, #7
// CHECK-ENCODING: [0xff,0xab,0x0f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff ab 0f 45 <unknown>
ushllb z0.s, z0.h, #0
// CHECK-INST: ushllb z0.s, z0.h, #0
// CHECK-ENCODING: [0x00,0xa8,0x10,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 a8 10 45 <unknown>
ushllb z31.s, z31.h, #15
// CHECK-INST: ushllb z31.s, z31.h, #15
// CHECK-ENCODING: [0xff,0xab,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff ab 1f 45 <unknown>
ushllb z0.d, z0.s, #0
// CHECK-INST: ushllb z0.d, z0.s, #0
// CHECK-ENCODING: [0x00,0xa8,0x40,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 a8 40 45 <unknown>
ushllb z31.d, z31.s, #31
// CHECK-INST: ushllb z31.d, z31.s, #31
// CHECK-ENCODING: [0xff,0xab,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff ab 5f 45 <unknown>

test/MC/AArch64/SVE2/ushllt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
ushllt z18.h, z28.b, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: ushllt z18.h, z28.b, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllt z1.h, z9.b, #8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
// CHECK-NEXT: ushllt z1.h, z9.b, #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllt z21.s, z2.h, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: ushllt z21.s, z2.h, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllt z14.s, z30.h, #16
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
// CHECK-NEXT: ushllt z14.s, z30.h, #16
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllt z6.d, z12.s, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: ushllt z6.d, z12.s, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllt z23.d, z19.s, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
// CHECK-NEXT: ushllt z23.d, z19.s, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid element width
ushllt z0.b, z0.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ushllt z0.b, z0.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllt z0.h, z0.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ushllt z0.h, z0.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllt z0.s, z0.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ushllt z0.s, z0.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ushllt z0.d, z0.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ushllt z0.d, z0.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6
ushllt z31.d, z31.s, #31
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ushllt z31.d, z31.s, #31
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31.d, p0/m, z6.d
ushllt z31.d, z31.s, #31
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ushllt z31.d, z31.s, #31
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ushllt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ushllt z0.h, z0.b, #0
// CHECK-INST: ushllt z0.h, z0.b, #0
// CHECK-ENCODING: [0x00,0xac,0x08,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 ac 08 45 <unknown>
ushllt z31.h, z31.b, #7
// CHECK-INST: ushllt z31.h, z31.b, #7
// CHECK-ENCODING: [0xff,0xaf,0x0f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff af 0f 45 <unknown>
ushllt z0.s, z0.h, #0
// CHECK-INST: ushllt z0.s, z0.h, #0
// CHECK-ENCODING: [0x00,0xac,0x10,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 ac 10 45 <unknown>
ushllt z31.s, z31.h, #15
// CHECK-INST: ushllt z31.s, z31.h, #15
// CHECK-ENCODING: [0xff,0xaf,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff af 1f 45 <unknown>
ushllt z0.d, z0.s, #0
// CHECK-INST: ushllt z0.d, z0.s, #0
// CHECK-ENCODING: [0x00,0xac,0x40,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 ac 40 45 <unknown>
ushllt z31.d, z31.s, #31
// CHECK-INST: ushllt z31.d, z31.s, #31
// CHECK-ENCODING: [0xff,0xaf,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff af 5f 45 <unknown>

test/MC/AArch64/SVE2/usqadd-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
usqadd z0.b, p0/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: usqadd z0.b, p0/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
usqadd z0.b, p0/m, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usqadd z0.b, p0/m, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usqadd z0.b, p0/m, z0.b, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usqadd z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
usqadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: usqadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/usqadd.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
usqadd z0.b, p0/m, z0.b, z1.b
// CHECK-INST: usqadd z0.b, p0/m, z0.b, z1.b
// CHECK-ENCODING: [0x20,0x80,0x1d,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 1d 44 <unknown>
usqadd z0.h, p0/m, z0.h, z1.h
// CHECK-INST: usqadd z0.h, p0/m, z0.h, z1.h
// CHECK-ENCODING: [0x20,0x80,0x5d,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 80 5d 44 <unknown>
usqadd z29.s, p7/m, z29.s, z30.s
// CHECK-INST: usqadd z29.s, p7/m, z29.s, z30.s
// CHECK-ENCODING: [0xdd,0x9f,0x9d,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 9f 9d 44 <unknown>
usqadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: usqadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xdd,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f dd 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31.d, p0/z, z6.d
// CHECK-INST: movprfx z31.d, p0/z, z6.d
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
usqadd z31.d, p0/m, z31.d, z30.d
// CHECK-INST: usqadd z31.d, p0/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x83,0xdd,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 83 dd 44 <unknown>
movprfx z31, z6
// CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
usqadd z31.d, p7/m, z31.d, z30.d
// CHECK-INST: usqadd z31.d, p7/m, z31.d, z30.d
// CHECK-ENCODING: [0xdf,0x9f,0xdd,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 9f dd 44 <unknown>

test/MC/AArch64/SVE2/usra-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
usra z30.b, z10.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: usra z30.b, z10.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usra z18.b, z27.b, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: usra z18.b, z27.b, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usra z26.h, z4.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: usra z26.h, z4.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usra z25.h, z10.h, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: usra z25.h, z10.h, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usra z17.s, z0.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: usra z17.s, z0.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usra z0.s, z15.s, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: usra z0.s, z15.s, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usra z4.d, z13.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: usra z4.d, z13.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usra z26.d, z26.d, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: usra z26.d, z26.d, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
usra z0.b, z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usra z0.b, z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
usra z0.d, z1.d, #64
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: usra z0.d, z1.d, #64
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/usra.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
usra z0.b, z0.b, #1
// CHECK-INST: usra z0.b, z0.b, #1
// CHECK-ENCODING: [0x00,0xe4,0x0f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 e4 0f 45 <unknown>
usra z31.b, z31.b, #8
// CHECK-INST: usra z31.b, z31.b, #8
// CHECK-ENCODING: [0xff,0xe7,0x08,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff e7 08 45 <unknown>
usra z0.h, z0.h, #1
// CHECK-INST: usra z0.h, z0.h, #1
// CHECK-ENCODING: [0x00,0xe4,0x1f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 e4 1f 45 <unknown>
usra z31.h, z31.h, #16
// CHECK-INST: usra z31.h, z31.h, #16
// CHECK-ENCODING: [0xff,0xe7,0x10,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff e7 10 45 <unknown>
usra z0.s, z0.s, #1
// CHECK-INST: usra z0.s, z0.s, #1
// CHECK-ENCODING: [0x00,0xe4,0x5f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 e4 5f 45 <unknown>
usra z31.s, z31.s, #32
// CHECK-INST: usra z31.s, z31.s, #32
// CHECK-ENCODING: [0xff,0xe7,0x40,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff e7 40 45 <unknown>
usra z0.d, z0.d, #1
// CHECK-INST: usra z0.d, z0.d, #1
// CHECK-ENCODING: [0x00,0xe4,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 e4 df 45 <unknown>
usra z31.d, z31.d, #64
// CHECK-INST: usra z31.d, z31.d, #64
// CHECK-ENCODING: [0xff,0xe7,0x80,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff e7 80 45 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z0, z7
// CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
usra z0.d, z1.d, #1
// CHECK-INST: usra z0.d, z1.d, #1
// CHECK-ENCODING: [0x20,0xe4,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 e4 df 45 <unknown>

test/MC/AArch64/SVE2/usublb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
usublb z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usublb z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usublb z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usublb z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usublb z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usublb z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usublb z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usublb z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
usublb z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: usublb z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
usublb z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: usublb z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/usublb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
usublb z0.h, z1.b, z2.b
// CHECK-INST: usublb z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x18,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 18 42 45 <unknown>
usublb z29.s, z30.h, z31.h
// CHECK-INST: usublb z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x1b,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 1b 9f 45 <unknown>
usublb z31.d, z31.s, z31.s
// CHECK-INST: usublb z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x1b,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 1b df 45 <unknown>

test/MC/AArch64/SVE2/usublt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
usublt z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usublt z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usublt z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usublt z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usublt z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usublt z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usublt z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usublt z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
usublt z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: usublt z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
usublt z0.d, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: usublt z0.d, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/usublt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
usublt z0.h, z1.b, z2.b
// CHECK-INST: usublt z0.h, z1.b, z2.b
// CHECK-ENCODING: [0x20,0x1c,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 1c 42 45 <unknown>
usublt z29.s, z30.h, z31.h
// CHECK-INST: usublt z29.s, z30.h, z31.h
// CHECK-ENCODING: [0xdd,0x1f,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 1f 9f 45 <unknown>
usublt z31.d, z31.s, z31.s
// CHECK-INST: usublt z31.d, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x1f,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 1f df 45 <unknown>

test/MC/AArch64/SVE2/usubwb-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
usubwb z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usubwb z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usubwb z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usubwb z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usubwb z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usubwb z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usubwb z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usubwb z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
usubwb z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: usubwb z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
usubwb z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: usubwb z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/usubwb.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
usubwb z0.h, z1.h, z2.b
// CHECK-INST: usubwb z0.h, z1.h, z2.b
// CHECK-ENCODING: [0x20,0x58,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 58 42 45 <unknown>
usubwb z29.s, z30.s, z31.h
// CHECK-INST: usubwb z29.s, z30.s, z31.h
// CHECK-ENCODING: [0xdd,0x5b,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 5b 9f 45 <unknown>
usubwb z31.d, z31.d, z31.s
// CHECK-INST: usubwb z31.d, z31.d, z31.s
// CHECK-ENCODING: [0xff,0x5b,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 5b df 45 <unknown>

test/MC/AArch64/SVE2/usubwt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid element width
usubwt z0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usubwt z0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usubwt z0.h, z0.h, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usubwt z0.h, z0.h, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usubwt z0.s, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usubwt z0.s, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usubwt z0.d, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: usubwt z0.d, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d
usubwt z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: usubwt z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z31, z6
usubwt z0.d, z1.d, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: usubwt z0.d, z1.d, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/usubwt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
usubwt z0.h, z1.h, z2.b
// CHECK-INST: usubwt z0.h, z1.h, z2.b
// CHECK-ENCODING: [0x20,0x5c,0x42,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 5c 42 45 <unknown>
usubwt z29.s, z30.s, z31.h
// CHECK-INST: usubwt z29.s, z30.s, z31.h
// CHECK-ENCODING: [0xdd,0x5f,0x9f,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: dd 5f 9f 45 <unknown>
usubwt z31.d, z31.d, z31.s
// CHECK-INST: usubwt z31.d, z31.d, z31.s
// CHECK-ENCODING: [0xff,0x5f,0xdf,0x45]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 5f df 45 <unknown>

test/MC/AArch64/SVE2/whilege-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid scalar registers
whilege p15.b, xzr, sp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilege p15.b, xzr, sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilege p15.b, xzr, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilege p15.b, xzr, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilege p15.b, w0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilege p15.b, w0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate
whilege p15, w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
// CHECK-NEXT: whilege p15, w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/whilege.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
whilege p15.b, xzr, x0
// CHECK-INST: whilege p15.b, xzr, x0
// CHECK-ENCODING: [0xef,0x13,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ef 13 20 25 <unknown>
whilege p15.b, x0, xzr
// CHECK-INST: whilege p15.b, x0, xzr
// CHECK-ENCODING: [0x0f,0x10,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 10 3f 25 <unknown>
whilege p15.b, wzr, w0
// CHECK-INST: whilege p15.b, wzr, w0
// CHECK-ENCODING: [0xef,0x03,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ef 03 20 25 <unknown>
whilege p15.b, w0, wzr
// CHECK-INST: whilege p15.b, w0, wzr
// CHECK-ENCODING: [0x0f,0x00,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 00 3f 25 <unknown>
whilege p15.h, x0, xzr
// CHECK-INST: whilege p15.h, x0, xzr
// CHECK-ENCODING: [0x0f,0x10,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 10 7f 25 <unknown>
whilege p15.h, w0, wzr
// CHECK-INST: whilege p15.h, w0, wzr
// CHECK-ENCODING: [0x0f,0x00,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 00 7f 25 <unknown>
whilege p15.s, x0, xzr
// CHECK-INST: whilege p15.s, x0, xzr
// CHECK-ENCODING: [0x0f,0x10,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 10 bf 25 <unknown>
whilege p15.s, w0, wzr
// CHECK-INST: whilege p15.s, w0, wzr
// CHECK-ENCODING: [0x0f,0x00,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 00 bf 25 <unknown>
whilege p15.d, w0, wzr
// CHECK-INST: whilege p15.d, w0, wzr
// CHECK-ENCODING: [0x0f,0x00,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 00 ff 25 <unknown>
whilege p15.d, x0, xzr
// CHECK-INST: whilege p15.d, x0, xzr
// CHECK-ENCODING: [0x0f,0x10,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 10 ff 25 <unknown>

test/MC/AArch64/SVE2/whilegt-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid scalar registers
whilegt p15.b, xzr, sp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilegt p15.b, xzr, sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilegt p15.b, xzr, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilegt p15.b, xzr, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilegt p15.b, w0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilegt p15.b, w0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate
whilegt p15, w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
// CHECK-NEXT: whilegt p15, w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/whilegt.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
whilegt p15.b, xzr, x0
// CHECK-INST: whilegt p15.b, xzr, x0
// CHECK-ENCODING: [0xff,0x13,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 13 20 25 <unknown>
whilegt p15.b, x0, xzr
// CHECK-INST: whilegt p15.b, x0, xzr
// CHECK-ENCODING: [0x1f,0x10,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 10 3f 25 <unknown>
whilegt p15.b, wzr, w0
// CHECK-INST: whilegt p15.b, wzr, w0
// CHECK-ENCODING: [0xff,0x03,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 03 20 25 <unknown>
whilegt p15.b, w0, wzr
// CHECK-INST: whilegt p15.b, w0, wzr
// CHECK-ENCODING: [0x1f,0x00,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 00 3f 25 <unknown>
whilegt p15.h, x0, xzr
// CHECK-INST: whilegt p15.h, x0, xzr
// CHECK-ENCODING: [0x1f,0x10,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 10 7f 25 <unknown>
whilegt p15.h, w0, wzr
// CHECK-INST: whilegt p15.h, w0, wzr
// CHECK-ENCODING: [0x1f,0x00,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 00 7f 25 <unknown>
whilegt p15.s, x0, xzr
// CHECK-INST: whilegt p15.s, x0, xzr
// CHECK-ENCODING: [0x1f,0x10,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 10 bf 25 <unknown>
whilegt p15.s, w0, wzr
// CHECK-INST: whilegt p15.s, w0, wzr
// CHECK-ENCODING: [0x1f,0x00,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 00 bf 25 <unknown>
whilegt p15.d, w0, wzr
// CHECK-INST: whilegt p15.d, w0, wzr
// CHECK-ENCODING: [0x1f,0x00,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 00 ff 25 <unknown>
whilegt p15.d, x0, xzr
// CHECK-INST: whilegt p15.d, x0, xzr
// CHECK-ENCODING: [0x1f,0x10,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 10 ff 25 <unknown>

test/MC/AArch64/SVE2/whilehi-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid scalar registers
whilehi p15.b, xzr, sp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilehi p15.b, xzr, sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilehi p15.b, xzr, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilehi p15.b, xzr, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilehi p15.b, w0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilehi p15.b, w0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate
whilehi p15, w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
// CHECK-NEXT: whilehi p15, w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/whilehi.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
whilehi p15.b, xzr, x0
// CHECK-INST: whilehi p15.b, xzr, x0
// CHECK-ENCODING: [0xff,0x1b,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 1b 20 25 <unknown>
whilehi p15.b, x0, xzr
// CHECK-INST: whilehi p15.b, x0, xzr
// CHECK-ENCODING: [0x1f,0x18,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 18 3f 25 <unknown>
whilehi p15.b, wzr, w0
// CHECK-INST: whilehi p15.b, wzr, w0
// CHECK-ENCODING: [0xff,0x0b,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 0b 20 25 <unknown>
whilehi p15.b, w0, wzr
// CHECK-INST: whilehi p15.b, w0, wzr
// CHECK-ENCODING: [0x1f,0x08,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 08 3f 25 <unknown>
whilehi p15.h, x0, xzr
// CHECK-INST: whilehi p15.h, x0, xzr
// CHECK-ENCODING: [0x1f,0x18,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 18 7f 25 <unknown>
whilehi p15.h, w0, wzr
// CHECK-INST: whilehi p15.h, w0, wzr
// CHECK-ENCODING: [0x1f,0x08,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 08 7f 25 <unknown>
whilehi p15.s, x0, xzr
// CHECK-INST: whilehi p15.s, x0, xzr
// CHECK-ENCODING: [0x1f,0x18,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 18 bf 25 <unknown>
whilehi p15.s, w0, wzr
// CHECK-INST: whilehi p15.s, w0, wzr
// CHECK-ENCODING: [0x1f,0x08,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 08 bf 25 <unknown>
whilehi p15.d, w0, wzr
// CHECK-INST: whilehi p15.d, w0, wzr
// CHECK-ENCODING: [0x1f,0x08,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 08 ff 25 <unknown>
whilehi p15.d, x0, xzr
// CHECK-INST: whilehi p15.d, x0, xzr
// CHECK-ENCODING: [0x1f,0x18,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 1f 18 ff 25 <unknown>

test/MC/AArch64/SVE2/whilehs-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid scalar registers
whilehs p15.b, xzr, sp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilehs p15.b, xzr, sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilehs p15.b, xzr, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilehs p15.b, xzr, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilehs p15.b, w0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilehs p15.b, w0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate
whilehs p15, w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
// CHECK-NEXT: whilehs p15, w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/whilehs.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
whilehs p15.b, xzr, x0
// CHECK-INST: whilehs p15.b, xzr, x0
// CHECK-ENCODING: [0xef,0x1b,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ef 1b 20 25 <unknown>
whilehs p15.b, x0, xzr
// CHECK-INST: whilehs p15.b, x0, xzr
// CHECK-ENCODING: [0x0f,0x18,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 18 3f 25 <unknown>
whilehs p15.b, wzr, w0
// CHECK-INST: whilehs p15.b, wzr, w0
// CHECK-ENCODING: [0xef,0x0b,0x20,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ef 0b 20 25 <unknown>
whilehs p15.b, w0, wzr
// CHECK-INST: whilehs p15.b, w0, wzr
// CHECK-ENCODING: [0x0f,0x08,0x3f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 08 3f 25 <unknown>
whilehs p15.h, x0, xzr
// CHECK-INST: whilehs p15.h, x0, xzr
// CHECK-ENCODING: [0x0f,0x18,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 18 7f 25 <unknown>
whilehs p15.h, w0, wzr
// CHECK-INST: whilehs p15.h, w0, wzr
// CHECK-ENCODING: [0x0f,0x08,0x7f,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 08 7f 25 <unknown>
whilehs p15.s, x0, xzr
// CHECK-INST: whilehs p15.s, x0, xzr
// CHECK-ENCODING: [0x0f,0x18,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 18 bf 25 <unknown>
whilehs p15.s, w0, wzr
// CHECK-INST: whilehs p15.s, w0, wzr
// CHECK-ENCODING: [0x0f,0x08,0xbf,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 08 bf 25 <unknown>
whilehs p15.d, w0, wzr
// CHECK-INST: whilehs p15.d, w0, wzr
// CHECK-ENCODING: [0x0f,0x08,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 08 ff 25 <unknown>
whilehs p15.d, x0, xzr
// CHECK-INST: whilehs p15.d, x0, xzr
// CHECK-ENCODING: [0x0f,0x18,0xff,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 0f 18 ff 25 <unknown>

test/MC/AArch64/SVE2/whilerw-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid scalar registers
whilerw p15.b, xzr, sp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilerw p15.b, xzr, sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilerw p15.b, xzr, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilerw p15.b, xzr, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilerw p15.b, w0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilerw p15.b, w0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilerw p15.b, w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilerw p15.b, w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/whilerw.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
whilerw p15.b, x30, x30
// CHECK-INST: whilerw p15.b, x30, x30
// CHECK-ENCODING: [0xdf,0x33,0x3e,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 33 3e 25 <unknown>
whilerw p15.h, x30, x30
// CHECK-INST: whilerw p15.h, x30, x30
// CHECK-ENCODING: [0xdf,0x33,0x7e,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 33 7e 25 <unknown>
whilerw p15.s, x30, x30
// CHECK-INST: whilerw p15.s, x30, x30
// CHECK-ENCODING: [0xdf,0x33,0xbe,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 33 be 25 <unknown>
whilerw p15.d, x30, x30
// CHECK-INST: whilerw p15.d, x30, x30
// CHECK-ENCODING: [0xdf,0x33,0xfe,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 33 fe 25 <unknown>

test/MC/AArch64/SVE2/whilewr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid scalar registers
whilewr p15.b, xzr, sp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilewr p15.b, xzr, sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilewr p15.b, xzr, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilewr p15.b, xzr, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilewr p15.b, w0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilewr p15.b, w0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilewr p15.b, w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilewr p15.b, w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/whilewr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
whilewr p15.b, x30, x30
// CHECK-INST: whilewr p15.b, x30, x30
// CHECK-ENCODING: [0xcf,0x33,0x3e,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: cf 33 3e 25 <unknown>
whilewr p15.h, x30, x30
// CHECK-INST: whilewr p15.h, x30, x30
// CHECK-ENCODING: [0xcf,0x33,0x7e,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: cf 33 7e 25 <unknown>
whilewr p15.s, x30, x30
// CHECK-INST: whilewr p15.s, x30, x30
// CHECK-ENCODING: [0xcf,0x33,0xbe,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: cf 33 be 25 <unknown>
whilewr p15.d, x30, x30
// CHECK-INST: whilewr p15.d, x30, x30
// CHECK-ENCODING: [0xcf,0x33,0xfe,0x25]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: cf 33 fe 25 <unknown>

test/MC/AArch64/SVE2/xar-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
xar z30.b, z30.b, z10.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: xar z30.b, z30.b, z10.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
xar z18.b, z18.b, z27.b, #9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
// CHECK-NEXT: xar z18.b, z18.b, z27.b, #9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
xar z26.h, z26.h, z4.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: xar z26.h, z26.h, z4.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
xar z25.h, z25.h, z10.h, #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: xar z25.h, z25.h, z10.h, #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
xar z17.s, z17.s, z0.s, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: xar z17.s, z17.s, z0.s, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
xar z0.s, z0.s, z15.s, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
// CHECK-NEXT: xar z0.s, z0.s, z15.s, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
xar z4.d, z4.d, z13.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: xar z4.d, z4.d, z13.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
xar z26.d, z26.d, z26.d, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: xar z26.d, z26.d, z26.d, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Element sizes must match
xar z0.b, z0.b , z0.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: xar z0.b, z0.b , z0.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
xar z0.d, z0.d, z1.d, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: xar z0.d, z0.d, z1.d, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/xar.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
xar z0.b, z0.b, z1.b, #1
// CHECK-INST: xar z0.b, z0.b, z1.b, #1
// CHECK-ENCODING: [0x20,0x34,0x2f,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 34 2f 04 <unknown>
xar z31.b, z31.b, z30.b, #8
// CHECK-INST: xar z31.b, z31.b, z30.b, #8
// CHECK-ENCODING: [0xdf,0x37,0x28,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 37 28 04 <unknown>
xar z0.h, z0.h, z1.h, #1
// CHECK-INST: xar z0.h, z0.h, z1.h, #1
// CHECK-ENCODING: [0x20,0x34,0x3f,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 34 3f 04 <unknown>
xar z31.h, z31.h, z30.h, #16
// CHECK-INST: xar z31.h, z31.h, z30.h, #16
// CHECK-ENCODING: [0xdf,0x37,0x30,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 37 30 04 <unknown>
xar z0.s, z0.s, z1.s, #1
// CHECK-INST: xar z0.s, z0.s, z1.s, #1
// CHECK-ENCODING: [0x20,0x34,0x7f,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 34 7f 04 <unknown>
xar z31.s, z31.s, z30.s, #32
// CHECK-INST: xar z31.s, z31.s, z30.s, #32
// CHECK-ENCODING: [0xdf,0x37,0x60,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 37 60 04 <unknown>
xar z0.d, z0.d, z1.d, #1
// CHECK-INST: xar z0.d, z0.d, z1.d, #1
// CHECK-ENCODING: [0x20,0x34,0xff,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 34 ff 04 <unknown>
xar z31.d, z31.d, z30.d, #64
// CHECK-INST: xar z31.d, z31.d, z30.d, #64
// CHECK-ENCODING: [0xdf,0x37,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 37 a0 04 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z31, z7
// CHECK-INST: movprfx z31, z7
// CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bc 20 04 <unknown>
xar z31.d, z31.d, z30.d, #64
// CHECK-INST: xar z31.d, z31.d, z30.d, #64
// CHECK-ENCODING: [0xdf,0x37,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: df 37 a0 04 <unknown>

unittests/Support/TargetParserTest.cpp

Context not available.
AArch64::AEK_FP16 | AArch64::AEK_PROFILE | AArch64::AEK_FP16 | AArch64::AEK_PROFILE |
AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RAS | AArch64::AEK_LSE |
AArch64::AEK_RDM | AArch64::AEK_SVE | AArch64::AEK_RDM | AArch64::AEK_SVE |
AArch64::AEK_DOTPROD | AArch64::AEK_RCPC | AArch64::AEK_SVE2 | AArch64::AEK_DOTPROD |
AArch64::AEK_FP16FML; AArch64::AEK_RCPC | AArch64::AEK_FP16FML;
for (unsigned i = 0; i <= Extensions; i++) for (unsigned i = 0; i <= Extensions; i++)
EXPECT_TRUE(i == 0 ? !AArch64::getExtensionFeatures(i, Features) EXPECT_TRUE(i == 0 ? !AArch64::getExtensionFeatures(i, Features)
Context not available.
{"lse", "nolse", "+lse", "-lse"}, {"lse", "nolse", "+lse", "-lse"},
{"rdm", "nordm", "+rdm", "-rdm"}, {"rdm", "nordm", "+rdm", "-rdm"},
{"sve", "nosve", "+sve", "-sve"}, {"sve", "nosve", "+sve", "-sve"},
{"sve2", "nosve2", "+sve2", "-sve2"},
{"sve2-aes", "nosve2-aes", "+sve2-aes",
"-sve2-aes"},
{"sve2-sm4", "nosve2-sm4", "+sve2-sm4",
"-sve2-sm4"},
{"sve2-sha3", "nosve2-sha3", "+sve2-sha3",
"-sve2-sha3"},
{"bitperm", "nobitperm", "+bitperm", "-bitperm"},
{"dotprod", "nodotprod", "+dotprod", "-dotprod"}, {"dotprod", "nodotprod", "+dotprod", "-dotprod"},
{"rcpc", "norcpc", "+rcpc", "-rcpc" }, {"rcpc", "norcpc", "+rcpc", "-rcpc" },
{"rng", "norng", "+rand", "-rand"}, {"rng", "norng", "+rand", "-rand"},
Context not available.