[CodeGenPrepare] Don't split the store if it is volatile

[steven.zhang]

Summary

We shouldn't split the store when it is volatile.

[dmgreen]

Hello. I feel like this splitting just shouldn't be done for volatile stores.

[steven.zhang]

In D61169#1481670, @dmgreen wrote:

Hello. I feel like this splitting just shouldn't be done for volatile stores.

Good point. Address the comments.

[dmgreen]

Looks like there is similar code in DAGCombiner that may need a volatile check too, if you search for isMultiStoresCheaperThanBitsMerge.

llvm/test/CodeGen/PowerPC/splitstore-check-volatile.ll

4

You could just make this an opt test, running the codegenprepare pass.

[steven.zhang]

Use opt instead of llc to do the check.

[dmgreen]

This LGTM.

Like I said, you may also want to look into doing the same thing for the code in DAGCombiner.

llvm/lib/CodeGen/CodeGenPrepare.cpp

if (DL.getTypeStoreSizeInBits(StoreType) != DL.getTypeSizeInBits(StoreType) ||
     return false;
 
   unsigned HalfValBitSize = DL.getTypeSizeInBits(StoreType) / 2;
   Type *SplitStoreType = Type::getIntNTy(SI.getContext(), HalfValBitSize);
   if (DL.getTypeStoreSizeInBits(SplitStoreType) !=
       DL.getTypeSizeInBits(SplitStoreType))
     return false;
 
+  // Don't split the store if it is volatile.
+  if (SI.isVolatile())
+    return false;
+
   // Match the following patterns:
   // (store (or (zext LValue to i64),
   //            (shl (zext HValue to i64), 32)), HalfValBitSize)
   //  or
   // (store (or (shl (zext HValue to i64), 32)), HalfValBitSize)
   //            (zext LValue to i64),
   // Expect both operands of OR and the first operand of SHL have only
   // one use.

llvm/test/CodeGen/PowerPC/splitstore-check-volatile.ll

+; Test that CodeGenPrepare respect the volatile flag when splitting a store.
+;
+; RUN: opt -S -codegenprepare -force-split-store < %s  | FileCheck %s
+
+define void @fun(i16* %Src, i16* %Dst) {
+; CHECK: store volatile i16 %8, i16* %Dst 
+  %1 = load i16, i16* %Src
+  %2 = trunc i16 %1 to i8
+  %3 = lshr i16 %1, 8
+  %4 = trunc i16 %3 to i8
+  %5 = zext i8 %2 to i16
+  %6 = zext i8 %4 to i16
+  %7 = shl nuw i16 %6, 8
+  %8 = or i16 %7, %5
+  store volatile i16 %8, i16* %Dst
+  ret void
+}