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[ARM] Add v4f16 and v8f16 types to the CallingConv
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Authored by dnsampaio on Apr 15 2019, 10:00 AM.

Details

Summary

The Procedure Call Standard for the Arm Architecture
states that float16x4_t and float16x8_t behave just
as uint16x4_t and uint16x8_t for argument passing.
This patch adds the fp16 vectors to the
ARMCallingConv.td file.

Diff Detail

Repository
rL LLVM

Event Timeline

dnsampaio created this revision.Apr 15 2019, 10:00 AM
dnsampaio updated this revision to Diff 195349.Apr 16 2019, 3:57 AM
  • Added tests
dnsampaio updated this revision to Diff 195353.Apr 16 2019, 4:25 AM
  • Added big-endian tests
dnsampaio edited reviewers, added: ostannard; removed: olista01.Apr 16 2019, 4:26 AM
dnsampaio updated this revision to Diff 195709.Apr 18 2019, 3:30 AM

Fixed duplicates

ostannard added inline comments.Apr 18 2019, 4:58 AM
test/CodeGen/ARM/fp16-vector-argument.ll
6 ↗(On Diff #195709)

This is only testing the soft-float calling convention, we should also test hard-float. We should also cover multiple vector arguments, including enough arguments that some must be passed on the stack.

dnsampaio updated this revision to Diff 196421.Apr 24 2019, 4:31 AM

Tests updated

  • Added:
    • hard-float calling convention
    • bit-endian tests to be activated by D60618
ostannard added inline comments.Apr 25 2019, 2:14 AM
test/CodeGen/ARM/fp16-vector-argument.ll
31 ↗(On Diff #196421)

This test is labelled as hard-float, but is passing the vector argument in GPRs. I suspect that this is because the APCS calling convention doesn't support hard-float. Actually, i think you could remove all of the tests for APCS to simplify this file, because it's a very old calling convention, which was superseded by AAPCS a long time ago, and it's unlikely to ever be used with v8.2A.

dnsampaio updated this revision to Diff 196657.Apr 25 2019, 9:31 AM
dnsampaio marked an inline comment as done.
  • removed old apcs
This revision is now accepted and ready to land.Apr 29 2019, 2:34 AM
This revision was automatically updated to reflect the committed changes.
RKSimon added inline comments.
llvm/trunk/lib/Target/ARM/ARMCallingConv.td
168

@dnsampaio @ostannard This introduces duplicate v4f16/v8f16 types which is causing PVS Studio warnings:

ARMGenCallingConv.inc	63	err	V501 There are identical sub-expressions 'LocVT == MVT::v4f16' to the left and to the right of the '||' operator.
ARMGenCallingConv.inc	74	err	V501 There are identical sub-expressions 'LocVT == MVT::v8f16' to the left and to the right of the '||' operator.
ARMGenCallingConv.inc	235	err	V501 There are identical sub-expressions 'LocVT == MVT::v4f16' to the left and to the right of the '||' operator.
ARMGenCallingConv.inc	246	err	V501 There are identical sub-expressions 'LocVT == MVT::v8f16' to the left and to the right of the '||' operator.
ARMGenCallingConv.inc	605	err	V501 There are identical sub-expressions 'LocVT == MVT::v4f16' to the left and to the right of the '||' operator.
ARMGenCallingConv.inc	616	err	V501 There are identical sub-expressions 'LocVT == MVT::v8f16' to the left and to the right of the '||' operator.
ARMGenCallingConv.inc	710	err	V501 There are identical sub-expressions 'LocVT == MVT::v4f16' to the left and to the right of the '||' operator.
ARMGenCallingConv.inc	721	err	V501 There are identical sub-expressions 'LocVT == MVT::v8f16' to the left and to the right of the '||' operator.

Thanks @RKSimon, will remove the 8 duplicates.