[ARM] Add v4f16 and v8f16 types to the CallingConv

[dnsampaio]

Summary

The Procedure Call Standard for the Arm Architecture
states that float16x4_t and float16x8_t behave just
as uint16x4_t and uint16x8_t for argument passing.
This patch adds the fp16 vectors to the
ARMCallingConv.td file.

[ostannard]

Tests?

[dnsampaio]

• Added tests

[dnsampaio]

• Added big-endian tests

[dnsampaio]

Fixed duplicates

[ostannard]

test/CodeGen/ARM/fp16-vector-argument.ll

6 ↗

(On Diff #195709)

This is only testing the soft-float calling convention, we should also test hard-float. We should also cover multiple vector arguments, including enough arguments that some must be passed on the stack.

[dnsampaio]

Tests updated

• Added:
  • hard-float calling convention
  • bit-endian tests to be activated by D60618

[ostannard]

test/CodeGen/ARM/fp16-vector-argument.ll

31 ↗

(On Diff #196421)

This test is labelled as hard-float, but is passing the vector argument in GPRs. I suspect that this is because the APCS calling convention doesn't support hard-float. Actually, i think you could remove all of the tests for APCS to simplify this file, because it's a very old calling convention, which was superseded by AAPCS a long time ago, and it's unlikely to ever be used with v8.2A.

[dnsampaio]

• removed old apcs

[ostannard]

LGTM

[RKSimon]

llvm/trunk/lib/Target/ARM/ARMCallingConv.td

168

@dnsampaio @ostannard This introduces duplicate v4f16/v8f16 types which is causing PVS Studio warnings:

ARMGenCallingConv.inc	63	err	V501 There are identical sub-expressions 'LocVT == MVT::v4f16' to the left and to the right of the '||' operator.
ARMGenCallingConv.inc	74	err	V501 There are identical sub-expressions 'LocVT == MVT::v8f16' to the left and to the right of the '||' operator.
ARMGenCallingConv.inc	235	err	V501 There are identical sub-expressions 'LocVT == MVT::v4f16' to the left and to the right of the '||' operator.
ARMGenCallingConv.inc	246	err	V501 There are identical sub-expressions 'LocVT == MVT::v8f16' to the left and to the right of the '||' operator.
ARMGenCallingConv.inc	605	err	V501 There are identical sub-expressions 'LocVT == MVT::v4f16' to the left and to the right of the '||' operator.
ARMGenCallingConv.inc	616	err	V501 There are identical sub-expressions 'LocVT == MVT::v8f16' to the left and to the right of the '||' operator.
ARMGenCallingConv.inc	710	err	V501 There are identical sub-expressions 'LocVT == MVT::v4f16' to the left and to the right of the '||' operator.
ARMGenCallingConv.inc	721	err	V501 There are identical sub-expressions 'LocVT == MVT::v8f16' to the left and to the right of the '||' operator.

[dnsampaio]

Thanks @RKSimon, will remove the 8 duplicates.

llvm/trunk/lib/Target/ARM/ARMCallingConv.td

def CC_ARM_APCS : CallingConv<[
 
   // Pass SwiftSelf in a callee saved register.
   CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
 
   // A SwiftError is passed in R8.
   CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
 
   // Handle all vector types as either f64 or v2f64.
-  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
+  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
 
   // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
   CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
 
   CCIfType<[f32], CCBitConvertToType<i32>>,
   CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
 
   CCIfType<[i32], CCAssignToStack<4, 4>>,
   CCIfType<[f64], CCAssignToStack<8, 4>>,
   CCIfType<[v2f64], CCAssignToStack<16, 4>>
 ]>;
 
 let Entry = 1 in
 def RetCC_ARM_APCS : CallingConv<[
   CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
   CCIfType<[f32], CCBitConvertToType<i32>>,
 
   // Pass SwiftSelf in a callee saved register.
   CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
 
   // A SwiftError is returned in R8.
   CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
 
   // Handle all vector types as either f64 or v2f64.
-  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
+  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
 
   CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
 
   CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
   CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
 ]>;
 
 //===----------------------------------------------------------------------===//
 // ARM APCS Calling Convention for FastCC (when VFP2 or later is available)
 //===----------------------------------------------------------------------===//
 let Entry = 1 in
 def FastCC_ARM_APCS : CallingConv<[
   // Handle all vector types as either f64 or v2f64.
-  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
+  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
 
   CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
   CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
   CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
                                  S9, S10, S11, S12, S13, S14, S15]>>,
 
   // CPRCs may be allocated to co-processor registers or the stack - they
   // may never be allocated to core registers. 
   CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
   CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
   CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
 
   CCDelegateTo<CC_ARM_APCS>
 ]>;
 
 let Entry = 1 in
 def RetFastCC_ARM_APCS : CallingConv<[
   // Handle all vector types as either f64 or v2f64.
-  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
+  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
 
   CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
   CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
   CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
                                  S9, S10, S11, S12, S13, S14, S15]>>,
   CCDelegateTo<RetCC_ARM_APCS>
 ]>;
 
 //===----------------------------------------------------------------------===//
 // ARM APCS Calling Convention for GHC
 //===----------------------------------------------------------------------===//
 
 let Entry = 1 in
 def CC_ARM_APCS_GHC : CallingConv<[
   // Handle all vector types as either f64 or v2f64.
-  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
+  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
 
   CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
   CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
   CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
 
   // Promote i8/i16 arguments to i32.
   CCIfType<[i8, i16], CCPromoteToType<i32>>,
 

 def CC_ARM_AAPCS : CallingConv<[
   // Handles byval parameters.
   CCIfByVal<CCPassByVal<4, 4>>,
 
   // The 'nest' parameter, if any, is passed in R12.
   CCIfNest<CCAssignToReg<[R12]>>,
 
   // Handle all vector types as either f64 or v2f64.
-  CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfType<[v1i64, v2i32, v4i16, v4f16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
+  CCIfType<[v2i64, v4i32, v8i16, v8f16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
 
   // Pass SwiftSelf in a callee saved register.
   CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
 
   // A SwiftError is passed in R8.
   CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
 
   CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
   CCIfType<[f32], CCBitConvertToType<i32>>,
   CCDelegateTo<CC_ARM_AAPCS_Common>
 ]>;
 
 let Entry = 1 in
 def RetCC_ARM_AAPCS : CallingConv<[
   // Handle all vector types as either f64 or v2f64.
-  CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v8f16,v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfType<[v1i64, v2i32, v4i16, v4f16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
+  CCIfType<[v2i64, v4i32, v8i16, v8f16, v8f16,v16i8, v4f32], CCBitConvertToType<v2f64>>,
 
   // Pass SwiftSelf in a callee saved register.
   CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
 
   // A SwiftError is returned in R8.
   CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
 
   CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
   CCIfType<[f32], CCBitConvertToType<i32>>,
 
   CCDelegateTo<RetCC_ARM_AAPCS_Common>
 ]>;
 
 //===----------------------------------------------------------------------===//
 // ARM AAPCS-VFP (EABI) Calling Convention
 // Also used for FastCC (when VFP2 or later is available)
 //===----------------------------------------------------------------------===//
 
 let Entry = 1 in
 def CC_ARM_AAPCS_VFP : CallingConv<[
   // Handles byval parameters.
   CCIfByVal<CCPassByVal<4, 4>>,
 
   // Handle all vector types as either f64 or v2f64.
-  CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfType<[v1i64, v2i32, v4i16, v4f16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
+  CCIfType<[v2i64, v4i32, v8i16, v8f16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
 
   // Pass SwiftSelf in a callee saved register.
   CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
 
   // A SwiftError is passed in R8.
   CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
 
   // HFAs are passed in a contiguous block of registers, or on the stack
   CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_Aggregate">>,
 
   CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
   CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
   CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
                                  S9, S10, S11, S12, S13, S14, S15]>>,
   CCDelegateTo<CC_ARM_AAPCS_Common>
 ]>;
 
 let Entry = 1 in
 def RetCC_ARM_AAPCS_VFP : CallingConv<[
   // Handle all vector types as either f64 or v2f64.
-  CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
-  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+  CCIfType<[v1i64, v2i32, v4i16, v4f16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
+  CCIfType<[v2i64, v4i32, v8i16, v8f16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
 
   // Pass SwiftSelf in a callee saved register.
   CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
 
   // A SwiftError is returned in R8.
   CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
 
   CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,

llvm/trunk/test/CodeGen/ARM/fp16-vector-argument.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv8a -mattr=+armv8.2-a,+fullfp16,+neon -target-abi=aapcs-gnu -float-abi=soft -o - %s | FileCheck %s --check-prefix=SOFT
+; RUN: llc -mtriple=armv8a -mattr=+armv8.2-a,+fullfp16,+neon -target-abi=aapcs-gnu -float-abi=hard -o - %s | FileCheck %s --check-prefix=HARD
+; RUNTOADD: llc -mtriple=armeb-eabi -mattr=+armv8.2-a,+fullfp16,+neon -target-abi=aapcs-gnu -float-abi=soft -o - %s | FileCheck %s --check-prefix=SOFTEB
+; RUNTOADD: llc -mtriple=armeb-eabi -mattr=+armv8.2-a,+fullfp16,+neon -target-abi=aapcs-gnu -float-abi=hard -o - %s | FileCheck %s --check-prefix=HARDEB
+
+declare <4 x half> @llvm.fabs.v4f16(<4 x half>)
+declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
+declare void @use(double, float, <4 x half>, i16, <8 x half>)
+define <4 x half> @test_vabs_f16(<4 x half> %a) {
+; SOFT-LABEL: test_vabs_f16:
+; SOFT:       @ %bb.0: @ %entry
+; SOFT-NEXT:    vmov d16, r0, r1
+; SOFT-NEXT:    vabs.f16 d16, d16
+; SOFT-NEXT:    vmov r0, r1, d16
+; SOFT-NEXT:    bx lr
+;
+; HARD-LABEL: test_vabs_f16:
+; HARD:       @ %bb.0: @ %entry
+; HARD-NEXT:    vabs.f16 d0, d0
+; HARD-NEXT:    bx lr
+;
+; SOFTEB-LABEL: test_vabs_f16:
+; SOFTEB:       @ %bb.0: @ %entry
+; SOFTEB-NEXT:    vmov d16, r1, r0
+; SOFTEB-NEXT:    vrev64.16 d16, d16
+; SOFTEB-NEXT:    vabs.f16 d16, d16
+; SOFTEB-NEXT:    vrev64.16 d16, d16
+; SOFTEB-NEXT:    vmov r1, r0, d16
+; SOFTEB-NEXT:    bx lr
+;
+; HARDEB-LABEL: test_vabs_f16:
+; HARDEB:       @ %bb.0: @ %entry
+; HARDEB-NEXT:    vrev64.16 d16, d0
+; HARDEB-NEXT:    vabs.f16 d16, d16
+; HARDEB-NEXT:    vrev64.16 d0, d16
+; HARDEB-NEXT:    bx lr
+entry:
+  %vabs1.i = tail call <4 x half> @llvm.fabs.v4f16(<4 x half> %a)
+  ret <4 x half> %vabs1.i
+}
+
+
+define <8 x half> @test2_vabs_f16(<8 x half> %a) {
+; SOFT-LABEL: test2_vabs_f16:
+; SOFT:       @ %bb.0: @ %entry
+; SOFT-NEXT:    vmov d17, r2, r3
+; SOFT-NEXT:    vmov d16, r0, r1
+; SOFT-NEXT:    vabs.f16 q8, q8
+; SOFT-NEXT:    vmov r0, r1, d16
+; SOFT-NEXT:    vmov r2, r3, d17
+; SOFT-NEXT:    bx lr
+;
+; HARD-LABEL: test2_vabs_f16:
+; HARD:       @ %bb.0: @ %entry
+; HARD-NEXT:    vabs.f16 q0, q0
+; HARD-NEXT:    bx lr
+;
+; SOFTEB-LABEL: test2_vabs_f16:
+; SOFTEB:       @ %bb.0: @ %entry
+; SOFTEB-NEXT:    vmov d17, r3, r2
+; SOFTEB-NEXT:    vmov d16, r1, r0
+; SOFTEB-NEXT:    vrev64.16 q8, q8
+; SOFTEB-NEXT:    vabs.f16 q8, q8
+; SOFTEB-NEXT:    vrev64.16 q8, q8
+; SOFTEB-NEXT:    vmov r1, r0, d16
+; SOFTEB-NEXT:    vmov r3, r2, d17
+; SOFTEB-NEXT:    bx lr
+;
+; HARDEB-LABEL: test2_vabs_f16:
+; HARDEB:       @ %bb.0: @ %entry
+; HARDEB-NEXT:    vrev64.16 q8, q0
+; HARDEB-NEXT:    vabs.f16 q8, q8
+; HARDEB-NEXT:    vrev64.16 q0, q8
+; HARDEB-NEXT:    bx lr
+entry:
+  %vabs1.i = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %a)
+  ret <8 x half> %vabs1.i
+}
+
+define void @test(double, float, i16, <4 x half>, <8 x half>) {
+; SOFT-LABEL: test:
+; SOFT:       @ %bb.0: @ %entry
+; SOFT-NEXT:    push {r11, lr}
+; SOFT-NEXT:    sub sp, sp, #32
+; SOFT-NEXT:    vldr d16, [sp, #40]
+; SOFT-NEXT:    mov r12, #16
+; SOFT-NEXT:    vabs.f16 d16, d16
+; SOFT-NEXT:    mov lr, sp
+; SOFT-NEXT:    vst1.16 {d16}, [lr:64], r12
+; SOFT-NEXT:    add r12, sp, #48
+; SOFT-NEXT:    vld1.64 {d16, d17}, [r12]
+; SOFT-NEXT:    vabs.f16 q8, q8
+; SOFT-NEXT:    str r3, [sp, #8]
+; SOFT-NEXT:    vst1.64 {d16, d17}, [lr]
+; SOFT-NEXT:    bl use
+; SOFT-NEXT:    add sp, sp, #32
+; SOFT-NEXT:    pop {r11, pc}
+;
+; HARD-LABEL: test:
+; HARD:       @ %bb.0: @ %entry
+; HARD-NEXT:    vabs.f16 q2, q2
+; HARD-NEXT:    vabs.f16 d2, d2
+; HARD-NEXT:    b use
+;
+; SOFTEB-LABEL: test:
+; SOFTEB:       @ %bb.0: @ %entry
+; SOFTEB-NEXT:    .save {r11, lr}
+; SOFTEB-NEXT:    push {r11, lr}
+; SOFTEB-NEXT:    .pad #32
+; SOFTEB-NEXT:    sub sp, sp, #32
+; SOFTEB-NEXT:    vldr d16, [sp, #40]
+; SOFTEB-NEXT:    mov r12, #16
+; SOFTEB-NEXT:    mov lr, sp
+; SOFTEB-NEXT:    str r3, [sp, #8]
+; SOFTEB-NEXT:    vrev64.16 d16, d16
+; SOFTEB-NEXT:    vabs.f16 d16, d16
+; SOFTEB-NEXT:    vst1.16 {d16}, [lr:64], r12
+; SOFTEB-NEXT:    add r12, sp, #48
+; SOFTEB-NEXT:    vld1.64 {d16, d17}, [r12]
+; SOFTEB-NEXT:    vrev64.16 q8, q8
+; SOFTEB-NEXT:    vabs.f16 q8, q8
+; SOFTEB-NEXT:    vrev64.16 q8, q8
+; SOFTEB-NEXT:    vst1.64 {d16, d17}, [lr]
+; SOFTEB-NEXT:    bl use
+; SOFTEB-NEXT:    add sp, sp, #32
+; SOFTEB-NEXT:    pop {r11, pc}
+;
+; HARDEB-LABEL: test:
+; HARDEB:       @ %bb.0: @ %entry
+; HARDEB-NEXT:    vrev64.16 d16, d2
+; HARDEB-NEXT:    vabs.f16 d16, d16
+; HARDEB-NEXT:    vrev64.16 d2, d16
+; HARDEB-NEXT:    vrev64.16 q8, q2
+; HARDEB-NEXT:    vabs.f16 q8, q8
+; HARDEB-NEXT:    vrev64.16 q2, q8
+; HARDEB-NEXT:    b use
+entry:
+  %5 = tail call <4 x half> @llvm.fabs.v4f16(<4 x half> %3)
+  %6 = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %4)
+  tail call void @use(double %0, float %1, <4 x half> %5, i16 %2, <8 x half> %6)
+  ret void
+}
+
+define void @many_args_test(double, float, i16, <4 x half>, <8 x half>, <8 x half>, <8 x half>) {
+; SOFT-LABEL: many_args_test:
+; SOFT:       @ %bb.0: @ %entry
+; SOFT-NEXT:    push {r11, lr}
+; SOFT-NEXT:    sub sp, sp, #32
+; SOFT-NEXT:    add r12, sp, #80
+; SOFT-NEXT:    mov lr, sp
+; SOFT-NEXT:    vld1.64 {d16, d17}, [r12]
+; SOFT-NEXT:    add r12, sp, #48
+; SOFT-NEXT:    vabs.f16 q8, q8
+; SOFT-NEXT:    vld1.64 {d18, d19}, [r12]
+; SOFT-NEXT:    add r12, sp, #64
+; SOFT-NEXT:    str r3, [sp, #8]
+; SOFT-NEXT:    vadd.f16 q8, q8, q9
+; SOFT-NEXT:    vld1.64 {d18, d19}, [r12]
+; SOFT-NEXT:    mov r12, #16
+; SOFT-NEXT:    vmul.f16 q8, q9, q8
+; SOFT-NEXT:    vldr d18, [sp, #40]
+; SOFT-NEXT:    vst1.16 {d18}, [lr:64], r12
+; SOFT-NEXT:    vst1.64 {d16, d17}, [lr]
+; SOFT-NEXT:    bl use
+; SOFT-NEXT:    add sp, sp, #32
+; SOFT-NEXT:    pop {r11, pc}
+;
+; HARD-LABEL: many_args_test:
+; HARD:       @ %bb.0: @ %entry
+; HARD-NEXT:    mov r1, sp
+; HARD-NEXT:    vld1.64 {d16, d17}, [r1]
+; HARD-NEXT:    vabs.f16 q8, q8
+; HARD-NEXT:    vadd.f16 q8, q8, q2
+; HARD-NEXT:    vmul.f16 q2, q3, q8
+; HARD-NEXT:    b use
+;
+; SOFTEB-LABEL: many_args_test:
+; SOFTEB:       @ %bb.0: @ %entry
+; SOFTEB-NEXT:    .save {r11, lr}
+; SOFTEB-NEXT:    push {r11, lr}
+; SOFTEB-NEXT:    .pad #32
+; SOFTEB-NEXT:    sub sp, sp, #32
+; SOFTEB-NEXT:    vldr d16, [sp, #40]
+; SOFTEB-NEXT:    mov r12, #16
+; SOFTEB-NEXT:    mov lr, sp
+; SOFTEB-NEXT:    str r3, [sp, #8]
+; SOFTEB-NEXT:    vrev64.16 d16, d16
+; SOFTEB-NEXT:    vst1.16 {d16}, [lr:64], r12
+; SOFTEB-NEXT:    add r12, sp, #80
+; SOFTEB-NEXT:    vld1.64 {d16, d17}, [r12]
+; SOFTEB-NEXT:    add r12, sp, #48
+; SOFTEB-NEXT:    vrev64.16 q8, q8
+; SOFTEB-NEXT:    vabs.f16 q8, q8
+; SOFTEB-NEXT:    vld1.64 {d18, d19}, [r12]
+; SOFTEB-NEXT:    add r12, sp, #64
+; SOFTEB-NEXT:    vrev64.16 q9, q9
+; SOFTEB-NEXT:    vadd.f16 q8, q8, q9
+; SOFTEB-NEXT:    vld1.64 {d18, d19}, [r12]
+; SOFTEB-NEXT:    vrev64.16 q9, q9
+; SOFTEB-NEXT:    vmul.f16 q8, q9, q8
+; SOFTEB-NEXT:    vrev64.16 q8, q8
+; SOFTEB-NEXT:    vst1.64 {d16, d17}, [lr]
+; SOFTEB-NEXT:    bl use
+; SOFTEB-NEXT:    add sp, sp, #32
+; SOFTEB-NEXT:    pop {r11, pc}
+;
+; HARDEB-LABEL: many_args_test:
+; HARDEB:       @ %bb.0: @ %entry
+; HARDEB-NEXT:    mov r1, sp
+; HARDEB-NEXT:    vld1.64 {d16, d17}, [r1]
+; HARDEB-NEXT:    vrev64.16 q8, q8
+; HARDEB-NEXT:    vabs.f16 q8, q8
+; HARDEB-NEXT:    vrev64.16 q9, q2
+; HARDEB-NEXT:    vadd.f16 q8, q8, q9
+; HARDEB-NEXT:    vrev64.16 q9, q3
+; HARDEB-NEXT:    vmul.f16 q8, q9, q8
+; HARDEB-NEXT:    vrev64.16 q2, q8
+; HARDEB-NEXT:    b use
+entry:
+  %7 = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %6)
+  %8 = fadd <8 x half> %7, %4
+  %9 = fmul <8 x half> %5, %8
+  tail call void @use(double %0, float %1, <4 x half> %3, i16 %2, <8 x half> %9)
+  ret void
+}