[MC] Minor cleanup to MCFixup::Kind handling. NFC.

[sbc100]

Summary

Prefer MCFixupKind where possible and add getTargetKind() to
convert to unsigned when needed rather than scatterin cast
operators around the place.

[sbc100]

• revert

[sbc100]

• revert more

[sbc100]

• rebase

[sbc100]

• rebase

[sbc100]

• rebase

[sbc100]

@grosbach do you have time to take quick look? Should be fairly straight forward.

[sbc100]

rebase

[sbc100]

• rebase

[dschuff]

Nice.

llvm/include/llvm/MC/MCFixup.h

class MCFixup {
   /// an instruction or an assembler directive.
   const MCExpr *Value;
 
   /// The byte index of start of the relocation inside the MCFragment.
   uint32_t Offset;
 
   /// The target dependent kind of fixup item this is. The kind is used to
   /// determine how the operand value should be encoded into the instruction.
-  unsigned Kind;
+  MCFixupKind Kind;
 
   /// The source location which gave rise to the fixup, if any.
   SMLoc Loc;
 public:
   static MCFixup create(uint32_t Offset, const MCExpr *Value,
                         MCFixupKind Kind, SMLoc Loc = SMLoc()) {
-    assert(unsigned(Kind) < MaxTargetFixupKind && "Kind out of range!");
+    assert(Kind < MaxTargetFixupKind && "Kind out of range!");
     MCFixup FI;
     FI.Value = Value;
     FI.Offset = Offset;
-    FI.Kind = unsigned(Kind);
+    FI.Kind = Kind;
     FI.Loc = Loc;
     return FI;
   }
 
   /// Return a fixup corresponding to the add half of a add/sub fixup pair for
   /// the given Fixup.
   static MCFixup createAddFor(const MCFixup &Fixup) {
     MCFixup FI;
     FI.Value = Fixup.getValue();
     FI.Offset = Fixup.getOffset();
-    FI.Kind = (unsigned)getAddKindForKind(Fixup.getKind());
+    FI.Kind = getAddKindForKind(Fixup.getKind());
     FI.Loc = Fixup.getLoc();
     return FI;
   }
 
   /// Return a fixup corresponding to the sub half of a add/sub fixup pair for
   /// the given Fixup.
   static MCFixup createSubFor(const MCFixup &Fixup) {
     MCFixup FI;
     FI.Value = Fixup.getValue();
     FI.Offset = Fixup.getOffset();
-    FI.Kind = (unsigned)getSubKindForKind(Fixup.getKind());
+    FI.Kind = getSubKindForKind(Fixup.getKind());
     FI.Loc = Fixup.getLoc();
     return FI;
   }
 
-  MCFixupKind getKind() const { return MCFixupKind(Kind); }
+  MCFixupKind getKind() const { return Kind; }
+
+  unsigned getTargetKind() const { return Kind; }
 
   uint32_t getOffset() const { return Offset; }
   void setOffset(uint32_t Value) { Offset = Value; }
 
   const MCExpr *getValue() const { return Value; }
 
   /// Return the generic fixup kind for a value with the given size. It
   /// is an error to pass an unsupported size.
   static MCFixupKind getKindForSize(unsigned Size, bool isPCRel) {
     switch (Size) {
     default: llvm_unreachable("Invalid generic fixup size!");
     case 1: return isPCRel ? FK_PCRel_1 : FK_Data_1;
     case 2: return isPCRel ? FK_PCRel_2 : FK_Data_2;
     case 4: return isPCRel ? FK_PCRel_4 : FK_Data_4;
     case 8: return isPCRel ? FK_PCRel_8 : FK_Data_8;
     }
   }
 
   /// Return the generic fixup kind for an addition with a given size. It
   /// is an error to pass an unsupported size.
-  static MCFixupKind getAddKindForKind(unsigned Kind) {
+  static MCFixupKind getAddKindForKind(MCFixupKind Kind) {
     switch (Kind) {
     default: llvm_unreachable("Unknown type to convert!");
     case FK_Data_1: return FK_Data_Add_1;
     case FK_Data_2: return FK_Data_Add_2;
     case FK_Data_4: return FK_Data_Add_4;
     case FK_Data_8: return FK_Data_Add_8;
     }
   }
 
   /// Return the generic fixup kind for an subtraction with a given size. It
   /// is an error to pass an unsupported size.
-  static MCFixupKind getSubKindForKind(unsigned Kind) {
+  static MCFixupKind getSubKindForKind(MCFixupKind Kind) {
     switch (Kind) {
     default: llvm_unreachable("Unknown type to convert!");
     case FK_Data_1: return FK_Data_Sub_1;
     case FK_Data_2: return FK_Data_Sub_2;
     case FK_Data_4: return FK_Data_Sub_4;
     case FK_Data_8: return FK_Data_Sub_8;
     }
   }
 
   SMLoc getLoc() const { return Loc; }
 };
 
 } // End llvm namespace
 
 #endif

llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

static unsigned AdrImmBits(unsigned Value) {
   unsigned lo2 = Value & 0x3;
   unsigned hi19 = (Value & 0x1ffffc) >> 2;
   return (hi19 << 5) | (lo2 << 29);
 }
 
 static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target,
                                  uint64_t Value, MCContext &Ctx,
                                  const Triple &TheTriple, bool IsResolved) {
-  unsigned Kind = Fixup.getKind();
   int64_t SignedValue = static_cast<int64_t>(Value);
-  switch (Kind) {
+  switch (Fixup.getTargetKind()) {
   default:
     llvm_unreachable("Unknown fixup kind!");
   case AArch64::fixup_aarch64_pcrel_adr_imm21:
     if (SignedValue > 2097151 || SignedValue < -2097152)
       Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
     return AdrImmBits(Value & 0x1fffffULL);
   case AArch64::fixup_aarch64_pcrel_adrp_imm21:
     assert(!IsResolved);
bool AArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm,
   //     ADRP x0, there
   //  there:
   //
   // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
   // we'll need that as an offset. At any other address "there" will be in the
   // same page as the ADRP and the instruction should encode 0x0. Assuming the
   // section isn't 0x1000-aligned, we therefore need to delegate this decision
   // to the linker -- a relocation!
-  if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_pcrel_adrp_imm21)
+  if (Fixup.getTargetKind() == AArch64::fixup_aarch64_pcrel_adrp_imm21)
     return true;
 
   AArch64MCExpr::VariantKind RefKind =
       static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
   AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
   // LDR GOT relocations need a relocation
-  if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_ldr_pcrel_imm19 &&
+  if (Fixup.getTargetKind() == AArch64::fixup_aarch64_ldr_pcrel_imm19 &&
       SymLoc == AArch64MCExpr::VK_GOT)
     return true;
   return false;
 }
 
 namespace {
 
 namespace CU {

llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp

 #define BAD_ILP32_MOV(lp64rtype)                                               \
   "ILP32 absolute MOV relocation not "                                         \
   "supported (LP64 eqv: " #lp64rtype ")"
 
 // assumes IsILP32 is true
 static bool isNonILP32reloc(const MCFixup &Fixup,
                             AArch64MCExpr::VariantKind RefKind,
                             MCContext &Ctx) {
-  if ((unsigned)Fixup.getKind() != AArch64::fixup_aarch64_movw)
+  if (Fixup.getTargetKind() != AArch64::fixup_aarch64_movw)
     return false;
   switch (RefKind) {
   case AArch64MCExpr::VK_ABS_G3:
     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G3));
     return true;
   case AArch64MCExpr::VK_ABS_G2:
     Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2));
     return true;
assert((!Target.getSymA() ||
           Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None) &&
          "Should only be expression-level modifiers here");
 
   assert((!Target.getSymB() ||
           Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) &&
          "Should only be expression-level modifiers here");
 
   if (IsPCRel) {
-    switch ((unsigned)Fixup.getKind()) {
+    switch (Fixup.getTargetKind()) {
     case FK_Data_1:
       Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
       return ELF::R_AARCH64_NONE;
     case FK_Data_2:
       return R_CLS(PREL16);
     case FK_Data_4:
       return R_CLS(PREL32);
     case FK_Data_8:
case AArch64::fixup_aarch64_pcrel_branch19:
       return R_CLS(CONDBR19);
     default:
       Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
       return ELF::R_AARCH64_NONE;
     }
   } else {
     if (IsILP32 && isNonILP32reloc(Fixup, RefKind, Ctx))
       return ELF::R_AARCH64_NONE;
-    switch ((unsigned)Fixup.getKind()) {
+    switch (Fixup.getTargetKind()) {
     case FK_Data_1:
       Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
       return ELF::R_AARCH64_NONE;
     case FK_Data_2:
       return R_CLS(ABS16);
     case FK_Data_4:
       return R_CLS(ABS32);
     case FK_Data_8:

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp

 } // end anonymous namespace
 
 bool AArch64MachObjectWriter::getAArch64FixupKindMachOInfo(
     const MCFixup &Fixup, unsigned &RelocType, const MCSymbolRefExpr *Sym,
     unsigned &Log2Size, const MCAssembler &Asm) {
   RelocType = unsigned(MachO::ARM64_RELOC_UNSIGNED);
   Log2Size = ~0U;
 
-  switch ((unsigned)Fixup.getKind()) {
+  switch (Fixup.getTargetKind()) {
   default:
     return false;
 
   case FK_Data_1:
     Log2Size = Log2_32(1);
     return true;
   case FK_Data_2:
     Log2Size = Log2_32(2);

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

default:
     llvm_unreachable("Unknown fixup kind!");
   }
 }
 
 static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
                                  MCContext *Ctx) {
   int64_t SignedValue = static_cast<int64_t>(Value);
 
-  switch (static_cast<unsigned>(Fixup.getKind())) {
+  switch (Fixup.getTargetKind()) {
   case AMDGPU::fixup_si_sopp_br: {
     int64_t BrImm = (SignedValue - 4) / 4;
 
     if (Ctx && !isInt<16>(BrImm))
       Ctx->reportError(Fixup.getLoc(), "branch size exceeds simm16");
 
     return BrImm;
   }

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst,
                                       const MCSubtargetInfo &STI) const {
   if (getRelaxedOpcode(Inst.getOpcode(), STI) != Inst.getOpcode())
     return true;
   return false;
 }
 
 const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup,
                                                     uint64_t Value) const {
-  switch ((unsigned)Fixup.getKind()) {
+  switch (Fixup.getTargetKind()) {
   case ARM::fixup_arm_thumb_br: {
     // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
     // low bit being an implied zero. There's an implied +4 offset for the
     // branch, so we adjust the other way here to determine what's
     // encodable.
     //
     // Relax if the value is too big for a (signed) i8.
     int64_t Offset = int64_t(Value) - 4;

 }
 
 bool ARMAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
                                           const MCFixup &Fixup,
                                           const MCValue &Target) {
   const MCSymbolRefExpr *A = Target.getSymA();
   const MCSymbol *Sym = A ? &A->getSymbol() : nullptr;
   const unsigned FixupKind = Fixup.getKind() ;
-  if ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) {
+  if (FixupKind == ARM::fixup_arm_thumb_bl) {
     assert(Sym && "How did we resolve this?");
 
     // If the symbol is external the linker will handle it.
     // FIXME: Should we handle it as an optimization?
 
     // If the symbol is out of range, produce a relocation and hope the
     // linker can handle it. GNU AS produces an error in this case.
     if (Sym->isExternal())

llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp

 
 unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
                                                const MCFixup &Fixup,
                                                bool IsPCRel,
                                                MCContext &Ctx) const {
   MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant();
 
   if (IsPCRel) {
-    switch ((unsigned)Fixup.getKind()) {
+    switch (Fixup.getTargetKind()) {
     default:
       Ctx.reportFatalError(Fixup.getLoc(), "unsupported relocation on symbol");
       return ELF::R_ARM_NONE;
     case FK_Data_4:
       switch (Modifier) {
       default:
         llvm_unreachable("Unsupported Modifier");
       case MCSymbolRefExpr::VK_None:
case ARM::fixup_arm_thumb_blx:
       switch (Modifier) {
       case MCSymbolRefExpr::VK_TLSCALL:
         return ELF::R_ARM_THM_TLS_CALL;
       default:
         return ELF::R_ARM_THM_CALL;
       }
     }
   }
-  switch ((unsigned)Fixup.getKind()) {
+  switch (Fixup.getTargetKind()) {
   default:
     Ctx.reportFatalError(Fixup.getLoc(), "unsupported relocation on symbol");
     return ELF::R_ARM_NONE;
   case FK_Data_1:
     switch (Modifier) {
     default:
       llvm_unreachable("unsupported Modifier");
     case MCSymbolRefExpr::VK_None:

llvm/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp

RecordARMScatteredHalfRelocation(MachObjectWriter *Writer,
   //      1 - :upper16: for movt instructions
   //   high bit of r_length:
   //      0 - arm instructions
   //      1 - thumb instructions
   // the other half of the relocated expression is in the following pair
   // relocation entry in the low 16 bits of r_address field.
   unsigned ThumbBit = 0;
   unsigned MovtBit = 0;
-  switch ((unsigned)Fixup.getKind()) {
+  switch (Fixup.getTargetKind()) {
   default: break;
   case ARM::fixup_arm_movt_hi16:
     MovtBit = 1;
     // The thumb bit shouldn't be set in the 'other-half' bit of the
     // relocation, but it will be set in FixedValue if the base symbol
     // is a thumb function. Clear it out here.
     if (Asm.isThumbFunc(A))
       FixedValue &= 0xfffffffe;
void ARMMachObjectWriter::recordRelocation(MachObjectWriter *Writer,
   // Even when it's not a scattered relocation, movw/movt always uses
   // a PAIR relocation.
   if (Type == MachO::ARM_RELOC_HALF) {
     // The entire addend is needed to correctly apply a relocation. One half is
     // extracted from the instruction itself, the other comes from this
     // PAIR. I.e. it's correct that we insert the high bits of the addend in the
     // MOVW case here.  relocation entries.
     uint32_t Value = 0;
-    switch ((unsigned)Fixup.getKind()) {
+    switch (Fixup.getTargetKind()) {
     default: break;
     case ARM::fixup_arm_movw_lo16:
     case ARM::fixup_t2_movw_lo16:
       Value = (FixedValue >> 16) & 0xffff;
       break;
     case ARM::fixup_arm_movt_hi16:
     case ARM::fixup_t2_movt_hi16:
       Value = FixedValue & 0xffff;

llvm/lib/Target/BPF/MCTargetDesc/BPFELFObjectWriter.cpp

 BPFELFObjectWriter::BPFELFObjectWriter(uint8_t OSABI)
     : MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI, ELF::EM_BPF,
                               /*HasRelocationAddend*/ false) {}
 
 unsigned BPFELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
                                           const MCFixup &Fixup,
                                           bool IsPCRel) const {
   // determine the type of the relocation
-  switch ((unsigned)Fixup.getKind()) {
+  switch (Fixup.getKind()) {
   default:
     llvm_unreachable("invalid fixup kind!");
   case FK_SecRel_8:
     return ELF::R_BPF_64_64;
   case FK_PCRel_4:
   case FK_SecRel_4:
     return ELF::R_BPF_64_32;
   case FK_Data_8:

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp

const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
 
     assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
            "Invalid kind!");
     return Infos[Kind - FirstTargetFixupKind];
   }
 
   bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
                              const MCValue &Target) override {
-    MCFixupKind Kind = Fixup.getKind();
-
-    switch((unsigned)Kind) {
+    switch(Fixup.getTargetKind()) {
       default:
         llvm_unreachable("Unknown Fixup Kind!");
 
       case fixup_Hexagon_LO16:
       case fixup_Hexagon_HI16:
       case fixup_Hexagon_16:
       case fixup_Hexagon_8:
       case fixup_Hexagon_GPREL16_0:
bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
     *RelaxTarget = nullptr;
     MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
         MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
     bool Relaxable = isInstRelaxable(MCI);
     if (Relaxable == false)
       return false;
     // If we cannot resolve the fixup value, it requires relaxation.
     if (!Resolved) {
-      switch ((unsigned)Fixup.getKind()) {
+      switch (Fixup.getTargetKind()) {
       case fixup_Hexagon_B22_PCREL:
         // GetFixupCount assumes B22 won't relax
         LLVM_FALLTHROUGH;
       default:
         return false;
         break;
       case fixup_Hexagon_B13_PCREL:
       case fixup_Hexagon_B15_PCREL:

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp

: MCELFObjectTargetWriter(/*Is64bit*/ false, OSABI, ELF::EM_HEXAGON,
                               /*HasRelocationAddend*/ true),
       CPU(C) {}
 
 unsigned HexagonELFObjectWriter::getRelocType(MCContext &Ctx,
                                               MCValue const &Target,
                                               MCFixup const &Fixup,
                                               bool IsPCRel) const {
   MCSymbolRefExpr::VariantKind Variant = Target.getAccessVariant();
-  switch ((unsigned)Fixup.getKind()) {
+  switch (Fixup.getTargetKind()) {
   default:
     report_fatal_error("Unrecognized relocation type");
     break;
   case FK_Data_4:
     switch(Variant) {
     case MCSymbolRefExpr::VariantKind::VK_DTPREL:
       return ELF::R_HEX_DTPREL_32;
     case MCSymbolRefExpr::VariantKind::VK_GOT:

llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFObjectWriter.cpp

: MCELFObjectTargetWriter(false, OSABI, ELF::EM_MSP430,
                               /*HasRelocationAddend*/ true) {}
 
   ~MSP430ELFObjectWriter() override {}
 
 protected:
   unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
                         const MCFixup &Fixup, bool IsPCRel) const override {
     // Translate fixup kind to ELF relocation type.
-    switch ((unsigned)Fixup.getKind()) {
+    switch (Fixup.getTargetKind()) {
     case FK_Data_1:                   return ELF::R_MSP430_8;
     case FK_Data_2:                   return ELF::R_MSP430_16_BYTE;
     case FK_Data_4:                   return ELF::R_MSP430_32;
     case MSP430::fixup_32:            return ELF::R_MSP430_32;
     case MSP430::fixup_10_pcrel:      return ELF::R_MSP430_10_PCREL;
     case MSP430::fixup_16:            return ELF::R_MSP430_16;
     case MSP430::fixup_16_pcrel:      return ELF::R_MSP430_16_PCREL;
     case MSP430::fixup_16_byte:       return ELF::R_MSP430_16_BYTE;

llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp

MipsELFObjectWriter::MipsELFObjectWriter(uint8_t OSABI,
                                          bool HasRelocationAddend, bool Is64)
     : MCELFObjectTargetWriter(Is64, OSABI, ELF::EM_MIPS, HasRelocationAddend) {}
 
 unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx,
                                            const MCValue &Target,
                                            const MCFixup &Fixup,
                                            bool IsPCRel) const {
   // Determine the type of the relocation.
-  unsigned Kind = (unsigned)Fixup.getKind();
+  unsigned Kind = Fixup.getTargetKind();
 
   switch (Kind) {
   case Mips::fixup_Mips_NONE:
     return ELF::R_MIPS_NONE;
   case FK_Data_1:
     Ctx.reportError(Fixup.getLoc(),
                     "MIPS does not support one byte relocations");
     return ELF::R_MIPS_NONE;

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp

 unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
                                           const MCFixup &Fixup,
                                           bool IsPCRel) const {
   MCSymbolRefExpr::VariantKind Modifier = getAccessVariant(Target, Fixup);
 
   // determine the type of the relocation
   unsigned Type;
   if (IsPCRel) {
-    switch ((unsigned)Fixup.getKind()) {
+    switch (Fixup.getTargetKind()) {
     default:
       llvm_unreachable("Unimplemented");
     case PPC::fixup_ppc_br24:
     case PPC::fixup_ppc_br24abs:
       switch (Modifier) {
       default: llvm_unreachable("Unsupported Modifier");
       case MCSymbolRefExpr::VK_None:
         Type = ELF::R_PPC_REL24;
case FK_PCRel_4:
       Type = ELF::R_PPC_REL32;
       break;
     case FK_Data_8:
     case FK_PCRel_8:
       Type = ELF::R_PPC64_REL64;
       break;
     }
   } else {
-    switch ((unsigned)Fixup.getKind()) {
+    switch (Fixup.getTargetKind()) {
       default: llvm_unreachable("invalid fixup kind!");
     case PPC::fixup_ppc_br24abs:
       Type = ELF::R_PPC_ADDR24;
       break;
     case PPC::fixup_ppc_brcond14abs:
       Type = ELF::R_PPC_ADDR14; // XXX: or BRNTAKEN?_
       break;
     case PPC::fixup_ppc_half16:

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp

 
 /// Compute fixup offset (address).
 static uint32_t getFixupOffset(const MCAsmLayout &Layout,
                                const MCFragment *Fragment,
                                const MCFixup &Fixup) {
   uint32_t FixupOffset = Layout.getFragmentOffset(Fragment) + Fixup.getOffset();
   // On Mach-O, ppc_fixup_half16 relocations must refer to the
   // start of the instruction, not the second halfword, as ELF does
-  if (unsigned(Fixup.getKind()) == PPC::fixup_ppc_half16)
+  if (Fixup.getTargetKind() == PPC::fixup_ppc_half16)
     FixupOffset &= ~uint32_t(3);
   return FixupOffset;
 }
 
 /// \return false if falling back to using non-scattered relocation,
 /// otherwise true for normal scattered relocation.
 /// based on X86MachObjectWriter::recordScatteredRelocation
 /// and ARMMachObjectWriter::recordScatteredRelocation

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

 // If linker relaxation is enabled, or the relax option had previously been
 // enabled, always emit relocations even if the fixup can be resolved. This is
 // necessary for correctness as offsets may change during relaxation.
 bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
                                             const MCFixup &Fixup,
                                             const MCValue &Target) {
   bool ShouldForce = false;
 
-  switch ((unsigned)Fixup.getKind()) {
+  switch (Fixup.getTargetKind()) {
   default:
     break;
   case RISCV::fixup_riscv_got_hi20:
     return true;
   case RISCV::fixup_riscv_pcrel_lo12_i:
   case RISCV::fixup_riscv_pcrel_lo12_s:
     // For pcrel_lo12, force a relocation if the target of the corresponding
     // pcrel_hi20 is not in the same fragment.
     const MCFixup *T = cast<RISCVMCExpr>(Fixup.getValue())->getPCRelHiFixup();
     if (!T) {
       Asm.getContext().reportError(Fixup.getLoc(),
                                    "could not find corresponding %pcrel_hi");
       return false;
     }
 
-    switch ((unsigned)T->getKind()) {
+    switch (T->getTargetKind()) {
     default:
       llvm_unreachable("Unexpected fixup kind for pcrel_lo12");
       break;
     case RISCV::fixup_riscv_got_hi20:
       ShouldForce = true;
       break;
     case RISCV::fixup_riscv_pcrel_hi20:
       ShouldForce = T->getValue()->findAssociatedFragment() !=
bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,
   // Return true if the symbol is actually unresolved.
   // Resolved could be always false when shouldForceRelocation return true.
   // We use !WasForced to indicate that the symbol is unresolved and not forced
   // by shouldForceRelocation.
   if (!Resolved && !WasForced)
     return true;
 
   int64_t Offset = int64_t(Value);
-  switch ((unsigned)Fixup.getKind()) {
+  switch (Fixup.getTargetKind()) {
   default:
     return false;
   case RISCV::fixup_riscv_rvc_branch:
     // For compressed branch instructions the immediate must be
     // in the range [-256, 254].
     return Offset > 254 || Offset < -256;
   case RISCV::fixup_riscv_rvc_jump:
     // For compressed jump instructions the immediate must be
for (uint64_t i = Nop16Count; i != 0; --i)
       OS.write("\x01\0", 2);
   }
 
   return true;
 }
 
 static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
                                  MCContext &Ctx) {
-  unsigned Kind = Fixup.getKind();
-  switch (Kind) {
+  switch (Fixup.getTargetKind()) {
   default:
     llvm_unreachable("Unknown fixup kind!");
   case RISCV::fixup_riscv_got_hi20:
     llvm_unreachable("Relocation should be unconditionally forced\n");
   case FK_Data_1:
   case FK_Data_2:
   case FK_Data_4:
   case FK_Data_8:

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

 
 RISCVELFObjectWriter::~RISCVELFObjectWriter() {}
 
 unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
                                             const MCValue &Target,
                                             const MCFixup &Fixup,
                                             bool IsPCRel) const {
   // Determine the type of the relocation
-  switch ((unsigned)Fixup.getKind()) {
+  switch (Fixup.getTargetKind()) {
   default:
     llvm_unreachable("invalid fixup kind!");
   case FK_Data_4:
     return ELF::R_RISCV_32;
   case FK_Data_8:
     return ELF::R_RISCV_64;
   case FK_Data_Add_1:
     return ELF::R_RISCV_ADD8;

llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp

unsigned SparcELFObjectWriter::getRelocType(MCContext &Ctx,
                                             bool IsPCRel) const {
 
   if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Fixup.getValue())) {
     if (SExpr->getKind() == SparcMCExpr::VK_Sparc_R_DISP32)
       return ELF::R_SPARC_DISP32;
   }
 
   if (IsPCRel) {
-    switch((unsigned)Fixup.getKind()) {
+    switch(Fixup.getTargetKind()) {
     default:
       llvm_unreachable("Unimplemented fixup -> relocation");
     case FK_Data_1:                  return ELF::R_SPARC_DISP8;
     case FK_Data_2:                  return ELF::R_SPARC_DISP16;
     case FK_Data_4:                  return ELF::R_SPARC_DISP32;
     case FK_Data_8:                  return ELF::R_SPARC_DISP64;
     case Sparc::fixup_sparc_call30:  return ELF::R_SPARC_WDISP30;
     case Sparc::fixup_sparc_br22:    return ELF::R_SPARC_WDISP22;
     case Sparc::fixup_sparc_br19:    return ELF::R_SPARC_WDISP19;
     case Sparc::fixup_sparc_pc22:    return ELF::R_SPARC_PC22;
     case Sparc::fixup_sparc_pc10:    return ELF::R_SPARC_PC10;
     case Sparc::fixup_sparc_wplt30:  return ELF::R_SPARC_WPLT30;
     }
   }
 
-  switch((unsigned)Fixup.getKind()) {
+  switch(Fixup.getTargetKind()) {
   default:
     llvm_unreachable("Unimplemented fixup -> relocation");
   case FK_Data_1:                return ELF::R_SPARC_8;
   case FK_Data_2:                return ((Fixup.getOffset() % 2)
                                          ? ELF::R_SPARC_UA16
                                          : ELF::R_SPARC_16);
   case FK_Data_4:                return ((Fixup.getOffset() % 4)
                                          ? ELF::R_SPARC_UA32

llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyWasmObjectWriter.cpp

 }
 
 unsigned WebAssemblyWasmObjectWriter::getRelocType(const MCValue &Target,
                                                    const MCFixup &Fixup) const {
   const MCSymbolRefExpr *RefA = Target.getSymA();
   assert(RefA);
   auto& SymA = cast<MCSymbolWasm>(RefA->getSymbol());
 
-  switch (unsigned(Fixup.getKind())) {
+  switch (Fixup.getTargetKind()) {
   case WebAssembly::fixup_sleb128_i32:
     if (SymA.isFunction())
       return wasm::R_WASM_TABLE_INDEX_SLEB;
     return wasm::R_WASM_MEMORY_ADDR_SLEB;
   case WebAssembly::fixup_sleb128_i64:
     llvm_unreachable("fixup_sleb128_i64 not implemented yet");
   case WebAssembly::fixup_uleb128_i32:
     if (SymA.isGlobal() || isGOTRef(RefA))

llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp

X86ELFObjectWriter::X86ELFObjectWriter(bool IsELF64, uint8_t OSABI,
     : MCELFObjectTargetWriter(IsELF64, OSABI, EMachine,
                               // Only i386 and IAMCU use Rel instead of RelA.
                               /*HasRelocationAddend*/
                               (EMachine != ELF::EM_386) &&
                                   (EMachine != ELF::EM_IAMCU)) {}
 
 enum X86_64RelType { RT64_64, RT64_32, RT64_32S, RT64_16, RT64_8 };
 
-static X86_64RelType getType64(unsigned Kind,
+static X86_64RelType getType64(MCFixupKind Kind,
                                MCSymbolRefExpr::VariantKind &Modifier,
                                bool &IsPCRel) {
-  switch (Kind) {
+  switch (unsigned(Kind)) {
   default:
     llvm_unreachable("Unimplemented");
   case X86::reloc_global_offset_table8:
     Modifier = MCSymbolRefExpr::VK_GOT;
     IsPCRel = true;
     return RT64_64;
   case FK_Data_8:
     return RT64_64;
static void checkIs32(MCContext &Ctx, SMLoc Loc, X86_64RelType Type) {
   if (Type != RT64_32)
     Ctx.reportError(Loc,
                     "32 bit reloc applied to a field with a different size");
 }
 
 static unsigned getRelocType64(MCContext &Ctx, SMLoc Loc,
                                MCSymbolRefExpr::VariantKind Modifier,
                                X86_64RelType Type, bool IsPCRel,
-                               unsigned Kind) {
+                               MCFixupKind Kind) {
   switch (Modifier) {
   default:
     llvm_unreachable("Unimplemented");
   case MCSymbolRefExpr::VK_None:
   case MCSymbolRefExpr::VK_X86_ABS8:
     switch (Type) {
     case RT64_64:
       return IsPCRel ? ELF::R_X86_64_PC64 : ELF::R_X86_64_64;
case MCSymbolRefExpr::VK_PLT:
     return ELF::R_X86_64_PLT32;
   case MCSymbolRefExpr::VK_GOTPCREL:
     checkIs32(Ctx, Loc, Type);
     // Older versions of ld.bfd/ld.gold/lld
     // do not support GOTPCRELX/REX_GOTPCRELX,
     // and we want to keep back-compatibility.
     if (!Ctx.getAsmInfo()->canRelaxRelocations())
       return ELF::R_X86_64_GOTPCREL;
-    switch (Kind) {
+    switch (unsigned(Kind)) {
     default:
       return ELF::R_X86_64_GOTPCREL;
     case X86::reloc_riprel_4byte_relax:
       return ELF::R_X86_64_GOTPCRELX;
     case X86::reloc_riprel_4byte_relax_rex:
     case X86::reloc_riprel_4byte_movq_load:
       return ELF::R_X86_64_REX_GOTPCRELX;
     }
case RT64_8:
     return RT32_8;
   }
   llvm_unreachable("unexpected relocation type!");
 }
 
 static unsigned getRelocType32(MCContext &Ctx,
                                MCSymbolRefExpr::VariantKind Modifier,
                                X86_32RelType Type, bool IsPCRel,
-                               unsigned Kind) {
+                               MCFixupKind Kind) {
   switch (Modifier) {
   default:
     llvm_unreachable("Unimplemented");
   case MCSymbolRefExpr::VK_None:
   case MCSymbolRefExpr::VK_X86_ABS8:
     switch (Type) {
     case RT32_32:
       return IsPCRel ? ELF::R_386_PC32 : ELF::R_386_32;
     case RT32_16:
       return IsPCRel ? ELF::R_386_PC16 : ELF::R_386_16;
     case RT32_8:
       return IsPCRel ? ELF::R_386_PC8 : ELF::R_386_8;
     }
     llvm_unreachable("unexpected relocation type!");
   case MCSymbolRefExpr::VK_GOT:
     assert(Type == RT32_32);
     if (IsPCRel)
       return ELF::R_386_GOTPC;
     // Older versions of ld.bfd/ld.gold/lld do not support R_386_GOT32X and we
     // want to maintain compatibility.
     if (!Ctx.getAsmInfo()->canRelaxRelocations())
       return ELF::R_386_GOT32;
 
-    return Kind == X86::reloc_signed_4byte_relax ? ELF::R_386_GOT32X
-                                                 : ELF::R_386_GOT32;
+    return Kind == MCFixupKind(X86::reloc_signed_4byte_relax)
+               ? ELF::R_386_GOT32X
   case MCSymbolRefExpr::VK_GOTOFF:
     assert(Type == RT32_32);
     assert(!IsPCRel);
     return ELF::R_386_GOTOFF;
   case MCSymbolRefExpr::VK_TPOFF:
     assert(Type == RT32_32);
     assert(!IsPCRel);
     return ELF::R_386_TLS_LE_32;
case MCSymbolRefExpr::VK_TLSLDM:
     return ELF::R_386_TLS_LDM;
   }
 }
 
 unsigned X86ELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
                                           const MCFixup &Fixup,
                                           bool IsPCRel) const {
   MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant();
-  unsigned Kind = Fixup.getKind();
+  MCFixupKind Kind = Fixup.getKind();
   X86_64RelType Type = getType64(Kind, Modifier, IsPCRel);
   if (getEMachine() == ELF::EM_X86_64)
     return getRelocType64(Ctx, Fixup.getLoc(), Modifier, Type, IsPCRel, Kind);
 
   assert((getEMachine() == ELF::EM_386 || getEMachine() == ELF::EM_IAMCU) &&
          "Unsupported ELF machine type.");
   return getRelocType32(Ctx, Modifier, getType32(Type), IsPCRel, Kind);
 }
 
 std::unique_ptr<MCObjectTargetWriter>
 llvm::createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine) {
   return llvm::make_unique<X86ELFObjectWriter>(IsELF64, OSABI, EMachine);
 }

llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp

if (Target.isAbsolute()) { // constant
 
     MCSymbolRefExpr::VariantKind Modifier = Target.getSymA()->getKind();
     if (IsPCRel) {
       if (IsRIPRel) {
         if (Modifier == MCSymbolRefExpr::VK_GOTPCREL) {
           // x86_64 distinguishes movq foo@GOTPCREL so that the linker can
           // rewrite the movq to an leaq at link time if the symbol ends up in
           // the same linkage unit.
-          if (unsigned(Fixup.getKind()) == X86::reloc_riprel_4byte_movq_load)
+          if (Fixup.getTargetKind() == X86::reloc_riprel_4byte_movq_load)
             Type = MachO::X86_64_RELOC_GOT_LOAD;
           else
             Type = MachO::X86_64_RELOC_GOT;
         }  else if (Modifier == MCSymbolRefExpr::VK_TLVP) {
           Type = MachO::X86_64_RELOC_TLV;
         }  else if (Modifier != MCSymbolRefExpr::VK_None) {
           Asm.getContext().reportError(
               Fixup.getLoc(), "unsupported symbol modifier in relocation");
if (IsPCRel) {
             Fixup.getLoc(), "TLVP symbol modifier should have been rip-rel");
         return;
       } else if (Modifier != MCSymbolRefExpr::VK_None) {
         Asm.getContext().reportError(
             Fixup.getLoc(), "unsupported symbol modifier in relocation");
         return;
       } else {
         Type = MachO::X86_64_RELOC_UNSIGNED;
-        unsigned Kind = Fixup.getKind();
-        if (Kind == X86::reloc_signed_4byte) {
+        if (Fixup.getTargetKind() == X86::reloc_signed_4byte) {
           Asm.getContext().reportError(
               Fixup.getLoc(),
               "32-bit absolute addressing is not supported in 64-bit mode");
           return;
         }
       }
     }
   }