[llvm-exegesis] Allow the target to disable the selection of some registers.

[courbet]

Summary

This prevents "Cannot encode high byte register in REX-prefixed instruction"
from happening on instructions that require REX encoding when AH & co
get selected.
On the down side, these 4 registers can no longer be selected
automatically, but this avoids having to expose all the X86 encoding
complexity.

[gchatelet]

Thx!

[lebedev.ri]

Would be a good idea to add a test for some opcode that used to fail with that error?

[courbet]

The issue is that such a test would have failed in a non-deterministic manner, which is why I've only added a unit test. But now that this should not longer fail, let's add one.

[courbet]

Add unit test.

[craig.topper]

What protects R8-R15 in 32-bit mode or SIL/DIL/BPL/SPL?

[gchatelet]

In D59821#1444043, @craig.topper wrote:

What protects R8-R15 in 32-bit mode or SIL/DIL/BPL/SPL?

Is there a register class that can used reliably for this purpose?

[courbet]

In D59821#1444043, @craig.topper wrote:

What protects R8-R15 in 32-bit mode or SIL/DIL/BPL/SPL?

Thanks Craig,

This is the x86_64 target (the only one we support at the moment) so we're good on the first part :)

For the rest, TBH I'm not well versed in the subtleties of X86 encoding, so got these registers from the list here.
As Guillaume mentioned if there is a register class I can use I'll be happy to.

[craig.topper]

In D59821#1444188, @courbet wrote:

In D59821#1444043, @craig.topper wrote:

What protects R8-R15 in 32-bit mode or SIL/DIL/BPL/SPL?

Thanks Craig,

This is the x86_64 target (the only one we support at the moment) so we're good on the first part :)

For the rest, TBH I'm not well versed in the subtleties of X86 encoding, so got these registers from the list here.
As Guillaume mentioned if there is a register class I can use I'll be happy to.

I should have phrased my question better. SIL/DIL/BPL/SPL are only available in x86_64. So if that's all you support then you are ok.

[courbet]

OK cool thanks for having a look.

llvm/trunk/test/tools/llvm-exegesis/X86/latency-SBB8rr.s

+# RUN: llvm-exegesis -mode=latency -opcode-name=SBB8rr | FileCheck %s
+
+CHECK:      ---
+CHECK-NEXT: mode: latency
+CHECK-NEXT: key:
+CHECK-NEXT:   instructions:
+CHECK-NEXT:     SBB8rr
+CHECK-NEXT: config: ''
+CHECK-NEXT: register_initial_values:
+CHECK-DAG: - '[[REG1:[A-Z0-9]+]]=0x0'
+CHECK-LAST: ...

llvm/trunk/tools/llvm-exegesis/lib/LlvmState.cpp

TargetMachine.reset(
           Triple, CpuName, Features, Options, llvm::Reloc::Model::Static)));
   TheExegesisTarget = ExegesisTarget::lookup(TargetMachine->getTargetTriple());
   if (!TheExegesisTarget) {
     llvm::errs() << "no exegesis target for " << Triple << ", using default\n";
     TheExegesisTarget = &ExegesisTarget::getDefault();
   }
   PfmCounters = &TheExegesisTarget->getPfmCounters(CpuName);
 
-  RATC.reset(new RegisterAliasingTrackerCache(
-      getRegInfo(), getFunctionReservedRegs(getTargetMachine())));
+  BitVector ReservedRegs = getFunctionReservedRegs(getTargetMachine());
+  for (const unsigned Reg : TheExegesisTarget->getUnavailableRegisters())
+    ReservedRegs.set(Reg);
+  RATC.reset(
+      new RegisterAliasingTrackerCache(getRegInfo(), std::move(ReservedRegs)));
   IC.reset(new InstructionsCache(getInstrInfo(), getRATC()));
 }
 
 LLVMState::LLVMState(const std::string &CpuName)
     : LLVMState(llvm::sys::getProcessTriple(),
                 CpuName.empty() ? llvm::sys::getHostCPUName().str() : CpuName,
                 "") {}
 

llvm/trunk/tools/llvm-exegesis/lib/Target.h

public:
   // Fills memory operands with references to the address at [Reg] + Offset.
   virtual void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
                                   unsigned Offset) const {
 
     llvm_unreachable(
         "fillMemoryOperands() requires getScratchMemoryRegister() > 0");
   }
 
+  // Returns a list of unavailable registers.
+  // Targets can use this to prevent some registers to be automatically selected
+  // for use in snippets.
+  virtual ArrayRef<unsigned> getUnavailableRegisters() const { return {}; }
+
   // Returns the maximum number of bytes a load/store instruction can access at
   // once. This is typically the size of the largest register available on the
   // processor. Note that this only used as a hint to generate independant
   // load/stores to/from memory, so the exact returned value does not really
   // matter as long as it's large enough.
   virtual unsigned getMaxMemoryAccessSize() const { return 0; }
 
   // Creates a snippet generator for the given mode.

llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp

private:
 
   void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
                           unsigned Offset) const override;
 
   std::vector<llvm::MCInst> setRegTo(const llvm::MCSubtargetInfo &STI,
                                      unsigned Reg,
                                      const llvm::APInt &Value) const override;
 
+  ArrayRef<unsigned> getUnavailableRegisters() const override {
+    return makeArrayRef(kUnavailableRegisters,
+                        sizeof(kUnavailableRegisters) /
+                            sizeof(kUnavailableRegisters[0]));
+  }
+
   std::unique_ptr<SnippetGenerator>
   createLatencySnippetGenerator(const LLVMState &State) const override {
     return llvm::make_unique<X86LatencySnippetGenerator>(State);
   }
 
   std::unique_ptr<SnippetGenerator>
   createUopsSnippetGenerator(const LLVMState &State) const override {
     return llvm::make_unique<X86UopsSnippetGenerator>(State);
   }
 
   bool matchesArch(llvm::Triple::ArchType Arch) const override {
     return Arch == llvm::Triple::x86_64 || Arch == llvm::Triple::x86;
   }
+
+  static const unsigned kUnavailableRegisters[4];
 };
+
+// We disable a few registers that cannot be encoded on instructions with a REX
+// prefix.
+const unsigned ExegesisX86Target::kUnavailableRegisters[4] = {X86::AH, X86::BH,
+                                                              X86::CH, X86::DH};
 } // namespace
 
 void ExegesisX86Target::addTargetSpecificPasses(
     llvm::PassManagerBase &PM) const {
   // Lowers FP pseudo-instructions, e.g. ABS_Fp32 -> ABS_F.
   PM.add(llvm::createX86FloatingPointStackifierPass());
 }
 

llvm/trunk/unittests/tools/llvm-exegesis/X86/TargetTest.cpp

public:
   Core2AvxTargetTest() : X86TargetTest("+avx") {}
 };
 
 class Core2Avx512TargetTest : public X86TargetTest {
 public:
   Core2Avx512TargetTest() : X86TargetTest("+avx512vl") {}
 };
 
+TEST_F(Core2TargetTest, NoHighByteRegs) {
+  EXPECT_TRUE(State.getRATC().reservedRegisters().test(X86::AH));
+}
+
 TEST_F(Core2TargetTest, SetFlags) {
   const unsigned Reg = llvm::X86::EFLAGS;
   EXPECT_THAT(
       setRegTo(Reg, APInt(64, 0x1111222233334444ULL)),
       ElementsAre(IsStackAllocate(8),
                   IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 0),
                   IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 4),
                   OpcodeIs(llvm::X86::POPF64)));