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Differential D59439

[ARM] Make sure to save/restore LR when we use tBfar.
ClosedPublic

Authored by efriedma on Mar 15 2019, 4:01 PM.

Details

Reviewers
samparker
t.p.northover
mstorsjo
SjoerdMeijer
olista01
Commits
rG2596e8b3e7ed: [ARM] Make sure to save/restore LR when we use tBfar.
rL356527: [ARM] Make sure to save/restore LR when we use tBfar.
Summary

This change does two things. One, it ensures compilation will abort instead of miscompiling if ARMFrameLowering::determineCalleeSaves chooses not to save LR in a case where it's necessary. Two, it changes the way we estimate the size of a function to be more conservative in the presence of constant pool entries and jump tables.

EstimateFunctionSizeInBytes probably still isn't really conservative enough, but I'm not sure how we can come up with a reliable estimate before constant islands runs.

The testcase is a little on the large side... suggestions welcome on how to shrink it.

Diff Detail

Repository
rL LLVM

Event Timeline

efriedma created this revision.Mar 15 2019, 4:01 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 15 2019, 4:01 PM
Herald added subscribers: jdoerfert, kristof.beyls, javed.absar. · View Herald Transcript
olista01 accepted this revision.Mar 18 2019, 6:14 AM
olista01 added a subscriber: olista01.

LGTM with one nit .

lib/Target/ARM/ARMMachineFunctionInfo.h
64 ↗(On Diff #190919)

s/LRSpilledForFarJump/LRSpilled/

This revision is now accepted and ready to land.Mar 18 2019, 6:14 AM
Closed by commit rL356527: [ARM] Make sure to save/restore LR when we use tBfar. (authored by efriedma). · Explain WhyMar 19 2019, 2:49 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
ARM/
3 lines
12 lines
7 lines
test/
CodeGen/
Thumb/
712 lines

Diff 191399

llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp

Show First 20 Lines • Show All 1,641 Lines • ▼ Show 20 Lines
/// Otherwise, add an intermediate branch instruction to a branch. /// Otherwise, add an intermediate branch instruction to a branch.
bool bool
ARMConstantIslands::fixupUnconditionalBr(ImmBranch &Br) { ARMConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {
MachineInstr *MI = Br.MI; MachineInstr *MI = Br.MI;
MachineBasicBlock *MBB = MI->getParent(); MachineBasicBlock *MBB = MI->getParent();
if (!isThumb1) if (!isThumb1)
llvm_unreachable("fixupUnconditionalBr is Thumb1 only!"); llvm_unreachable("fixupUnconditionalBr is Thumb1 only!");
if (!AFI->isLRSpilled())
report_fatal_error("underestimated function size");
// Use BL to implement far jump. // Use BL to implement far jump.
Br.MaxDisp = (1 << 21) * 2; Br.MaxDisp = (1 << 21) * 2;
MI->setDesc(TII->get(ARM::tBfar)); MI->setDesc(TII->get(ARM::tBfar));
BBInfo[MBB->getNumber()].Size += 2; BBInfo[MBB->getNumber()].Size += 2;
adjustBBOffsetsAfter(MBB); adjustBBOffsetsAfter(MBB);
HasFarJump = true; HasFarJump = true;
++NumUBrFixed; ++NumUBrFixed;
▲ Show 20 Lines • Show All 770 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp

Show All 23 Lines
#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h"
▲ Show 20 Lines • Show All 1,430 Lines • ▼ Show 20 Lines emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
&isARMArea2Register, 0); &isARMArea2Register, 0);
emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
&isARMArea1Register, 0); &isARMArea1Register, 0);
return true; return true;
} }
// FIXME: Make generic? // FIXME: Make generic?
static unsigned GetFunctionSizeInBytes(const MachineFunction &MF, static unsigned EstimateFunctionSizeInBytes(const MachineFunction &MF,
const ARMBaseInstrInfo &TII) { const ARMBaseInstrInfo &TII) {
unsigned FnSize = 0; unsigned FnSize = 0;
for (auto &MBB : MF) { for (auto &MBB : MF) {
for (auto &MI : MBB) for (auto &MI : MBB)
FnSize += TII.getInstSizeInBytes(MI); FnSize += TII.getInstSizeInBytes(MI);
} }
if (MF.getJumpTableInfo())
for (auto &Table: MF.getJumpTableInfo()->getJumpTables())
FnSize += Table.MBBs.size() * 4;
FnSize += MF.getConstantPool()->getConstants().size() * 4;
return FnSize; return FnSize;
} }
/// estimateRSStackSizeLimit - Look at each instruction that references stack /// estimateRSStackSizeLimit - Look at each instruction that references stack
/// frames and return the stack size limit beyond which some of these /// frames and return the stack size limit beyond which some of these
/// instructions will require a scratch register during their expansion later. /// instructions will require a scratch register during their expansion later.
// FIXME: Move to TII? // FIXME: Move to TII?
static unsigned estimateRSStackSizeLimit(MachineFunction &MF, static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
▲ Show 20 Lines • Show All 227 Lines • ▼ Show 20 Lines if (Spilled) {
UnspilledCS2GPRs.push_back(Reg); UnspilledCS2GPRs.push_back(Reg);
break; break;
} }
} }
} }
bool ForceLRSpill = false; bool ForceLRSpill = false;
if (!LRSpilled && AFI->isThumb1OnlyFunction()) { if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
unsigned FnSize = GetFunctionSizeInBytes(MF, TII); unsigned FnSize = EstimateFunctionSizeInBytes(MF, TII);
// Force LR to be spilled if the Thumb function size is > 2048. This enables // Force LR to be spilled if the Thumb function size is > 2048. This enables
// use of BL to implement far jump. If it turns out that it's not needed // use of BL to implement far jump. If it turns out that it's not needed
// then the branch fix up path will undo it. // then the branch fix up path will undo it.
if (FnSize >= (1 << 11)) { if (FnSize >= (1 << 11)) {
CanEliminateFrame = false; CanEliminateFrame = false;
ForceLRSpill = true; ForceLRSpill = true;
} }
} }
▲ Show 20 Lines • Show All 285 Lines • ▼ Show 20 Lines if (BigFrameOffsets && !ExtraCSSpill) {
} }
} }
} }
if (ForceLRSpill) { if (ForceLRSpill) {
SavedRegs.set(ARM::LR); SavedRegs.set(ARM::LR);
AFI->setLRIsSpilledForFarJump(true); AFI->setLRIsSpilledForFarJump(true);
} }
AFI->setLRIsSpilled(SavedRegs.test(ARM::LR));
} }
MachineBasicBlock::iterator ARMFrameLowering::eliminateCallFramePseudoInstr( MachineBasicBlock::iterator ARMFrameLowering::eliminateCallFramePseudoInstr(
MachineFunction &MF, MachineBasicBlock &MBB, MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const { MachineBasicBlock::iterator I) const {
const ARMBaseInstrInfo &TII = const ARMBaseInstrInfo &TII =
*static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
if (!hasReservedCallFrame(MF)) { if (!hasReservedCallFrame(MF)) {
▲ Show 20 Lines • Show All 475 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Linesclass ARMFunctionInfo : public MachineFunctionInfo {
/// RestoreSPFromFP - True if epilogue should restore SP from FP. Set by /// RestoreSPFromFP - True if epilogue should restore SP from FP. Set by
/// emitPrologue. /// emitPrologue.
bool RestoreSPFromFP = false; bool RestoreSPFromFP = false;
/// LRSpilledForFarJump - True if the LR register has been for spilled to /// LRSpilledForFarJump - True if the LR register has been for spilled to
/// enable far jump. /// enable far jump.
bool LRSpilledForFarJump = false; bool LRSpilledForFarJump = false;
/// LRSpilled - True if the LR register has been for spilled for
/// any reason, so it's legal to emit an ARM::tBfar (i.e. "bl").
bool LRSpilled = false;
/// FramePtrSpillOffset - If HasStackFrame, this records the frame pointer /// FramePtrSpillOffset - If HasStackFrame, this records the frame pointer
/// spill stack offset. /// spill stack offset.
unsigned FramePtrSpillOffset = 0; unsigned FramePtrSpillOffset = 0;
/// GPRCS1Offset, GPRCS2Offset, DPRCSOffset - Starting offset of callee saved /// GPRCS1Offset, GPRCS2Offset, DPRCSOffset - Starting offset of callee saved
/// register spills areas. For Mac OS X: /// register spills areas. For Mac OS X:
/// ///
/// GPR callee-saved (1) : r4, r5, r6, r7, lr /// GPR callee-saved (1) : r4, r5, r6, r7, lr
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Linespublic:
void setReturnRegsCount(unsigned s) { ReturnRegsCount = s; } void setReturnRegsCount(unsigned s) { ReturnRegsCount = s; }
bool hasStackFrame() const { return HasStackFrame; } bool hasStackFrame() const { return HasStackFrame; }
void setHasStackFrame(bool s) { HasStackFrame = s; } void setHasStackFrame(bool s) { HasStackFrame = s; }
bool shouldRestoreSPFromFP() const { return RestoreSPFromFP; } bool shouldRestoreSPFromFP() const { return RestoreSPFromFP; }
void setShouldRestoreSPFromFP(bool s) { RestoreSPFromFP = s; } void setShouldRestoreSPFromFP(bool s) { RestoreSPFromFP = s; }
bool isLRSpilled() const { return LRSpilled; }
void setLRIsSpilled(bool s) { LRSpilled = s; }
bool isLRSpilledForFarJump() const { return LRSpilledForFarJump; } bool isLRSpilledForFarJump() const { return LRSpilledForFarJump; }
void setLRIsSpilledForFarJump(bool s) { LRSpilledForFarJump = s; } void setLRIsSpilledForFarJump(bool s) { LRSpilledForFarJump = s; }
unsigned getFramePtrSpillOffset() const { return FramePtrSpillOffset; } unsigned getFramePtrSpillOffset() const { return FramePtrSpillOffset; }
void setFramePtrSpillOffset(unsigned o) { FramePtrSpillOffset = o; } void setFramePtrSpillOffset(unsigned o) { FramePtrSpillOffset = o; }
unsigned getNumAlignedDPRCS2Regs() const { return NumAlignedDPRCS2Regs; } unsigned getNumAlignedDPRCS2Regs() const { return NumAlignedDPRCS2Regs; }
void setNumAlignedDPRCS2Regs(unsigned n) { NumAlignedDPRCS2Regs = n; } void setNumAlignedDPRCS2Regs(unsigned n) { NumAlignedDPRCS2Regs = n; }
▲ Show 20 Lines • Show All 85 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Thumb/large-fn-switch.ll

; RUN: llc < %s | FileCheck %s
; Make sure we save/restore lr in the prologue of a function that's too large.
; CHECK: push {lr}
; CHECK: bl .LBB0_4
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv6m-unknown-unknown-eabi"
define dso_local i32 @a(i32 %x, i32* nocapture %p) {
entry:
switch i32 %x, label %return [
i32 0, label %GO2
i32 1, label %GO3
i32 999, label %GO3
i32 3, label %GO3
i32 998, label %GO3
i32 5, label %GO3
i32 6, label %GO2
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i32 8, label %GO2
i32 9, label %GO2
i32 10, label %GO2
i32 11, label %GO3
i32 996, label %GO3
i32 995, label %GO2
i32 993, label %GO3
i32 15, label %GO2
i32 16, label %GO3
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i32 18, label %GO3
i32 19, label %GO2
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i32 27, label %GO2
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i32 959, label %GO2
i32 958, label %GO3
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i32 89, label %GO3
i32 90, label %GO3
i32 956, label %GO3
i32 955, label %GO2
i32 93, label %GO2
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i32 95, label %GO3
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i32 134, label %GO3
i32 135, label %GO2
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i32 237, label %GO3
i32 238, label %GO3
i32 239, label %GO3
i32 240, label %GO3
i32 241, label %GO3
i32 242, label %GO2
i32 243, label %GO2
i32 901, label %GO2
i32 245, label %GO3
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i32 898, label %GO3
i32 251, label %GO2
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i32 255, label %GO2
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i32 259, label %GO3
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i32 262, label %GO3
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i32 264, label %GO2
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i32 267, label %GO2
i32 893, label %GO3
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i32 890, label %GO2
i32 273, label %GO3
i32 274, label %GO3
i32 888, label %GO3
i32 886, label %GO2
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i32 286, label %GO2
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i32 877, label %GO3
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i32 345, label %GO2
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i32 348, label %GO3
i32 846, label %GO3
i32 350, label %GO2
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i32 357, label %GO3
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i32 841, label %GO2
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i32 835, label %GO3
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i32 374, label %GO3
i32 375, label %GO2
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i32 831, label %GO2
i32 380, label %GO3
i32 381, label %GO2
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i32 383, label %GO2
i32 830, label %GO3
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i32 387, label %GO3
i32 388, label %GO3
i32 389, label %GO2
i32 390, label %GO3
i32 391, label %GO2
i32 392, label %GO2
i32 393, label %GO3
i32 824, label %GO3
i32 395, label %GO2
i32 396, label %GO3
i32 823, label %GO3
i32 398, label %GO3
i32 399, label %GO2
i32 400, label %GO2
i32 401, label %GO2
i32 822, label %GO2
i32 820, label %GO3
i32 404, label %GO3
i32 819, label %GO3
i32 406, label %GO2
i32 407, label %GO3
i32 408, label %GO2
i32 818, label %GO3
i32 817, label %GO3
i32 411, label %GO2
i32 412, label %GO2
i32 413, label %GO3
i32 414, label %GO3
i32 814, label %GO2
i32 813, label %GO3
i32 811, label %GO3
i32 810, label %GO3
i32 419, label %GO3
i32 420, label %GO3
i32 421, label %GO3
i32 809, label %GO2
i32 423, label %GO3
i32 424, label %GO3
i32 425, label %GO3
i32 808, label %GO3
i32 427, label %GO2
i32 807, label %GO3
i32 806, label %GO3
i32 430, label %GO2
i32 805, label %GO3
i32 432, label %GO2
i32 433, label %GO3
i32 804, label %GO3
i32 435, label %GO3
i32 802, label %GO2
i32 801, label %GO3
i32 800, label %GO2
i32 439, label %GO3
i32 440, label %GO2
i32 441, label %GO3
i32 442, label %GO2
i32 443, label %GO2
i32 799, label %GO2
i32 797, label %GO3
i32 446, label %GO3
i32 795, label %GO2
i32 794, label %GO2
i32 449, label %GO2
i32 450, label %GO2
i32 451, label %GO2
i32 452, label %GO3
i32 453, label %GO3
i32 454, label %GO3
i32 455, label %GO2
i32 456, label %GO3
i32 457, label %GO3
i32 793, label %GO3
i32 792, label %GO2
i32 460, label %GO2
i32 791, label %GO2
i32 462, label %GO2
i32 789, label %GO3
i32 785, label %GO2
i32 784, label %GO2
i32 783, label %GO2
i32 780, label %GO3
i32 468, label %GO3
i32 469, label %GO3
i32 470, label %GO2
i32 471, label %GO3
i32 472, label %GO3
i32 473, label %GO2
i32 779, label %GO2
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i32 476, label %GO3
i32 477, label %GO2
i32 777, label %GO3
i32 775, label %GO3
i32 480, label %GO2
i32 481, label %GO2
i32 774, label %GO2
i32 483, label %GO2
i32 484, label %GO3
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i32 487, label %GO2
i32 488, label %GO2
i32 489, label %GO3
i32 771, label %GO2
i32 770, label %GO3
i32 492, label %GO3
i32 493, label %GO2
i32 769, label %GO2
i32 495, label %GO2
i32 496, label %GO3
i32 497, label %GO3
i32 498, label %GO3
i32 766, label %GO2
i32 500, label %GO2
i32 501, label %GO3
i32 765, label %GO2
i32 503, label %GO3
i32 764, label %GO2
i32 505, label %GO3
i32 506, label %GO2
i32 507, label %GO3
i32 508, label %GO2
i32 509, label %GO3
i32 510, label %GO2
i32 511, label %GO3
i32 763, label %GO2
i32 761, label %GO2
i32 514, label %GO2
i32 515, label %GO3
i32 516, label %GO3
i32 760, label %GO2
i32 518, label %GO3
i32 519, label %GO3
i32 759, label %GO2
i32 521, label %GO2
i32 522, label %GO3
i32 523, label %GO3
i32 758, label %GO2
i32 525, label %GO3
i32 757, label %GO3
i32 756, label %GO2
i32 528, label %GO3
i32 529, label %GO2
i32 530, label %GO2
i32 531, label %GO3
i32 755, label %GO2
i32 533, label %GO3
i32 754, label %GO3
i32 535, label %GO2
i32 536, label %GO3
i32 537, label %GO3
i32 538, label %GO3
i32 539, label %GO3
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i32 753, label %GO2
i32 542, label %GO2
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i32 544, label %GO2
i32 545, label %GO2
i32 546, label %GO2
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i32 550, label %GO3
i32 750, label %GO3
i32 552, label %GO2
i32 553, label %GO2
i32 749, label %GO3
i32 555, label %GO2
i32 556, label %GO3
i32 748, label %GO3
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i32 744, label %GO2
i32 560, label %GO3
i32 741, label %GO3
i32 562, label %GO3
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i32 564, label %GO3
i32 565, label %GO3
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i32 737, label %GO3
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i32 572, label %GO2
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i32 575, label %GO3
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i32 581, label %GO2
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i32 594, label %GO3
i32 595, label %GO2
i32 596, label %GO2
i32 597, label %GO2
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i32 599, label %GO2
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i32 601, label %GO2
i32 602, label %GO3
i32 603, label %GO3
i32 604, label %GO3
i32 605, label %GO3
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i32 607, label %GO2
i32 608, label %GO2
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i32 712, label %GO3
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i32 702, label %GO2
i32 701, label %GO2
i32 652, label %GO2
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i32 655, label %GO3
i32 699, label %GO3
i32 698, label %GO2
i32 658, label %GO2
i32 659, label %GO2
i32 660, label %GO2
i32 661, label %GO2
i32 696, label %GO3
i32 695, label %GO3
i32 664, label %GO3
i32 665, label %GO3
i32 666, label %GO3
i32 667, label %GO2
i32 668, label %GO2
i32 669, label %GO3
i32 693, label %GO3
i32 671, label %GO3
i32 692, label %GO3
i32 673, label %GO3
i32 674, label %GO3
i32 675, label %GO2
i32 676, label %GO3
i32 677, label %GO2
i32 691, label %GO3
i32 679, label %GO3
i32 680, label %GO3
i32 681, label %GO3
i32 690, label %GO3
i32 689, label %GO3
i32 688, label %GO2
i32 685, label %GO3
i32 686, label %GO2
]
GO2:
br label %return
GO3:
store i32 3, i32* %p, align 4
br label %return
return:
%retval.0 = phi i32 [ 3, %GO3 ], [ 2, %GO2 ], [ 1, %entry ]
ret i32 %retval.0
}