[MIPS GlobalISel] Improve selection of constants

[Petar.Avramovic]

Summary

Certain 32 bit constants can be generated with a single instruction
instead of two. Implement materialize32BitImm function for MIPS32.

[atanasyan]

Nice. LGTM

lib/Target/Mips/MipsInstructionSelector.cpp

public:
   MipsInstructionSelector(const MipsTargetMachine &TM, const MipsSubtarget &STI,
                           const MipsRegisterBankInfo &RBI);
 
   bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
   static const char *getName() { return DEBUG_TYPE; }
 
 private:
   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+  bool materialize32BitImm(unsigned DestReg, APInt Imm,
+                           MachineIRBuilder &B) const;
 
   const MipsTargetMachine &TM;
   const MipsSubtarget &STI;
   const MipsInstrInfo &TII;
   const MipsRegisterInfo &TRI;
   const MipsRegisterBankInfo &RBI;
 
 #define GET_GLOBALISEL_PREDICATES_DECL
static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
   if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
     LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
                       << " operand\n");
     return false;
   }
   return true;
 }
 
+bool MipsInstructionSelector::materialize32BitImm(unsigned DestReg, APInt Imm,
+                                                  MachineIRBuilder &B) const {
+  assert(Imm.getBitWidth() == 32 && "Unsupported immediate size.");
+  // Ori zero extendeds immediate. Used for values with zeros in high 16 bits.
+  if (Imm.getHiBits(16).isNullValue()) {
+    MachineInstr *Inst = B.buildInstr(Mips::ORi, {DestReg}, {Mips::ZERO})
+                             .addImm(Imm.getLoBits(16).getLimitedValue());
+    return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
+  }
+  // Lui places immediate in high 16 bits and sets low 16 bits to zero.
+  if (Imm.getLoBits(16).isNullValue()) {
+    MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {})
+                             .addImm(Imm.getHiBits(16).getLimitedValue());
+    return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
+  }
+  // ADDiu sign extends immediate. Used for values with 1s in high 17 bits.
+  if (Imm.isSignedIntN(16)) {
+    MachineInstr *Inst = B.buildInstr(Mips::ADDiu, {DestReg}, {Mips::ZERO})
+                             .addImm(Imm.getLoBits(16).getLimitedValue());
+    return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
+  }
+  // Values that cannot be materialized with single immediate instruction.
+  unsigned LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass);
+  MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {})
+                          .addImm(Imm.getHiBits(16).getLimitedValue());
+  MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg})
+                          .addImm(Imm.getLoBits(16).getLimitedValue());
+  if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
+    return false;
+  if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
+    return false;
+  return true;
+}
+
 /// Returning Opc indicates that we failed to select MIPS instruction opcode.
 static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned MemSizeInBytes) {
   if (Opc == TargetOpcode::G_STORE)
     switch (MemSizeInBytes) {
     case 4:
       return Mips::SW;
     case 2:
       return Mips::SH;
case G_SELECT: {
     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I))
              .add(I.getOperand(0))
              .add(I.getOperand(2))
              .add(I.getOperand(1))
              .add(I.getOperand(3));
     break;
   }
   case G_CONSTANT: {
-    int Imm = I.getOperand(1).getCImm()->getValue().getLimitedValue();
-    unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
-    MachineInstr *LUi, *ORi;
-
-    LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
-              .addDef(LUiReg)
-              .addImm(Imm >> 16);
-
-    ORi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ORi))
-              .addDef(I.getOperand(0).getReg())
-              .addUse(LUiReg)
-              .addImm(Imm & 0xFFFF);
-
-    if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
-      return false;
-    if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
+    MachineIRBuilder B(I);
+    if (!materialize32BitImm(I.getOperand(0).getReg(),
+                             I.getOperand(1).getCImm()->getValue(), B))
       return false;
 
     I.eraseFromParent();
     return true;
   }
   case G_GLOBAL_VALUE: {
     if (MF.getTarget().isPositionIndependent())
       return false;

test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir

 body:             |
   ; MIPS32-LABEL: name: Conditional_branch
   ; MIPS32: bb.0 (%ir-block.0):
   ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; MIPS32:   liveins: $a0, $a1, $a2
   ; MIPS32:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
   ; MIPS32:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
   ; MIPS32:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
-  ; MIPS32:   [[LUi:%[0-9]+]]:gpr32 = LUi 0
-  ; MIPS32:   [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+  ; MIPS32:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
   ; MIPS32:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
   ; MIPS32:   BNE [[AND]], $zero, %bb.1, implicit-def $at
   ; MIPS32:   J %bb.2, implicit-def $at
   ; MIPS32: bb.1.if.then:
   ; MIPS32:   $v0 = COPY [[COPY1]]
   ; MIPS32:   RetRA implicit $v0
   ; MIPS32: bb.2.if.else:
   ; MIPS32:   $v0 = COPY [[COPY2]]

test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @_0xABCD0000() {entry: ret void}
+  define void @_0x00008000() {entry: ret void}
+  define void @_0xFFFFFFF6() {entry: ret void}
+  define void @_0x0A0B0C0D() {entry: ret void}
+
+...
+---
+name:            _0xABCD0000
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    ; MIPS32-LABEL: name: _0xABCD0000
+    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 43981
+    ; MIPS32: $v0 = COPY [[LUi]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = G_CONSTANT i32 -1412628480
+    $v0 = COPY %0(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            _0x00008000
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    ; MIPS32-LABEL: name: _0x00008000
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 32768
+    ; MIPS32: $v0 = COPY [[ORi]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = G_CONSTANT i32 32768
+    $v0 = COPY %0(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            _0xFFFFFFF6
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    ; MIPS32-LABEL: name: _0xFFFFFFF6
+    ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65526
+    ; MIPS32: $v0 = COPY [[ADDiu]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = G_CONSTANT i32 -10
+    $v0 = COPY %0(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            _0x0A0B0C0D
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    ; MIPS32-LABEL: name: _0x0A0B0C0D
+    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 2571
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 3085
+    ; MIPS32: $v0 = COPY [[ORi]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = G_CONSTANT i32 168496141
+    $v0 = COPY %0(s32)
+    RetRA implicit $v0
+
+...
+

test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir

 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     ; MIPS32-LABEL: name: main
     ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @.str
     ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @.str
     ; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi 18838
     ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi1]], 722
-    ; MIPS32: [[LUi2:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi [[LUi2]], 0
+    ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 0
     ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
     ; MIPS32: $a0 = COPY [[ADDiu]]
     ; MIPS32: $a1 = COPY [[ORi]]
     ; MIPS32: JAL @printf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
     ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
     ; MIPS32: $v0 = COPY [[ORi1]]
     ; MIPS32: RetRA implicit $v0
     %2:gprb(p0) = G_GLOBAL_VALUE @.str

test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir

bb.1.entry:
     liveins: $a0, $a1
 
     ; MIPS32-LABEL: name: eq
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
     ; MIPS32: [[SLTiu:%[0-9]+]]:gpr32 = SLTiu [[XOR]], 1
-    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
     ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTiu]], [[ORi]]
     ; MIPS32: $v0 = COPY [[AND]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(eq), %0(s32), %1
     %5:gprb(s32) = G_CONSTANT i32 1
     %6:gprb(s32) = COPY %4(s32)
bb.1.entry:
     liveins: $a0, $a1
 
     ; MIPS32-LABEL: name: ne
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]]
-    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
     ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]]
     ; MIPS32: $v0 = COPY [[AND]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(ne), %0(s32), %1
     %5:gprb(s32) = G_CONSTANT i32 1
     %6:gprb(s32) = COPY %4(s32)
body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
     ; MIPS32-LABEL: name: sgt
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
-    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
     ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLT]], [[ORi]]
     ; MIPS32: $v0 = COPY [[AND]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(sgt), %0(s32), %1
     %5:gprb(s32) = G_CONSTANT i32 1
     %6:gprb(s32) = COPY %4(s32)
bb.1.entry:
     liveins: $a0, $a1
 
     ; MIPS32-LABEL: name: sge
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
     ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
-    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
     ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
     ; MIPS32: $v0 = COPY [[AND]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(sge), %0(s32), %1
     %5:gprb(s32) = G_CONSTANT i32 1
     %6:gprb(s32) = COPY %4(s32)
body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
     ; MIPS32-LABEL: name: slt
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
-    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
     ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLT]], [[ORi]]
     ; MIPS32: $v0 = COPY [[AND]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(slt), %0(s32), %1
     %5:gprb(s32) = G_CONSTANT i32 1
     %6:gprb(s32) = COPY %4(s32)
bb.1.entry:
     liveins: $a0, $a1
 
     ; MIPS32-LABEL: name: sle
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
     ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
-    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
     ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
     ; MIPS32: $v0 = COPY [[AND]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(sle), %0(s32), %1
     %5:gprb(s32) = G_CONSTANT i32 1
     %6:gprb(s32) = COPY %4(s32)
body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
     ; MIPS32-LABEL: name: ugt
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]]
-    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
     ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]]
     ; MIPS32: $v0 = COPY [[AND]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(ugt), %0(s32), %1
     %5:gprb(s32) = G_CONSTANT i32 1
     %6:gprb(s32) = COPY %4(s32)
bb.1.entry:
     liveins: $a0, $a1
 
     ; MIPS32-LABEL: name: uge
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY]], [[COPY1]]
     ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1
-    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
     ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
     ; MIPS32: $v0 = COPY [[AND]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(uge), %0(s32), %1
     %5:gprb(s32) = G_CONSTANT i32 1
     %6:gprb(s32) = COPY %4(s32)
body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
     ; MIPS32-LABEL: name: ult
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY]], [[COPY1]]
-    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
     ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]]
     ; MIPS32: $v0 = COPY [[AND]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(ult), %0(s32), %1
     %5:gprb(s32) = G_CONSTANT i32 1
     %6:gprb(s32) = COPY %4(s32)
bb.1.entry:
     liveins: $a0, $a1
 
     ; MIPS32-LABEL: name: ule
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]]
     ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1
-    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
     ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
     ; MIPS32: $v0 = COPY [[AND]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(ule), %0(s32), %1
     %5:gprb(s32) = G_CONSTANT i32 1
     %6:gprb(s32) = COPY %4(s32)
     %3:gprb(s32) = G_AND %6, %5
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...

test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir

bb.1 (%ir-block.0):
     ; MIPS32: liveins: $a0, $a1, $a2, $a3
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
     ; MIPS32: [[COPY3:%[0-9]+]]:gpr32 = COPY $a3
     ; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
     ; MIPS32: [[PseudoMULTu:%[0-9]+]]:acc64 = PseudoMULTu [[COPY]], [[COPY1]]
     ; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoMULTu]]
-    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 0
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
     ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[PseudoMFHI]], [[ORi]]
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]]
-    ; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi [[LUi1]], 1
+    ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 1
     ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi1]]
     ; MIPS32: SB [[AND]], [[COPY3]], 0 :: (store 1 into %ir.pcarry_flag)
     ; MIPS32: SW [[MUL]], [[COPY2]], 0 :: (store 4 into %ir.pmul)
     ; MIPS32: RetRA
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %2:gprb(p0) = COPY $a2
     %3:gprb(p0) = COPY $a3

test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir

 body:             |
   ; MIPS32-LABEL: name: test_i32
   ; MIPS32: bb.0.entry:
   ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; MIPS32:   liveins: $a0, $a1, $a2
   ; MIPS32:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
   ; MIPS32:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
   ; MIPS32:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
-  ; MIPS32:   [[LUi:%[0-9]+]]:gpr32 = LUi 0
-  ; MIPS32:   [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+  ; MIPS32:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
   ; MIPS32:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
   ; MIPS32:   BNE [[AND]], $zero, %bb.1, implicit-def $at
   ; MIPS32:   J %bb.2, implicit-def $at
   ; MIPS32: bb.1.cond.true:
   ; MIPS32:   successors: %bb.3(0x80000000)
   ; MIPS32:   J %bb.3, implicit-def $at
   ; MIPS32: bb.2.cond.false:
   ; MIPS32:   successors: %bb.3(0x80000000)

test/CodeGen/Mips/GlobalISel/instruction-select/select.mir

body:             |
   bb.1.entry:
     liveins: $a0, $a1, $a2
 
     ; MIPS32-LABEL: name: select_i32
     ; MIPS32: liveins: $a0, $a1, $a2
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
-    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
     ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
     ; MIPS32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
     ; MIPS32: $v0 = COPY [[MOVN_I_I]]
     ; MIPS32: RetRA implicit $v0
     %3:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %2:gprb(s32) = COPY $a2
     %6:gprb(s32) = G_CONSTANT i32 1
body:             |
   bb.1.entry:
     liveins: $a0, $a1, $a2
 
     ; MIPS32-LABEL: name: select_ptr
     ; MIPS32: liveins: $a0, $a1, $a2
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
-    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
     ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
     ; MIPS32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
     ; MIPS32: $v0 = COPY [[MOVN_I_I]]
     ; MIPS32: RetRA implicit $v0
     %3:gprb(s32) = COPY $a0
     %1:gprb(p0) = COPY $a1
     %2:gprb(p0) = COPY $a2
     %6:gprb(s32) = G_CONSTANT i32 1
     %7:gprb(s32) = COPY %3(s32)
     %5:gprb(s32) = G_AND %7, %6
     %4:gprb(p0) = G_SELECT %5(s32), %1, %2
     $v0 = COPY %4(p0)
     RetRA implicit $v0
 
 ...

test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir

bb.1.entry:
     ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
     ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
     ; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
     ; MIPS32: $a0 = COPY [[COPY]]
     ; MIPS32: $a1 = COPY [[COPY1]]
     ; MIPS32: $a2 = COPY [[COPY2]]
     ; MIPS32: $a3 = COPY [[COPY3]]
     ; MIPS32: [[COPY4:%[0-9]+]]:gpr32 = COPY $sp
-    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 16
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
     ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY4]], [[ORi]]
     ; MIPS32: SW [[LW]], [[ADDu]], 0 :: (store 4 into stack + 16)
     ; MIPS32: JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
     ; MIPS32: [[COPY5:%[0-9]+]]:gpr32 = COPY $v0
     ; MIPS32: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
     ; MIPS32: $v0 = COPY [[COPY5]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0

test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll

entry:
   %add = add i8 %b, %a
   ret i8 %add
 }
 
 define zeroext i8 @add_i8_zext(i8 zeroext %a, i8 zeroext %b) {
 ; MIPS32-LABEL: add_i8_zext:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addu $4, $5, $4
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 255
+; MIPS32-NEXT:    ori $5, $zero, 255
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %add = add i8 %b, %a
   ret i8 %add
 }
 
entry:
   %add = add i16 %b, %a
   ret i16 %add
 }
 
 define zeroext i16 @add_i16_zext(i16 zeroext %a, i16 zeroext %b) {
 ; MIPS32-LABEL: add_i16_zext:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addu $4, $5, $4
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 65535
+; MIPS32-NEXT:    ori $5, $zero, 65535
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %add = add i16 %b, %a
   ret i16 %add
 }
 
 define i16 @add_i16_aext(i16 %a, i16 %b) {
 ; MIPS32-LABEL: add_i16_aext:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addu $2, $5, $4
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %add = add i16 %b, %a
   ret i16 %add
 }
 
 define i64 @add_i64(i64 %a, i64 %b) {
 ; MIPS32-LABEL: add_i64:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 0
+; MIPS32-NEXT:    ori $1, $zero, 0
 ; MIPS32-NEXT:    addu $4, $6, $4
-; MIPS32-NEXT:    lui $2, 0
-; MIPS32-NEXT:    ori $2, $2, 1
+; MIPS32-NEXT:    ori $2, $zero, 1
 ; MIPS32-NEXT:    and $1, $1, $2
 ; MIPS32-NEXT:    addu $1, $4, $1
 ; MIPS32-NEXT:    sltu $2, $1, $6
 ; MIPS32-NEXT:    addu $4, $7, $5
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $2, $2, $5
 ; MIPS32-NEXT:    addu $3, $4, $2
 ; MIPS32-NEXT:    move $2, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %add = add i64 %b, %a
   ret i64 %add
 }
 
 define i128 @add_i128(i128 %a, i128 %b) {
 ; MIPS32-LABEL: add_i128:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -8
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 8
 ; MIPS32-NEXT:    addiu $1, $sp, 24
 ; MIPS32-NEXT:    lw $1, 0($1)
 ; MIPS32-NEXT:    addiu $2, $sp, 28
 ; MIPS32-NEXT:    lw $2, 0($2)
 ; MIPS32-NEXT:    addiu $3, $sp, 32
 ; MIPS32-NEXT:    lw $3, 0($3)
 ; MIPS32-NEXT:    addiu $8, $sp, 36
 ; MIPS32-NEXT:    lw $8, 0($8)
-; MIPS32-NEXT:    lui $9, 0
-; MIPS32-NEXT:    ori $9, $9, 0
+; MIPS32-NEXT:    ori $9, $zero, 0
 ; MIPS32-NEXT:    addu $4, $1, $4
-; MIPS32-NEXT:    lui $10, 0
-; MIPS32-NEXT:    ori $10, $10, 1
+; MIPS32-NEXT:    ori $10, $zero, 1
 ; MIPS32-NEXT:    and $9, $9, $10
 ; MIPS32-NEXT:    addu $4, $4, $9
 ; MIPS32-NEXT:    sltu $1, $4, $1
 ; MIPS32-NEXT:    addu $5, $2, $5
-; MIPS32-NEXT:    lui $9, 0
-; MIPS32-NEXT:    ori $9, $9, 1
+; MIPS32-NEXT:    ori $9, $zero, 1
 ; MIPS32-NEXT:    and $1, $1, $9
 ; MIPS32-NEXT:    addu $1, $5, $1
 ; MIPS32-NEXT:    sltu $2, $1, $2
 ; MIPS32-NEXT:    addu $5, $3, $6
-; MIPS32-NEXT:    lui $6, 0
-; MIPS32-NEXT:    ori $6, $6, 1
+; MIPS32-NEXT:    ori $6, $zero, 1
 ; MIPS32-NEXT:    and $2, $2, $6
 ; MIPS32-NEXT:    addu $2, $5, $2
 ; MIPS32-NEXT:    sltu $3, $2, $3
 ; MIPS32-NEXT:    addu $5, $8, $7
-; MIPS32-NEXT:    lui $6, 0
-; MIPS32-NEXT:    ori $6, $6, 1
+; MIPS32-NEXT:    ori $6, $zero, 1
 ; MIPS32-NEXT:    and $3, $3, $6
 ; MIPS32-NEXT:    addu $5, $5, $3
 ; MIPS32-NEXT:    sw $2, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    move $2, $4
 ; MIPS32-NEXT:    move $3, $1
 ; MIPS32-NEXT:    lw $4, 4($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    addiu $sp, $sp, 8
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %add = add i128 %b, %a
   ret i128 %add
 }
 
 declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
 define void @uadd_with_overflow(i32 %lhs, i32 %rhs, i32* %padd, i1* %pcarry_flag) {
 ; MIPS32-LABEL: uadd_with_overflow:
 ; MIPS32:       # %bb.0:
 ; MIPS32-NEXT:    addu $4, $4, $5
 ; MIPS32-NEXT:    sltu $5, $4, $5
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    ori $1, $zero, 1
 ; MIPS32-NEXT:    and $1, $5, $1
 ; MIPS32-NEXT:    sb $1, 0($7)
 ; MIPS32-NEXT:    sw $4, 0($6)
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
   %res = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %lhs, i32 %rhs)
   %carry_flag = extractvalue { i32, i1 } %res, 1
   %add = extractvalue { i32, i1 } %res, 0
   store i1 %carry_flag, i1* %pcarry_flag
   store i32 %add, i32* %padd
   ret void
 }

test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll

block:
   br label %end
 }
 
 define i32 @Conditional_branch(i1 %cond, i32 %a, i32 %b) {
 ; MIPS32-LABEL: Conditional_branch:
 ; MIPS32:       # %bb.0:
 ; MIPS32-NEXT:    addiu $sp, $sp, -8
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 8
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    ori $1, $zero, 1
 ; MIPS32-NEXT:    and $1, $4, $1
 ; MIPS32-NEXT:    sw $5, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 0($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $1, $BB1_2
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1:
 ; MIPS32-NEXT:    j $BB1_3
 ; MIPS32-NEXT:    nop

test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
 
 define i64 @any_i64() {
 ; MIPS32-LABEL: any_i64:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $2, $1, 0
-; MIPS32-NEXT:    lui $1, 32768
-; MIPS32-NEXT:    ori $3, $1, 0
+; MIPS32-NEXT:    ori $2, $zero, 0
+; MIPS32-NEXT:    lui $3, 32768
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   ret i64 -9223372036854775808
 }
 
 define i32 @any_i32() {
 ; MIPS32-LABEL: any_i32:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 32768
-; MIPS32-NEXT:    ori $2, $1, 0
+; MIPS32-NEXT:    lui $2, 32768
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   ret i32 -2147483648
 }
 
 define signext i16 @signed_i16() {
 ; MIPS32-LABEL: signed_i16:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 65535
-; MIPS32-NEXT:    ori $1, $1, 32768
+; MIPS32-NEXT:    addiu $1, $zero, 32768
 ; MIPS32-NEXT:    sll $1, $1, 16
 ; MIPS32-NEXT:    sra $2, $1, 16
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   ret i16 -32768
 }
 
 define signext i8 @signed_i8() {
 ; MIPS32-LABEL: signed_i8:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 65535
-; MIPS32-NEXT:    ori $1, $1, 65408
+; MIPS32-NEXT:    addiu $1, $zero, 65408
 ; MIPS32-NEXT:    sll $1, $1, 24
 ; MIPS32-NEXT:    sra $2, $1, 24
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   ret i8 -128
 }
 
 define zeroext i16 @unsigned_i16() {
 ; MIPS32-LABEL: unsigned_i16:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 65535
-; MIPS32-NEXT:    ori $1, $1, 32768
-; MIPS32-NEXT:    lui $2, 0
-; MIPS32-NEXT:    ori $2, $2, 65535
+; MIPS32-NEXT:    addiu $1, $zero, 32768
+; MIPS32-NEXT:    ori $2, $zero, 65535
 ; MIPS32-NEXT:    and $2, $1, $2
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   ret i16 -32768
 }
 
 define zeroext i8 @unsigned_i8() {
 ; MIPS32-LABEL: unsigned_i8:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 65535
-; MIPS32-NEXT:    ori $1, $1, 65408
-; MIPS32-NEXT:    lui $2, 0
-; MIPS32-NEXT:    ori $2, $2, 255
+; MIPS32-NEXT:    addiu $1, $zero, 65408
+; MIPS32-NEXT:    ori $2, $zero, 255
 ; MIPS32-NEXT:    and $2, $1, $2
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   ret i8 -128
 }
 
 define zeroext i1 @i1_true() {
 ; MIPS32-LABEL: i1_true:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 65535
-; MIPS32-NEXT:    ori $1, $1, 65535
-; MIPS32-NEXT:    lui $2, 0
-; MIPS32-NEXT:    ori $2, $2, 1
+; MIPS32-NEXT:    addiu $1, $zero, 65535
+; MIPS32-NEXT:    ori $2, $zero, 1
 ; MIPS32-NEXT:    and $2, $1, $2
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   ret i1 true
 }
 
 define zeroext i1 @i1_false() {
 ; MIPS32-LABEL: i1_false:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 0
-; MIPS32-NEXT:    lui $2, 0
-; MIPS32-NEXT:    ori $2, $2, 1
+; MIPS32-NEXT:    ori $1, $zero, 0
+; MIPS32-NEXT:    ori $2, $zero, 1
 ; MIPS32-NEXT:    and $2, $1, $2
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   ret i1 false
 }
+
+define i32 @_0xABCD0000() {
+; MIPS32-LABEL: _0xABCD0000:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lui $2, 43981
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  ret i32 -1412628480
+}
+
+define i32 @_0x00008000() {
+; MIPS32-LABEL: _0x00008000:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    ori $2, $zero, 32768
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  ret i32 32768
+}
+
+define i32 @_0xFFFFFFF6() {
+; MIPS32-LABEL: _0xFFFFFFF6:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $2, $zero, 65526
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  ret i32 -10
+}
+
+define i32 @_0x0A0B0C0D() {
+; MIPS32-LABEL: _0x0A0B0C0D:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lui $1, 2571
+; MIPS32-NEXT:    ori $2, $1, 3085
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  ret i32 168496141
+}

test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
 
 @.str = private unnamed_addr constant [11 x i8] c"hello %d \0A\00"
 
 define i32 @main() {
 ; MIPS32-LABEL: main:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -24
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 24
 ; MIPS32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    .cfi_offset 31, -4
 ; MIPS32-NEXT:    lui $1, %hi($.str)
 ; MIPS32-NEXT:    addiu $4, $1, %lo($.str)
 ; MIPS32-NEXT:    lui $1, 18838
 ; MIPS32-NEXT:    ori $5, $1, 722
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $2, $1, 0
+; MIPS32-NEXT:    ori $2, $zero, 0
 ; MIPS32-NEXT:    sw $2, 16($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    jal printf
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:    lw $1, 16($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    move $2, $1
 ; MIPS32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    addiu $sp, $sp, 24
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i32 signext 1234567890)
   ret i32 0
 }
 
 declare i32 @printf(i8*, ...)
 

test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
 
 define i32 @eq(i32 %a, i32 %b){
 ; MIPS32-LABEL: eq:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    xor $4, $4, $5
 ; MIPS32-NEXT:    sltiu $4, $4, 1
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp eq i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @ne(i32 %a, i32 %b) {
 ; MIPS32-LABEL: ne:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    xor $4, $4, $5
 ; MIPS32-NEXT:    sltu $4, $zero, $4
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ne i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @sgt(i32 %a, i32 %b) {
 ; MIPS32-LABEL: sgt:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    slt $4, $5, $4
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp sgt i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @sge(i32 %a, i32 %b) {
 ; MIPS32-LABEL: sge:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    slt $4, $4, $5
 ; MIPS32-NEXT:    xori $4, $4, 1
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp sge i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @slt(i32 %a, i32 %b) {
 ; MIPS32-LABEL: slt:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    slt $4, $4, $5
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp slt i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @sle(i32 %a, i32 %b) {
 ; MIPS32-LABEL: sle:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    slt $4, $5, $4
 ; MIPS32-NEXT:    xori $4, $4, 1
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp sle i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @ugt(i32 %a, i32 %b) {
 ; MIPS32-LABEL: ugt:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    sltu $4, $5, $4
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ugt i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @uge(i32 %a, i32 %b) {
 ; MIPS32-LABEL: uge:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    sltu $4, $4, $5
 ; MIPS32-NEXT:    xori $4, $4, 1
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp uge i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @ult(i32 %a, i32 %b) {
 ; MIPS32-LABEL: ult:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    sltu $4, $4, $5
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ult i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i32 @ule(i32 %a, i32 %b) {
 ; MIPS32-LABEL: ule:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    sltu $4, $5, $4
 ; MIPS32-NEXT:    xori $4, $4, 1
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ule i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }

test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll

entry:
   %mul = mul i8 %b, %a
   ret i8 %mul
 }
 
 define zeroext i8 @mul_i8_zext(i8 zeroext %a, i8 zeroext %b) {
 ; MIPS32-LABEL: mul_i8_zext:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    mul $4, $5, $4
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 255
+; MIPS32-NEXT:    ori $5, $zero, 255
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %mul = mul i8 %b, %a
   ret i8 %mul
 }
 
entry:
   %mul = mul i16 %b, %a
   ret i16 %mul
 }
 
 define zeroext i16 @mul_i16_zext(i16 zeroext %a, i16 zeroext %b) {
 ; MIPS32-LABEL: mul_i16_zext:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    mul $4, $5, $4
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 65535
+; MIPS32-NEXT:    ori $5, $zero, 65535
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %mul = mul i16 %b, %a
   ret i16 %mul
 }
 

 ; MIPS32-NEXT:    lw $8, 0($8)
 ; MIPS32-NEXT:    mul $9, $1, $4
 ; MIPS32-NEXT:    mul $10, $2, $4
 ; MIPS32-NEXT:    mul $11, $1, $5
 ; MIPS32-NEXT:    multu $1, $4
 ; MIPS32-NEXT:    mfhi $12
 ; MIPS32-NEXT:    addu $10, $10, $11
 ; MIPS32-NEXT:    sltu $11, $10, $11
-; MIPS32-NEXT:    lui $13, 0
-; MIPS32-NEXT:    ori $13, $13, 1
+; MIPS32-NEXT:    ori $13, $zero, 1
 ; MIPS32-NEXT:    and $11, $11, $13
 ; MIPS32-NEXT:    addu $10, $10, $12
 ; MIPS32-NEXT:    sltu $12, $10, $12
-; MIPS32-NEXT:    lui $13, 0
-; MIPS32-NEXT:    ori $13, $13, 1
+; MIPS32-NEXT:    ori $13, $zero, 1
 ; MIPS32-NEXT:    and $12, $12, $13
 ; MIPS32-NEXT:    addu $11, $11, $12
 ; MIPS32-NEXT:    mul $12, $3, $4
 ; MIPS32-NEXT:    mul $13, $2, $5
 ; MIPS32-NEXT:    mul $14, $1, $6
 ; MIPS32-NEXT:    multu $2, $4
 ; MIPS32-NEXT:    mfhi $15
 ; MIPS32-NEXT:    multu $1, $5
 ; MIPS32-NEXT:    mfhi $24
 ; MIPS32-NEXT:    addu $12, $12, $13
 ; MIPS32-NEXT:    sltu $13, $12, $13
-; MIPS32-NEXT:    lui $25, 0
-; MIPS32-NEXT:    ori $25, $25, 1
+; MIPS32-NEXT:    ori $25, $zero, 1
 ; MIPS32-NEXT:    and $13, $13, $25
 ; MIPS32-NEXT:    addu $12, $12, $14
 ; MIPS32-NEXT:    sltu $14, $12, $14
-; MIPS32-NEXT:    lui $25, 0
-; MIPS32-NEXT:    ori $25, $25, 1
+; MIPS32-NEXT:    ori $25, $zero, 1
 ; MIPS32-NEXT:    and $14, $14, $25
 ; MIPS32-NEXT:    addu $13, $13, $14
 ; MIPS32-NEXT:    addu $12, $12, $15
 ; MIPS32-NEXT:    sltu $14, $12, $15
-; MIPS32-NEXT:    lui $15, 0
-; MIPS32-NEXT:    ori $15, $15, 1
+; MIPS32-NEXT:    ori $15, $zero, 1
 ; MIPS32-NEXT:    and $14, $14, $15
 ; MIPS32-NEXT:    addu $13, $13, $14
 ; MIPS32-NEXT:    addu $12, $12, $24
 ; MIPS32-NEXT:    sltu $14, $12, $24
-; MIPS32-NEXT:    lui $15, 0
-; MIPS32-NEXT:    ori $15, $15, 1
+; MIPS32-NEXT:    ori $15, $zero, 1
 ; MIPS32-NEXT:    and $14, $14, $15
 ; MIPS32-NEXT:    addu $13, $13, $14
 ; MIPS32-NEXT:    addu $12, $12, $11
 ; MIPS32-NEXT:    sltu $11, $12, $11
-; MIPS32-NEXT:    lui $14, 0
-; MIPS32-NEXT:    ori $14, $14, 1
+; MIPS32-NEXT:    ori $14, $zero, 1
 ; MIPS32-NEXT:    and $11, $11, $14
 ; MIPS32-NEXT:    addu $11, $13, $11
 ; MIPS32-NEXT:    mul $8, $8, $4
 ; MIPS32-NEXT:    mul $13, $3, $5
 ; MIPS32-NEXT:    mul $14, $2, $6
 ; MIPS32-NEXT:    mul $7, $1, $7
 ; MIPS32-NEXT:    multu $3, $4
 ; MIPS32-NEXT:    mfhi $3

 
 declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
 define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) {
 ; MIPS32-LABEL: umul_with_overflow:
 ; MIPS32:       # %bb.0:
 ; MIPS32-NEXT:    mul $1, $4, $5
 ; MIPS32-NEXT:    multu $4, $5
 ; MIPS32-NEXT:    mfhi $4
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 0
+; MIPS32-NEXT:    ori $5, $zero, 0
 ; MIPS32-NEXT:    xor $4, $4, $5
 ; MIPS32-NEXT:    sltu $4, $zero, $4
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $4, $4, $5
 ; MIPS32-NEXT:    sb $4, 0($7)
 ; MIPS32-NEXT:    sw $1, 0($6)
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
   %res = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %lhs, i32 %rhs)
   %carry_flag = extractvalue { i32, i1 } %res, 1
   %mul = extractvalue { i32, i1 } %res, 0
   store i1 %carry_flag, i1* %pcarry_flag
   store i32 %mul, i32* %pmul
   ret void
 }

test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
 
 define i1 @test_i1(i1 %cnd, i1 %a, i1 %b) {
 ; MIPS32-LABEL: test_i1:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -16
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 16
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    ori $1, $zero, 1
 ; MIPS32-NEXT:    and $1, $4, $1
 ; MIPS32-NEXT:    sw $5, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 8($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $1, $BB0_2
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %entry
 ; MIPS32-NEXT:    j $BB0_3
 ; MIPS32-NEXT:    nop
cond.end:
   ret i1 %cond
 }
 
 define i8 @test_i8(i1 %cnd, i8 %a, i8 %b) {
 ; MIPS32-LABEL: test_i8:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -16
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 16
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    ori $1, $zero, 1
 ; MIPS32-NEXT:    and $1, $4, $1
 ; MIPS32-NEXT:    sw $5, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 8($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $1, $BB1_2
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %entry
 ; MIPS32-NEXT:    j $BB1_3
 ; MIPS32-NEXT:    nop
cond.end:
   ret i8 %cond
 }
 
 define i16 @test_i16(i1 %cnd, i16 %a, i16 %b) {
 ; MIPS32-LABEL: test_i16:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -16
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 16
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    ori $1, $zero, 1
 ; MIPS32-NEXT:    and $1, $4, $1
 ; MIPS32-NEXT:    sw $5, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 8($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $1, $BB2_2
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %entry
 ; MIPS32-NEXT:    j $BB2_3
 ; MIPS32-NEXT:    nop
cond.end:
   ret i16 %cond
 }
 
 define i32 @test_i32(i1 %cnd, i32 %a, i32 %b) {
 ; MIPS32-LABEL: test_i32:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -16
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 16
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    ori $1, $zero, 1
 ; MIPS32-NEXT:    and $1, $4, $1
 ; MIPS32-NEXT:    sw $5, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 8($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $1, $BB3_2
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %entry
 ; MIPS32-NEXT:    j $BB3_3
 ; MIPS32-NEXT:    nop

test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll

entry:
   %rem = srem i64 %b, %a
   ret i64 %rem
 }
 
 ; udiv
 define signext i8 @udiv_i8(i8 signext %a, i8 signext %b) {
 ; MIPS32-LABEL: udiv_i8:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 255
+; MIPS32-NEXT:    ori $1, $zero, 255
 ; MIPS32-NEXT:    and $1, $5, $1
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 255
+; MIPS32-NEXT:    ori $5, $zero, 255
 ; MIPS32-NEXT:    and $4, $4, $5
 ; MIPS32-NEXT:    divu $zero, $1, $4
 ; MIPS32-NEXT:    teq $4, $zero, 7
 ; MIPS32-NEXT:    mflo $1
 ; MIPS32-NEXT:    sll $1, $1, 24
 ; MIPS32-NEXT:    sra $2, $1, 24
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %div = udiv i8 %b, %a
   ret i8 %div
 }
 
 define signext i16 @udiv_i16(i16 signext %a, i16 signext %b) {
 ; MIPS32-LABEL: udiv_i16:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 65535
+; MIPS32-NEXT:    ori $1, $zero, 65535
 ; MIPS32-NEXT:    and $1, $5, $1
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 65535
+; MIPS32-NEXT:    ori $5, $zero, 65535
 ; MIPS32-NEXT:    and $4, $4, $5
 ; MIPS32-NEXT:    divu $zero, $1, $4
 ; MIPS32-NEXT:    teq $4, $zero, 7
 ; MIPS32-NEXT:    mflo $1
 ; MIPS32-NEXT:    sll $1, $1, 16
 ; MIPS32-NEXT:    sra $2, $1, 16
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
entry:
   %div = udiv i64 %b, %a
   ret i64 %div
 }
 
 ; urem
 define signext i8 @urem_i8(i8 signext %a, i8 signext %b) {
 ; MIPS32-LABEL: urem_i8:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 255
+; MIPS32-NEXT:    ori $1, $zero, 255
 ; MIPS32-NEXT:    and $1, $5, $1
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 255
+; MIPS32-NEXT:    ori $5, $zero, 255
 ; MIPS32-NEXT:    and $4, $4, $5
 ; MIPS32-NEXT:    divu $zero, $1, $4
 ; MIPS32-NEXT:    teq $4, $zero, 7
 ; MIPS32-NEXT:    mfhi $1
 ; MIPS32-NEXT:    sll $1, $1, 24
 ; MIPS32-NEXT:    sra $2, $1, 24
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %rem = urem i8 %b, %a
   ret i8 %rem
 }
 
 define signext i16 @urem_i16(i16 signext %a, i16 signext %b) {
 ; MIPS32-LABEL: urem_i16:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 65535
+; MIPS32-NEXT:    ori $1, $zero, 65535
 ; MIPS32-NEXT:    and $1, $5, $1
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 65535
+; MIPS32-NEXT:    ori $5, $zero, 65535
 ; MIPS32-NEXT:    and $4, $4, $5
 ; MIPS32-NEXT:    divu $zero, $1, $4
 ; MIPS32-NEXT:    teq $4, $zero, 7
 ; MIPS32-NEXT:    mfhi $1
 ; MIPS32-NEXT:    sll $1, $1, 16
 ; MIPS32-NEXT:    sra $2, $1, 16
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop

test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
 
 define i8 @select_i8(i1 %test, i8 %a, i8 %b) {
 ; MIPS32-LABEL: select_i8:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    ori $1, $zero, 1
 ; MIPS32-NEXT:    and $1, $4, $1
 ; MIPS32-NEXT:    movn $6, $5, $1
 ; MIPS32-NEXT:    move $2, $6
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cond = select i1 %test, i8 %a, i8 %b
   ret i8 %cond
 }
 
 define i16 @select_i16(i1 %test, i16 %a, i16 %b) {
 ; MIPS32-LABEL: select_i16:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    ori $1, $zero, 1
 ; MIPS32-NEXT:    and $1, $4, $1
 ; MIPS32-NEXT:    movn $6, $5, $1
 ; MIPS32-NEXT:    move $2, $6
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cond = select i1 %test, i16 %a, i16 %b
   ret i16 %cond
 }
 
 define i32 @select_i32(i1 %test, i32 %a, i32 %b) {
 ; MIPS32-LABEL: select_i32:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    ori $1, $zero, 1
 ; MIPS32-NEXT:    and $1, $4, $1
 ; MIPS32-NEXT:    movn $6, $5, $1
 ; MIPS32-NEXT:    move $2, $6
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cond = select i1 %test, i32 %a, i32 %b
   ret i32 %cond
 }
 
 define i32* @select_ptr(i1 %test, i32* %a, i32* %b) {
 ; MIPS32-LABEL: select_ptr:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    ori $1, $zero, 1
 ; MIPS32-NEXT:    and $1, $4, $1
 ; MIPS32-NEXT:    movn $6, $5, $1
 ; MIPS32-NEXT:    move $2, $6
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cond = select i1 %test, i32* %a, i32* %b
   ret i32* %cond
 }
 
 define i32 @select_with_negation(i32 %a, i32 %b, i32 %x, i32 %y) {
 ; MIPS32-LABEL: select_with_negation:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    slt $4, $4, $5
 ; MIPS32-NEXT:    not $4, $4
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $4, $4, $5
 ; MIPS32-NEXT:    movn $7, $6, $4
 ; MIPS32-NEXT:    move $2, $7
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp slt i32 %a, %b
   %lneg = xor i1 %cmp, true
   %cond = select i1 %lneg, i32 %x, i32 %y
   ret i32 %cond
 }

test/CodeGen/Mips/GlobalISel/llvm-ir/stack_args.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
 
 declare i32 @f(i32, i32, i32, i32, i32)
 
 define  i32 @g(i32  %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5){
 ; MIPS32-LABEL: g:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -32
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 32
 ; MIPS32-NEXT:    sw $ra, 28($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    .cfi_offset 31, -4
 ; MIPS32-NEXT:    addiu $1, $sp, 48
 ; MIPS32-NEXT:    lw $1, 0($1)
 ; MIPS32-NEXT:    move $2, $sp
-; MIPS32-NEXT:    lui $3, 0
-; MIPS32-NEXT:    ori $3, $3, 16
+; MIPS32-NEXT:    ori $3, $zero, 1
 ; MIPS32-NEXT:    addu $2, $2, $3
 ; MIPS32-NEXT:    sw $1, 0($2)
 ; MIPS32-NEXT:    jal f
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:    lw $ra, 28($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    addiu $sp, $sp, 32
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %call = call i32 @f(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5)
   ret i32 %call
 }

test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll

entry:
   %sub = sub i8 %b, %a
   ret i8 %sub
 }
 
 define zeroext i8 @sub_i8_zext(i8 zeroext %a, i8 zeroext %b) {
 ; MIPS32-LABEL: sub_i8_zext:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    subu $4, $5, $4
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 255
+; MIPS32-NEXT:    ori $5, $zero, 255
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %sub = sub i8 %b, %a
   ret i8 %sub
 }
 
entry:
   %sub = sub i16 %b, %a
   ret i16 %sub
 }
 
 define zeroext i16 @sub_i16_zext(i16 zeroext %a, i16 zeroext %b) {
 ; MIPS32-LABEL: sub_i16_zext:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    subu $4, $5, $4
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 65535
+; MIPS32-NEXT:    ori $5, $zero, 65535
 ; MIPS32-NEXT:    and $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %sub = sub i16 %b, %a
   ret i16 %sub
 }
 

 }
 
 define i64 @sub_i64(i64 %a, i64 %b) {
 ; MIPS32-LABEL: sub_i64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    subu $2, $6, $4
 ; MIPS32-NEXT:    sltu $4, $6, $4
 ; MIPS32-NEXT:    subu $5, $7, $5
-; MIPS32-NEXT:    lui $6, 0
-; MIPS32-NEXT:    ori $6, $6, 1
+; MIPS32-NEXT:    ori $6, $zero, 1
 ; MIPS32-NEXT:    and $4, $4, $6
 ; MIPS32-NEXT:    subu $3, $5, $4
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %sub = sub i64 %b, %a
   ret i64 %sub
 }
 
 define i128 @sub_i128(i128 %a, i128 %b) {
 ; MIPS32-LABEL: sub_i128:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $1, $sp, 16
 ; MIPS32-NEXT:    lw $1, 0($1)
 ; MIPS32-NEXT:    addiu $2, $sp, 20
 ; MIPS32-NEXT:    lw $2, 0($2)
 ; MIPS32-NEXT:    addiu $3, $sp, 24
 ; MIPS32-NEXT:    lw $3, 0($3)
 ; MIPS32-NEXT:    addiu $8, $sp, 28
 ; MIPS32-NEXT:    lw $8, 0($8)
 ; MIPS32-NEXT:    subu $9, $1, $4
 ; MIPS32-NEXT:    sltu $1, $1, $4
 ; MIPS32-NEXT:    subu $4, $2, $5
-; MIPS32-NEXT:    lui $10, 0
-; MIPS32-NEXT:    ori $10, $10, 1
+; MIPS32-NEXT:    ori $10, $zero, 1
 ; MIPS32-NEXT:    and $10, $1, $10
 ; MIPS32-NEXT:    subu $4, $4, $10
 ; MIPS32-NEXT:    xor $10, $2, $5
 ; MIPS32-NEXT:    sltiu $10, $10, 1
 ; MIPS32-NEXT:    sltu $2, $2, $5
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $5, $10, $5
 ; MIPS32-NEXT:    movn $2, $1, $5
 ; MIPS32-NEXT:    subu $1, $3, $6
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $5, $2, $5
 ; MIPS32-NEXT:    subu $1, $1, $5
 ; MIPS32-NEXT:    xor $5, $3, $6
 ; MIPS32-NEXT:    sltiu $5, $5, 1
 ; MIPS32-NEXT:    sltu $3, $3, $6
-; MIPS32-NEXT:    lui $6, 0
-; MIPS32-NEXT:    ori $6, $6, 1
+; MIPS32-NEXT:    ori $6, $zero, 1
 ; MIPS32-NEXT:    and $5, $5, $6
 ; MIPS32-NEXT:    movn $3, $2, $5
 ; MIPS32-NEXT:    subu $2, $8, $7
-; MIPS32-NEXT:    lui $5, 0
-; MIPS32-NEXT:    ori $5, $5, 1
+; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    and $3, $3, $5
 ; MIPS32-NEXT:    subu $5, $2, $3
 ; MIPS32-NEXT:    move $2, $9
 ; MIPS32-NEXT:    move $3, $4
 ; MIPS32-NEXT:    move $4, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %sub = sub i128 %b, %a
   ret i128 %sub
 }

test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll

entry:
   %0 = load i16, i16* %px
   ret i16 %0
 }
 
 define void @load_store_i1(i1* %px, i1* %py) {
 ; MIPS32-LABEL: load_store_i1:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    lbu $5, 0($5)
-; MIPS32-NEXT:    lui $1, 0
-; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    ori $1, $zero, 1
 ; MIPS32-NEXT:    and $1, $5, $1
 ; MIPS32-NEXT:    sb $1, 0($4)
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %0 = load i1, i1* %py
   store i1 %0, i1* %px
   ret void