[ARM] Add v8m.base pattern for add negative imm

[samparker]

Summary

The v8m.base ISA contains movw, which can operate on an unsigned 16-bit value. Add the pattern that converts an add with a negative value, that could fit into 16-bits when negated, into a sub with that positive value.

[fhahn]

test/CodeGen/ARM/sub.ll

9–10

Why is this change and the similar ones needed?

70

Check-label

76

Check-label

Also it might be worth expanding the check for v6m a bit

[samparker]

test/CodeGen/ARM/sub.ll

9–10

because we're testing arm and thumb code, where we maybe using the destructive form.

[samparker]

Updated tests.

[dmgreen]

lib/Target/ARM/ARMInstrThumb.td

1326

Should this be t2MOVi16?

[samparker]

lib/Target/ARM/ARMInstrThumb.td

1326

yup, cheers!

[samparker]

Before I put this in ISelDAGToDAG, is there a way to reference machine instructions from across different tablegen files..?

[dmgreen]

As far as understand, ARMInstrThumb.td is just #included in the other tablegen file. I guess the ordering might be important for them. Would it work better if it's defined in ARMInstrThumb2.td?

[samparker]

Well, I'll still have the problem that tSUBrr is defined in the other file =/

[samparker]

I've opted for putting the pattern in ARMInstrInfo once everything has been included. Also added encodings to the test to ensure we're now using the correct movw.

[dmgreen]

It looks like there are already a couple of patterns in ARMInstrThumb2.td for thumb1 instructions. I think with a comment it would be fine to put it in there. HasV8MBaseline tends to cross Thumb1/Thumb2 already.

[samparker]

Cheers Dave!

I've moved the pattern to where the accompanying T2 patterns are defined.

[dmgreen]

LGTM

lib/Target/ARM/ARMInstrThumb.td

                 IIC_iALUr,
                 "sub", "\t$Rd, $Rn, $Rm",
                 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
                 Sched<[WriteALU]>;
 
 def : tInstAlias <"sub${s}${p} $Rdn, $Rm",
                  (tSUBrr tGPR:$Rdn,s_cc_out:$s, tGPR:$Rdn, tGPR:$Rm, pred:$p)>;
 
+def : T1Pat<(add tGPR:$src, imm0_65535_neg:$imm),
+             (tSUBrr tGPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
+             Requires<[HasV8MBaseline]>;
+
 /// Similar to the above except these set the 's' bit so the
 /// instruction modifies the CPSR register.
 ///
 /// These opcodes will be converted to the real non-S opcodes by
 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
 let hasPostISelHook = 1, Defs = [CPSR] in {
   let Uses = [CPSR] in
   def tSBCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),

test/CodeGen/ARM/sub.ll

 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
 ; RUN: llc -mtriple=armeb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
+; RUN: llc -mtriple=thumbv6m %s -o - | FileCheck %s --check-prefix=CHECK-V6M
+; RUN: llc -mtriple=thumbv8m.base %s -o - | FileCheck %s --check-prefix=CHECK
+; RUN: llc -mtriple=thumbv8m.main %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
 
 ; 171 = 0x000000ab
 define i64 @f1(i64 %a) {
-; CHECK: f1
-; CHECK-LE: subs r0, r0, #171
+; CHECK-LABEL: f1
+; CHECK-LE: subs{{.*}} r0, #171
 ; CHECK-LE: sbc r1, r1, #0
 ; CHECK-BE: subs r1, r1, #171
 ; CHECK-BE: sbc r0, r0, #0
     %tmp = sub i64 %a, 171
     ret i64 %tmp
 }
 
 ; 66846720 = 0x03fc0000
 define i64 @f2(i64 %a) {
-; CHECK: f2
-; CHECK-LE: subs r0, r0, #66846720
+; CHECK-LABEL: f2
+; CHECK-LE: subs{{.*}} r0, r0, #66846720
 ; CHECK-LE: sbc r1, r1, #0
 ; CHECK-BE: subs r1, r1, #66846720
 ; CHECK-BE: sbc r0, r0, #0
     %tmp = sub i64 %a, 66846720
     ret i64 %tmp
 }
 
 ; 734439407618 = 0x000000ab00000002
 define i64 @f3(i64 %a) {
-; CHECK: f3
-; CHECK-LE: subs r0, r0, #2
+; CHECK-LABEL: f3
+; CHECK-LE: subs{{.*}} r0, #2
 ; CHECK-LE: sbc r1, r1, #171
 ; CHECK-BE: subs r1, r1, #2
 ; CHECK-BE: sbc r0, r0, #171
    %tmp = sub i64 %a, 734439407618
    ret i64 %tmp
 }
 
 define i32 @f4(i32 %x) {
 entry:
-; CHECK: f4
-; CHECK: rsbs
+; CHECK-LABEL: f4
+; CHECK-LE: rsbs
+; CHECK-BE: rsbs
   %sub = sub i32 1, %x
   %cmp = icmp ugt i32 %sub, 0
   %sel = select i1 %cmp, i32 1, i32 %sub
   ret i32 %sel
 }
 
-; rdar://11726136
 define i32 @f5(i32 %x) {
 entry:
-; CHECK: f5
+; CHECK-LABEL: f5
 ; CHECK: movw r1, #65535
 ; CHECK-NOT: movt
 ; CHECK-NOT: add
-; CHECK: sub r0, r0, r1
+; CHECK: sub{{.*}} r0, r0, r1
+
+; CHECK-V6M-LABEL: f5
+; CHECK-V6M: ldr [[NEG:r[0-1]+]], [[CONST:.[A-Z0-9_]+]]
+; CHECK-V6M: add{{.*}} r0, [[NEG]]
+; CHECK-V6M: [[CONST]]
+; CHECK-V6M: .long   4294901761
   %sub = add i32 %x, -65535
   ret i32 %sub
 }
+
+define i32 @f6(i32 %x) {
+entry:
+; CHECK-LABEL: f6
+; CHECK: movw r1, #65535
+; CHECK-NOT: movt
+; CHECK-NOT: sub
+; CHECK: add{{.*}} r0, r1
+
+; CHECK-V6M-LABEL: f6
+; CHECK-V6M: ldr [[NEG:r[0-1]+]], [[CONST:.[A-Z0-9_]+]]
+; CHECK-V6M: add{{.*}} r0, [[NEG]]
+; CHECK-V6M: [[CONST]]
+; CHECK-V6M: .long 65535
+  %sub = sub i32 %x, -65535
+  ret i32 %sub
+}