[ARM] Fix TTI IntImmCost

[samparker]

Summary

The cost of immediates returned from the backend was generally wrong, returning 1 for most immediates that could be directly encoded within an instruction. We now return 0 for these. The valuesreturned are now also more accurate, taking into consideration the exotic encoding patterns of Thumb2 immediates and calculating how many mov instructions would be needed to rematerialise a value.

[samparker]

Some tests to follow...

[samparker]

It looks like APInt doesn't function the way I expected, nor in the way that the other authors of this area would have expected. I've posted a query: http://lists.llvm.org/pipermail/llvm-dev/2019-January/129781.html

[xbolva00]

lib/Target/ARM/ARMTargetTransformInfo.cpp

111

Can we have a enum or so with these return constants and use them instead of “return 3”, “return 1”, ..

[samparker]

lib/Target/ARM/ARMTargetTransformInfo.cpp

111

Sure, I'll use TargetCostConstants.

[efriedma]

lib/Target/ARM/ARMTargetTransformInfo.cpp

99

Why are you throwing away the existing code using getT2SOImmVal/getSOImmVal and writing out the same logic inline?

108

Should this be guarded by useMovt?

158

Not sure I follow this logic; what does "Imm" actually mean in this case? Are we expecting that the result of the GEP will be folded into a load?

[efriedma]

Actually, we already have some very similar code in ARMDAGToDAGISel::ConstantMaterializationCost; can we share that code somehow?

[samparker]

I like that idea, I think moving the logic into ARMISelLowering would be good as we already use similar logic there too.

lib/Target/ARM/ARMTargetTransformInfo.cpp

99

Thanks, I'll revert.

108

Will do.

158

Yes, I'm assuming an immediate index which will be directly used by a load/store. I know this assumption doesn't hold all the time... But I'm not sure what to do with the limited information here.

lib/Target/ARM/ARMTargetTransformInfo.cpp

bool ARMTTIImpl::areInlineCompatible(const Function *Caller,
   bool MatchSubset = ((CallerBits & CalleeBits) & InlineFeatureWhitelist) ==
                      (CalleeBits & InlineFeatureWhitelist);
   return MatchExact && MatchSubset;
 }
 
 int ARMTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
   assert(Ty->isIntegerTy());
 
- unsigned Bits = Ty->getPrimitiveSizeInBits();
- if (Bits == 0 || Imm.getActiveBits() >= 64)
+  if (Imm.getActiveBits() >= 64)
     return 4;
 
-  int64_t SImmVal = Imm.getSExtValue();
-  uint64_t ZImmVal = Imm.getZExtValue();
-  if (!ST->isThumb()) {
-    if ((SImmVal >= 0 && SImmVal < 65536) ||
-        (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
-        (ARM_AM::getSOImmVal(~ZImmVal) != -1))
+  // Thumb-1
+  if (ST->isThumb() && ST->isThumb1Only()) {
+    // Simplify to allow 8-bit positives, though many instructions will
+    // only support narrower values that this.
+    if (Imm.isNonNegative() && Imm.getLimitedValue() < 256)
+      return 0;
+
+    if (Imm.isNegative() && Imm.sgt(-256)) {
+      // Can just use mov.
+      if (cast<IntegerType>(Ty)->getBitWidth() == 8)
         return 1;
-    return ST->hasV6T2Ops() ? 2 : 3;
+
+      // Use mov imm and mvn.
+      return 2;
     }
-  if (ST->isThumb2()) {
-    if ((SImmVal >= 0 && SImmVal < 65536) ||
-        (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
-        (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
-      return 1;
-    return ST->hasV6T2Ops() ? 2 : 3;
+
+    // TODO: Could predict whether this immediate could be rematerialised
+    // more easily than using a constantpool.
+
+    // Load from constantpool.
+    return 3;
   }
-  // Thumb1, any i8 imm cost 1.
-  if (Bits == 8 || (SImmVal >= 0 && SImmVal < 256))
+
+  const int LeadingZeros = Imm.countLeadingZeros();
+  const int TrailingZeros = Imm.countTrailingZeros();
+  const int BitWidth = Imm.getBitWidth();
+
+  // T32 Expand Imm
+  // Could also be splatted: |0x0|Imm|0x0|Imm|
+  //                         |Imm|0x0|Imm|0x0|
+  if (ST->isThumb2() && BitWidth == 32 && Imm.isSplat(16) &&
+      (LeadingZeros == 8 || TrailingZeros == 8))
+    return 0;
+
+  // Thumb-2 and Arm
+  // Approximate to 8-bits that can be shifted/rotated.
+  if (BitWidth - LeadingZeros - TrailingZeros <= 8)
+    return 0;
+
+  // Use mov with a 16-bit immediate.
+  // FIXME Though this is only available on v6t2 and armv7 onwards, we're
+  // allowing for V6 so we don't break usat selection.
+  if (ST->hasV6Ops()) {
+    if (Imm.isNonNegative() && Imm.ult(65535))
       return 1;
-  if ((~SImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
+    // Use mov and movt
     return 2;
+  }
   // Load from constantpool.
   return 3;
 }
 
 // Constants smaller than 256 fit in the immediate field of
 // Thumb1 instructions so we return a zero cost and 1 otherwise.
 int ARMTTIImpl::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
                                       const APInt &Imm, Type *Ty) {
   if (Imm.isNonNegative() && Imm.getLimitedValue() < 256)
     return 0;
int ARMTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
 
   if (Opcode == Instruction::Add)
     // Conversion to SUB is free, and means we can use -Imm instead.
     return std::min(getIntImmCost(Imm, Ty), getIntImmCost(-Imm, Ty));
 
   if (Opcode == Instruction::ICmp && Imm.isNegative() &&
       Ty->getIntegerBitWidth() == 32) {
     int64_t NegImm = -Imm.getSExtValue();
-    if (ST->isThumb2() && NegImm < 1<<12)
+    if ((!ST->isThumb() || ST->isThumb2()) && NegImm < 1<<12)
       // icmp X, #-C -> cmn X, #C
       return 0;
     if (ST->isThumb() && NegImm < 1<<8)
       // icmp X, #-C -> adds X, #C
       return 0;
   }
 
   // xor a, -1 can always be folded to MVN
   if (Opcode == Instruction::Xor && Imm.isAllOnesValue())
     return 0;
 
+  if (Opcode == Instruction::GetElementPtr) {
+    // FIXME Simplify by assuming 32-bit access, which uses an 8-bit offset
+    // with the bottom two bits set to zero. 12 bits for Arm.
+    if (!ST->isThumb()) {
+      if (Imm.sge(-2048) && Imm.sle(2047))
+        return 0;
+    } else if (ST->isThumb2() && Imm.sge(-512) && Imm.sle(511))
+      return 0;
+  }
+
   return getIntImmCost(Imm, Ty);
 }
 
 int ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
                                  const Instruction *I) {
   int ISD = TLI->InstructionOpcodeToISD(Opcode);
   assert(ISD && "Invalid opcode");
 

test/CodeGen/ARM/select_const.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=arm-eabi-unknown-unknown | FileCheck %s
+; RUN: llc < %s -mtriple=arm-eabi-unknown-unknown | FileCheck %s --check-prefix=CHECK-ARM
+; RUN: llc < %s -mtriple=thumbv6t2 | FileCheck %s --check-prefix=CHECK-THUMB2
 
 ; Select of constants: control flow / conditional moves can always be replaced by logic+math (but may not be worth it?).
 ; Test the zeroext/signext variants of each pattern to see if that makes a difference.
 
 ; select Cond, 0, 1 --> zext (!Cond)
 
 define i32 @select_0_or_1(i1 %cond) {
-; CHECK-LABEL: select_0_or_1:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov r1, #1
-; CHECK-NEXT:    bic r0, r1, r0
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_0_or_1:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mov r1, #1
+; CHECK-ARM-NEXT:    bic r0, r1, r0
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_0_or_1:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    movs r1, #1
+; CHECK-THUMB2-NEXT:    bic.w r0, r1, r0
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 0, i32 1
   ret i32 %sel
 }
 
 define i32 @select_0_or_1_zeroext(i1 zeroext %cond) {
-; CHECK-LABEL: select_0_or_1_zeroext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    eor r0, r0, #1
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_0_or_1_zeroext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    eor r0, r0, #1
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_0_or_1_zeroext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    eor r0, r0, #1
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 0, i32 1
   ret i32 %sel
 }
 
 define i32 @select_0_or_1_signext(i1 signext %cond) {
-; CHECK-LABEL: select_0_or_1_signext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov r1, #1
-; CHECK-NEXT:    bic r0, r1, r0
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_0_or_1_signext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mov r1, #1
+; CHECK-ARM-NEXT:    bic r0, r1, r0
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_0_or_1_signext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    movs r1, #1
+; CHECK-THUMB2-NEXT:    bic.w r0, r1, r0
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 0, i32 1
   ret i32 %sel
 }
 
 ; select Cond, 1, 0 --> zext (Cond)
 
 define i32 @select_1_or_0(i1 %cond) {
-; CHECK-LABEL: select_1_or_0:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_1_or_0:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    and r0, r0, #1
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_1_or_0:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    and r0, r0, #1
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 1, i32 0
   ret i32 %sel
 }
 
 define i32 @select_1_or_0_zeroext(i1 zeroext %cond) {
-; CHECK-LABEL: select_1_or_0_zeroext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_1_or_0_zeroext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_1_or_0_zeroext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 1, i32 0
   ret i32 %sel
 }
 
 define i32 @select_1_or_0_signext(i1 signext %cond) {
-; CHECK-LABEL: select_1_or_0_signext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_1_or_0_signext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    and r0, r0, #1
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_1_or_0_signext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    and r0, r0, #1
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 1, i32 0
   ret i32 %sel
 }
 
 ; select Cond, 0, -1 --> sext (!Cond)
 
 define i32 @select_0_or_neg1(i1 %cond) {
-; CHECK-LABEL: select_0_or_neg1:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov r1, #1
-; CHECK-NEXT:    bic r0, r1, r0
-; CHECK-NEXT:    rsb r0, r0, #0
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_0_or_neg1:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mov r1, #1
+; CHECK-ARM-NEXT:    bic r0, r1, r0
+; CHECK-ARM-NEXT:    rsb r0, r0, #0
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_0_or_neg1:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    movs r1, #1
+; CHECK-THUMB2-NEXT:    bic.w r0, r1, r0
+; CHECK-THUMB2-NEXT:    rsbs r0, r0, #0
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 0, i32 -1
   ret i32 %sel
 }
 
 define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {
-; CHECK-LABEL: select_0_or_neg1_zeroext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    eor r0, r0, #1
-; CHECK-NEXT:    rsb r0, r0, #0
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_0_or_neg1_zeroext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    eor r0, r0, #1
+; CHECK-ARM-NEXT:    rsb r0, r0, #0
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_0_or_neg1_zeroext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    eor r0, r0, #1
+; CHECK-THUMB2-NEXT:    rsbs r0, r0, #0
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 0, i32 -1
   ret i32 %sel
 }
 
 define i32 @select_0_or_neg1_signext(i1 signext %cond) {
-; CHECK-LABEL: select_0_or_neg1_signext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mvn r0, r0
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_0_or_neg1_signext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mvn r0, r0
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_0_or_neg1_signext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    mvns r0, r0
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 0, i32 -1
   ret i32 %sel
 }
 
 define i32 @select_0_or_neg1_alt(i1 %cond) {
-; CHECK-LABEL: select_0_or_neg1_alt:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    sub r0, r0, #1
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_0_or_neg1_alt:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    and r0, r0, #1
+; CHECK-ARM-NEXT:    sub r0, r0, #1
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_0_or_neg1_alt:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    and r0, r0, #1
+; CHECK-THUMB2-NEXT:    subs r0, #1
+; CHECK-THUMB2-NEXT:    bx lr
   %z = zext i1 %cond to i32
   %add = add i32 %z, -1
   ret i32 %add
 }
 
 define i32 @select_0_or_neg1_alt_zeroext(i1 zeroext %cond) {
-; CHECK-LABEL: select_0_or_neg1_alt_zeroext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    sub r0, r0, #1
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_0_or_neg1_alt_zeroext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    sub r0, r0, #1
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_0_or_neg1_alt_zeroext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    subs r0, #1
+; CHECK-THUMB2-NEXT:    bx lr
   %z = zext i1 %cond to i32
   %add = add i32 %z, -1
   ret i32 %add
 }
 
 define i32 @select_0_or_neg1_alt_signext(i1 signext %cond) {
-; CHECK-LABEL: select_0_or_neg1_alt_signext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mvn r0, r0
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_0_or_neg1_alt_signext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mvn r0, r0
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_0_or_neg1_alt_signext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    mvns r0, r0
+; CHECK-THUMB2-NEXT:    bx lr
   %z = zext i1 %cond to i32
   %add = add i32 %z, -1
   ret i32 %add
 }
 
 ; select Cond, -1, 0 --> sext (Cond)
 
 define i32 @select_neg1_or_0(i1 %cond) {
-; CHECK-LABEL: select_neg1_or_0:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsb r0, r0, #0
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_neg1_or_0:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    and r0, r0, #1
+; CHECK-ARM-NEXT:    rsb r0, r0, #0
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_neg1_or_0:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    and r0, r0, #1
+; CHECK-THUMB2-NEXT:    rsbs r0, r0, #0
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 -1, i32 0
   ret i32 %sel
 }
 
 define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {
-; CHECK-LABEL: select_neg1_or_0_zeroext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    rsb r0, r0, #0
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_neg1_or_0_zeroext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    rsb r0, r0, #0
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_neg1_or_0_zeroext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    rsbs r0, r0, #0
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 -1, i32 0
   ret i32 %sel
 }
 
 define i32 @select_neg1_or_0_signext(i1 signext %cond) {
-; CHECK-LABEL: select_neg1_or_0_signext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_neg1_or_0_signext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_neg1_or_0_signext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 -1, i32 0
   ret i32 %sel
 }
 
 ; select Cond, C+1, C --> add (zext Cond), C
 
 define i32 @select_Cplus1_C(i1 %cond) {
-; CHECK-LABEL: select_Cplus1_C:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov r1, #41
-; CHECK-NEXT:    tst r0, #1
-; CHECK-NEXT:    movne r1, #42
-; CHECK-NEXT:    mov r0, r1
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_Cplus1_C:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mov r1, #41
+; CHECK-ARM-NEXT:    tst r0, #1
+; CHECK-ARM-NEXT:    movne r1, #42
+; CHECK-ARM-NEXT:    mov r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_Cplus1_C:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    lsls r0, r0, #31
+; CHECK-THUMB2-NEXT:    mov.w r0, #41
+; CHECK-THUMB2-NEXT:    it ne
+; CHECK-THUMB2-NEXT:    movne r0, #42
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 42, i32 41
   ret i32 %sel
 }
 
 define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) {
-; CHECK-LABEL: select_Cplus1_C_zeroext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov r1, #41
-; CHECK-NEXT:    cmp r0, #0
-; CHECK-NEXT:    movne r1, #42
-; CHECK-NEXT:    mov r0, r1
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_Cplus1_C_zeroext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mov r1, #41
+; CHECK-ARM-NEXT:    cmp r0, #0
+; CHECK-ARM-NEXT:    movne r1, #42
+; CHECK-ARM-NEXT:    mov r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_Cplus1_C_zeroext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    movs r1, #41
+; CHECK-THUMB2-NEXT:    cmp r0, #0
+; CHECK-THUMB2-NEXT:    it ne
+; CHECK-THUMB2-NEXT:    movne r1, #42
+; CHECK-THUMB2-NEXT:    mov r0, r1
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 42, i32 41
   ret i32 %sel
 }
 
 define i32 @select_Cplus1_C_signext(i1 signext %cond) {
-; CHECK-LABEL: select_Cplus1_C_signext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov r1, #41
-; CHECK-NEXT:    tst r0, #1
-; CHECK-NEXT:    movne r1, #42
-; CHECK-NEXT:    mov r0, r1
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_Cplus1_C_signext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mov r1, #41
+; CHECK-ARM-NEXT:    tst r0, #1
+; CHECK-ARM-NEXT:    movne r1, #42
+; CHECK-ARM-NEXT:    mov r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_Cplus1_C_signext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    lsls r0, r0, #31
+; CHECK-THUMB2-NEXT:    mov.w r0, #41
+; CHECK-THUMB2-NEXT:    it ne
+; CHECK-THUMB2-NEXT:    movne r0, #42
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 42, i32 41
   ret i32 %sel
 }
 
 ; select Cond, C, C+1 --> add (sext Cond), C
 
 define i32 @select_C_Cplus1(i1 %cond) {
-; CHECK-LABEL: select_C_Cplus1:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov r1, #42
-; CHECK-NEXT:    tst r0, #1
-; CHECK-NEXT:    movne r1, #41
-; CHECK-NEXT:    mov r0, r1
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_C_Cplus1:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mov r1, #42
+; CHECK-ARM-NEXT:    tst r0, #1
+; CHECK-ARM-NEXT:    movne r1, #41
+; CHECK-ARM-NEXT:    mov r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_C_Cplus1:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    lsls r0, r0, #31
+; CHECK-THUMB2-NEXT:    mov.w r0, #42
+; CHECK-THUMB2-NEXT:    it ne
+; CHECK-THUMB2-NEXT:    movne r0, #41
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {
-; CHECK-LABEL: select_C_Cplus1_zeroext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov r1, #42
-; CHECK-NEXT:    cmp r0, #0
-; CHECK-NEXT:    movne r1, #41
-; CHECK-NEXT:    mov r0, r1
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_C_Cplus1_zeroext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mov r1, #42
+; CHECK-ARM-NEXT:    cmp r0, #0
+; CHECK-ARM-NEXT:    movne r1, #41
+; CHECK-ARM-NEXT:    mov r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_C_Cplus1_zeroext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    movs r1, #42
+; CHECK-THUMB2-NEXT:    cmp r0, #0
+; CHECK-THUMB2-NEXT:    it ne
+; CHECK-THUMB2-NEXT:    movne r1, #41
+; CHECK-THUMB2-NEXT:    mov r0, r1
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C_Cplus1_signext(i1 signext %cond) {
-; CHECK-LABEL: select_C_Cplus1_signext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov r1, #42
-; CHECK-NEXT:    tst r0, #1
-; CHECK-NEXT:    movne r1, #41
-; CHECK-NEXT:    mov r0, r1
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_C_Cplus1_signext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mov r1, #42
+; CHECK-ARM-NEXT:    tst r0, #1
+; CHECK-ARM-NEXT:    movne r1, #41
+; CHECK-ARM-NEXT:    mov r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_C_Cplus1_signext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    lsls r0, r0, #31
+; CHECK-THUMB2-NEXT:    mov.w r0, #42
+; CHECK-THUMB2-NEXT:    it ne
+; CHECK-THUMB2-NEXT:    movne r0, #41
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
 }
 
 ; In general, select of 2 constants could be:
 ; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> add (and (sext Cond), C1-C2), C2
 
 define i32 @select_C1_C2(i1 %cond) {
-; CHECK-LABEL: select_C1_C2:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov r1, #165
-; CHECK-NEXT:    tst r0, #1
-; CHECK-NEXT:    orr r1, r1, #256
-; CHECK-NEXT:    moveq r1, #42
-; CHECK-NEXT:    mov r0, r1
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_C1_C2:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mov r1, #165
+; CHECK-ARM-NEXT:    tst r0, #1
+; CHECK-ARM-NEXT:    orr r1, r1, #256
+; CHECK-ARM-NEXT:    moveq r1, #42
+; CHECK-ARM-NEXT:    mov r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_C1_C2:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    lsls r0, r0, #31
+; CHECK-THUMB2-NEXT:    mov.w r0, #42
+; CHECK-THUMB2-NEXT:    it ne
+; CHECK-THUMB2-NEXT:    movwne r0, #421
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 421, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {
-; CHECK-LABEL: select_C1_C2_zeroext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov r1, #165
-; CHECK-NEXT:    cmp r0, #0
-; CHECK-NEXT:    orr r1, r1, #256
-; CHECK-NEXT:    moveq r1, #42
-; CHECK-NEXT:    mov r0, r1
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_C1_C2_zeroext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mov r1, #165
+; CHECK-ARM-NEXT:    cmp r0, #0
+; CHECK-ARM-NEXT:    orr r1, r1, #256
+; CHECK-ARM-NEXT:    moveq r1, #42
+; CHECK-ARM-NEXT:    mov r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_C1_C2_zeroext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    movs r1, #42
+; CHECK-THUMB2-NEXT:    cmp r0, #0
+; CHECK-THUMB2-NEXT:    it ne
+; CHECK-THUMB2-NEXT:    movwne r1, #421
+; CHECK-THUMB2-NEXT:    mov r0, r1
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 421, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C1_C2_signext(i1 signext %cond) {
-; CHECK-LABEL: select_C1_C2_signext:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov r1, #165
-; CHECK-NEXT:    tst r0, #1
-; CHECK-NEXT:    orr r1, r1, #256
-; CHECK-NEXT:    moveq r1, #42
-; CHECK-NEXT:    mov r0, r1
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: select_C1_C2_signext:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mov r1, #165
+; CHECK-ARM-NEXT:    tst r0, #1
+; CHECK-ARM-NEXT:    orr r1, r1, #256
+; CHECK-ARM-NEXT:    moveq r1, #42
+; CHECK-ARM-NEXT:    mov r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: select_C1_C2_signext:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    lsls r0, r0, #31
+; CHECK-THUMB2-NEXT:    mov.w r0, #42
+; CHECK-THUMB2-NEXT:    it ne
+; CHECK-THUMB2-NEXT:    movwne r0, #421
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i32 421, i32 42
   ret i32 %sel
 }
 
 ; 4295032833 = 0x100010001.
 ; This becomes an opaque constant via ConstantHoisting, so we don't fold it into the select.
 
 define i64 @opaque_constant1(i1 %cond, i64 %x) {
-; CHECK-LABEL: opaque_constant1:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    .save {r4, lr}
-; CHECK-NEXT:    push {r4, lr}
-; CHECK-NEXT:    mov lr, #1
-; CHECK-NEXT:    ands r12, r0, #1
-; CHECK-NEXT:    mov r0, #23
-; CHECK-NEXT:    orr lr, lr, #65536
-; CHECK-NEXT:    mvnne r0, #3
-; CHECK-NEXT:    and r4, r0, lr
-; CHECK-NEXT:    movne r12, #1
-; CHECK-NEXT:    subs r0, r4, #1
-; CHECK-NEXT:    eor r2, r2, lr
-; CHECK-NEXT:    eor r3, r3, #1
-; CHECK-NEXT:    sbc r1, r12, #0
-; CHECK-NEXT:    orrs r2, r2, r3
-; CHECK-NEXT:    movne r0, r4
-; CHECK-NEXT:    movne r1, r12
-; CHECK-NEXT:    pop {r4, lr}
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: opaque_constant1:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    .save {r4, lr}
+; CHECK-ARM-NEXT:    push {r4, lr}
+; CHECK-ARM-NEXT:    mov lr, #1
+; CHECK-ARM-NEXT:    ands r12, r0, #1
+; CHECK-ARM-NEXT:    mov r0, #23
+; CHECK-ARM-NEXT:    orr lr, lr, #65536
+; CHECK-ARM-NEXT:    mvnne r0, #3
+; CHECK-ARM-NEXT:    and r4, r0, lr
+; CHECK-ARM-NEXT:    movne r12, #1
+; CHECK-ARM-NEXT:    subs r0, r4, #1
+; CHECK-ARM-NEXT:    eor r2, r2, lr
+; CHECK-ARM-NEXT:    eor r3, r3, #1
+; CHECK-ARM-NEXT:    sbc r1, r12, #0
+; CHECK-ARM-NEXT:    orrs r2, r2, r3
+; CHECK-ARM-NEXT:    movne r0, r4
+; CHECK-ARM-NEXT:    movne r1, r12
+; CHECK-ARM-NEXT:    pop {r4, lr}
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: opaque_constant1:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    push {r7, lr}
+; CHECK-THUMB2-NEXT:    ands r12, r0, #1
+; CHECK-THUMB2-NEXT:    mov.w r0, #23
+; CHECK-THUMB2-NEXT:    it ne
+; CHECK-THUMB2-NEXT:    mvnne r0, #3
+; CHECK-THUMB2-NEXT:    and lr, r0, #65537
+; CHECK-THUMB2-NEXT:    it ne
+; CHECK-THUMB2-NEXT:    movne.w r12, #1
+; CHECK-THUMB2-NEXT:    subs.w r0, lr, #1
+; CHECK-THUMB2-NEXT:    sbc r1, r12, #0
+; CHECK-THUMB2-NEXT:    eor r3, r3, #1
+; CHECK-THUMB2-NEXT:    eor r2, r2, #65537
+; CHECK-THUMB2-NEXT:    orrs r2, r3
+; CHECK-THUMB2-NEXT:    itt ne
+; CHECK-THUMB2-NEXT:    movne r0, lr
+; CHECK-THUMB2-NEXT:    movne r1, r12
+; CHECK-THUMB2-NEXT:    pop {r7, pc}
   %sel = select i1 %cond, i64 -4, i64 23
   %bo = and i64 %sel, 4295032833  ; 0x100010001
   %cmp = icmp eq i64 %x, 4295032833
   %sext = sext i1 %cmp to i64
   %add = add i64 %bo, %sext
   ret i64 %add
 }
 
 ; 65537 == 0x10001.
 ; This becomes an opaque constant via ConstantHoisting, so we don't fold it into the select.
 
 define i64 @opaque_constant2(i1 %cond, i64 %x) {
-; CHECK-LABEL: opaque_constant2:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    mov r1, #1
-; CHECK-NEXT:    tst r0, #1
-; CHECK-NEXT:    orr r1, r1, #65536
-; CHECK-NEXT:    moveq r1, #23
-; CHECK-NEXT:    bic r0, r1, #22
-; CHECK-NEXT:    mov r1, #0
-; CHECK-NEXT:    mov pc, lr
+; CHECK-ARM-LABEL: opaque_constant2:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mov r1, #1
+; CHECK-ARM-NEXT:    tst r0, #1
+; CHECK-ARM-NEXT:    orr r1, r1, #65536
+; CHECK-ARM-NEXT:    moveq r1, #23
+; CHECK-ARM-NEXT:    bic r0, r1, #22
+; CHECK-ARM-NEXT:    mov r1, #0
+; CHECK-ARM-NEXT:    mov pc, lr
+;
+; CHECK-THUMB2-LABEL: opaque_constant2:
+; CHECK-THUMB2:       @ %bb.0:
+; CHECK-THUMB2-NEXT:    lsls r0, r0, #31
+; CHECK-THUMB2-NEXT:    mov.w r1, #0
+; CHECK-THUMB2-NEXT:    mov.w r0, #23
+; CHECK-THUMB2-NEXT:    it ne
+; CHECK-THUMB2-NEXT:    movne.w r0, #65537
+; CHECK-THUMB2-NEXT:    bic r0, r0, #22
+; CHECK-THUMB2-NEXT:    bx lr
   %sel = select i1 %cond, i64 65537, i64 23
   %bo = and i64 %sel, 65537
   ret i64 %bo
 }