GlobalISel: Legalization for inttoptr/ptrtoint

[aemerson]

LGTM.

[aemerson]

I've just remembered we need to notify the Observer when we're modifying instructions in place.

[arsenm]

Call observer

[arsenm]

r352973

include/llvm/CodeGen/GlobalISel/LegalizerInfo.h

 /// size.
 LegalityPredicate narrowerThan(unsigned TypeIdx, unsigned Size);
 /// True iff the specified type index is a scalar that's wider than the given
 /// size.
 LegalityPredicate widerThan(unsigned TypeIdx, unsigned Size);
 /// True iff the specified type index is a scalar whose size is not a power of
 /// 2.
 LegalityPredicate sizeNotPow2(unsigned TypeIdx);
+/// True iff the specified type indices are both the same bit size.
+LegalityPredicate sameSize(unsigned TypeIdx0, unsigned TypeIdx1);
 /// True iff the specified MMO index has a size that is not a power of 2
 LegalityPredicate memSizeInBytesNotPow2(unsigned MMOIdx);
 /// True iff the specified type index is a vector whose element count is not a
 /// power of 2.
 LegalityPredicate numElementsNotPow2(unsigned TypeIdx);
 /// True iff the specified MMO index has at an atomic ordering of at Ordering or
 /// stronger.
 LegalityPredicate atomicOrderingAtLeastOrStrongerThan(unsigned MMOIdx,

lib/CodeGen/GlobalISel/LegalityPredicates.cpp

 
 LegalityPredicate LegalityPredicates::sizeNotPow2(unsigned TypeIdx) {
   return [=](const LegalityQuery &Query) {
     const LLT &QueryTy = Query.Types[TypeIdx];
     return QueryTy.isScalar() && !isPowerOf2_32(QueryTy.getSizeInBits());
   };
 }
 
+LegalityPredicate LegalityPredicates::sameSize(unsigned TypeIdx0,
+                                               unsigned TypeIdx1) {
+  return [=](const LegalityQuery &Query) {
+    return Query.Types[TypeIdx0].getSizeInBits() ==
+           Query.Types[TypeIdx1].getSizeInBits();
+  };
+}
+
 LegalityPredicate LegalityPredicates::memSizeInBytesNotPow2(unsigned MMOIdx) {
   return [=](const LegalityQuery &Query) {
     return !isPowerOf2_32(Query.MMODescrs[MMOIdx].SizeInBits / 8);
   };
 }
 
 LegalityPredicate LegalityPredicates::numElementsNotPow2(unsigned TypeIdx) {
   return [=](const LegalityQuery &Query) {

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
   case TargetOpcode::G_CTTZ:
   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
   case TargetOpcode::G_CTPOP:
     if (TypeIdx != 0)
       return UnableToLegalize; // TODO
     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
     return Legalized;
+  case TargetOpcode::G_INTTOPTR:
+    if (TypeIdx != 1)
+      return UnableToLegalize;
+    narrowScalarSrc(MI, NarrowTy, 1);
+    return Legalized;
+  case TargetOpcode::G_PTRTOINT:
+    if (TypeIdx != 0)
+      return UnableToLegalize;
+    narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
+    return Legalized;
   }
 }
 
 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
                                      unsigned OpIdx, unsigned ExtOpcode) {
   MachineOperand &MO = MI.getOperand(OpIdx);
   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
   MO.setReg(ExtB->getOperand(0).getReg());
case TargetOpcode::G_FCEIL:
     Observer.changingInstr(MI);
 
     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
 
     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
     Observer.changedInstr(MI);
     return Legalized;
+  case TargetOpcode::G_INTTOPTR:
+    if (TypeIdx != 1)
+      return UnableToLegalize;
+    widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
+    return Legalized;
+  case TargetOpcode::G_PTRTOINT:
+    if (TypeIdx != 0)
+      return UnableToLegalize;
+    widenScalarDst(MI, WideTy, 0);
+    return Legalized;
   }
 }
 
 LegalizerHelper::LegalizeResult
 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
   using namespace TargetOpcode;
   MIRBuilder.setInstr(MI);
 
LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
   unsigned SrcReg = MI.getOperand(1).getReg();
   LLT DstTy = MRI.getType(DstReg);
   LLT SrcTy = MRI.getType(SrcReg);
 
   LLT NarrowTy0 = NarrowTy;
   LLT NarrowTy1;
   unsigned NumParts;
 
-  if (NarrowTy.isScalar()) {
-    NumParts = DstTy.getNumElements();
-    NarrowTy1 = SrcTy.getElementType();
-  } else {
+  if (NarrowTy.isVector()) {
     // Uneven breakdown not handled.
     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
       return UnableToLegalize;
 
     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
+  } else {
+    NumParts = DstTy.getNumElements();
+    NarrowTy1 = SrcTy.getElementType();
   }
 
   SmallVector<unsigned, 4> SrcRegs, DstRegs;
   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
 
   for (unsigned I = 0; I < NumParts; ++I) {
     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
   case TargetOpcode::G_SEXT:
   case TargetOpcode::G_ANYEXT:
   case TargetOpcode::G_FPEXT:
   case TargetOpcode::G_FPTRUNC:
   case TargetOpcode::G_SITOFP:
   case TargetOpcode::G_UITOFP:
   case TargetOpcode::G_FPTOSI:
   case TargetOpcode::G_FPTOUI:
+  case TargetOpcode::G_INTTOPTR:
+  case TargetOpcode::G_PTRTOINT:
     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
   }
 }
 
 LegalizerHelper::LegalizeResult
 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
   unsigned Opc = MI.getOpcode();
   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

getActionDefinitionsBuilder(G_FSUB)
       .lowerFor({S64, S16, V2S16})
       .scalarize(0)
       .clampScalar(0, S32, S64);
 
   getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
     .legalFor({{S64, S32}, {S32, S16}, {S64, S16},
                {S32, S1}, {S64, S1}, {S16, S1},
                // FIXME: Hack
-               {S128, S32}})
+               {S128, S32}, {S128, S64}})
     .scalarize(0);
 
   getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
     .legalFor({{S32, S32}, {S64, S32}})
     .scalarize(0);
 
   getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
     .legalFor({{S32, S32}, {S32, S64}})
getActionDefinitionsBuilder({G_CTLZ, G_CTLZ_ZERO_UNDEF,
     .legalFor({{S32, S32}, {S32, S64}})
     .clampScalar(0, S32, S32)
     .clampScalar(1, S32, S64);
   // TODO: Scalarize
 
 
   setAction({G_BSWAP, S32}, Legal);
 
+  auto smallerThan = [](unsigned TypeIdx0, unsigned TypeIdx1) {
+    return [=](const LegalityQuery &Query) {
+      return Query.Types[TypeIdx0].getSizeInBits() <
+             Query.Types[TypeIdx1].getSizeInBits();
+    };
+  };
+
+  auto greaterThan = [](unsigned TypeIdx0, unsigned TypeIdx1) {
+    return [=](const LegalityQuery &Query) {
+      return Query.Types[TypeIdx0].getSizeInBits() >
+             Query.Types[TypeIdx1].getSizeInBits();
+    };
+  };
+
   getActionDefinitionsBuilder(G_INTTOPTR)
-    .legalIf([](const LegalityQuery &Query) {
-      return true;
+    // List the common cases
+    .legalForCartesianProduct({GlobalPtr, ConstantPtr, FlatPtr}, {S64})
+    .legalForCartesianProduct({LocalPtr, PrivatePtr}, {S32})
+    .scalarize(0)
+    // Accept any address space as long as the size matches
+    .legalIf(sameSize(0, 1))
+    .widenScalarIf(smallerThan(1, 0),
+      [](const LegalityQuery &Query) {
+        return std::make_pair(1, LLT::scalar(Query.Types[0].getSizeInBits()));
+      })
+    .narrowScalarIf(greaterThan(1, 0),
+      [](const LegalityQuery &Query) {
+        return std::make_pair(1, LLT::scalar(Query.Types[0].getSizeInBits()));
       });
 
   getActionDefinitionsBuilder(G_PTRTOINT)
-    .legalIf([](const LegalityQuery &Query) {
-      return true;
+    // List the common cases
+    .legalForCartesianProduct({GlobalPtr, ConstantPtr, FlatPtr}, {S64})
+    .legalForCartesianProduct({LocalPtr, PrivatePtr}, {S32})
+    .scalarize(0)
+    // Accept any address space as long as the size matches
+    .legalIf(sameSize(0, 1))
+    .widenScalarIf(smallerThan(0, 1),
+      [](const LegalityQuery &Query) {
+        return std::make_pair(0, LLT::scalar(Query.Types[1].getSizeInBits()));
+      })
+    .narrowScalarIf(
+      greaterThan(0, 1),
+      [](const LegalityQuery &Query) {
+        return std::make_pair(0, LLT::scalar(Query.Types[1].getSizeInBits()));
       });
 
   getActionDefinitionsBuilder({G_LOAD, G_STORE})
     .legalIf([=, &ST](const LegalityQuery &Query) {
         const LLT &Ty0 = Query.Types[0];
 
         // TODO: Decompose private loads into 4-byte components.
         // TODO: Illegal flat loads on SI
         switch (Ty0.getSizeInBits()) {
AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
   getActionDefinitionsBuilder({G_EXTRACT, G_INSERT})
     .legalIf([=](const LegalityQuery &Query) {
         const LLT &Ty0 = Query.Types[0];
         const LLT &Ty1 = Query.Types[1];
         return (Ty0.getSizeInBits() % 32 == 0) &&
                (Ty1.getSizeInBits() % 32 == 0);
       });
 
+  // TODO: vectors of pointers
   getActionDefinitionsBuilder(G_BUILD_VECTOR)
       .legalForCartesianProduct(AllS32Vectors, {S32})
       .legalForCartesianProduct(AllS64Vectors, {S64})
       .clampNumElements(0, V16S32, V16S32)
       .clampNumElements(0, V2S64, V8S64)
       .minScalarSameAs(1, 0)
       // FIXME: Sort of a hack to make progress on other legalizations.
       .legalIf([=](const LegalityQuery &Query) {

test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir

-# RUN: llc -march=amdgcn -run-pass=legalizer %s -o - | FileCheck %s
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck %s
 
 ---
-name: test_inttoptr
+name: test_inttoptr_s64_to_p0
 body: |
   bb.0:
-    liveins: $sgpr0_sgpr1, $sgpr2, $vgpr0_vgpr1, $vgpr2
+    liveins: $vgpr0_vgpr1
 
-    ; CHECK-LABEL: name: test_inttoptr
-    ; CHECK: [[S64:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
-    ; CHECK: [[S32:%[0-9]+]]:_(s32) = COPY $sgpr2
-    ; CHECK: [[V64:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
-    ; CHECK: [[V32:%[0-9]+]]:_(s32) = COPY $vgpr2
-    ; CHECK: (p0) = G_INTTOPTR [[V64]]
-    ; CHECK: (p1) = G_INTTOPTR [[V64]]
-    ; CHECK: (p3) = G_INTTOPTR [[V32]]
-    ; CHECK: (p4) = G_INTTOPTR [[S64]]
-    ; CHECK: (p5) = G_INTTOPTR [[S32]]
-    %0:_(s64) = COPY $sgpr0_sgpr1
-    %1:_(s32) = COPY $sgpr2
-    %2:_(s64) = COPY $vgpr0_vgpr1
-    %3:_(s32) = COPY $vgpr2
-    %4:_(p0) = G_INTTOPTR %2
-    %5:_(p1) = G_INTTOPTR %2
-    %6:_(p3) = G_INTTOPTR %3
-    %7:_(p4) = G_INTTOPTR %0
-    %8:_(p5) = G_INTTOPTR %1
-    S_ENDPGM implicit %4, implicit %5, implicit %6, implicit %7, implicit %8
+    ; CHECK-LABEL: name: test_inttoptr_s64_to_p0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p0)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(p0) = G_INTTOPTR %0
+    $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: test_inttoptr_s64_to_p1
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+
+    ; CHECK-LABEL: name: test_inttoptr_s64_to_p1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[COPY]](s64)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(p1) = G_INTTOPTR %0
+    $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: test_inttoptr_s64_to_p4
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+
+    ; CHECK-LABEL: name: test_inttoptr_s64_to_p4
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p4) = G_INTTOPTR [[COPY]](s64)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p4)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(p4) = G_INTTOPTR %0
+    $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: test_inttoptr_s32_to_p3
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_inttoptr_s32_to_p3
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[COPY]](s32)
+    ; CHECK: $vgpr0 = COPY [[INTTOPTR]](p3)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(p3) = G_INTTOPTR %0
+    $vgpr0 = COPY %1
+...
+
+---
+name: test_inttoptr_s32_to_p5
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_inttoptr_s32_to_p5
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[COPY]](s32)
+    ; CHECK: $vgpr0 = COPY [[INTTOPTR]](p5)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(p5) = G_INTTOPTR %0
+    $vgpr0 = COPY %1
+...
+
+---
+name: test_inttoptr_s64_to_p999
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+
+    ; CHECK-LABEL: name: test_inttoptr_s64_to_p999
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p999) = G_INTTOPTR [[COPY]](s64)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p999)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(p999) = G_INTTOPTR %0
+    $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: test_inttoptr_s32_to_p0
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_inttoptr_s32_to_p0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ZEXT]](s64)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p0)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(p0) = G_INTTOPTR %0
+    $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: test_inttoptr_s128_to_p0
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+    ; CHECK-LABEL: name: test_inttoptr_s128_to_p0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[TRUNC]](s64)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p0)
+    %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+    %1:_(p0) = G_INTTOPTR %0
+    $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: test_inttoptr_v2s64_to_v2p0
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+    ; CHECK-LABEL: name: test_inttoptr_v2s64_to_v2p0
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[UV]](s64)
+    ; CHECK: [[INTTOPTR1:%[0-9]+]]:_(p0) = G_INTTOPTR [[UV1]](s64)
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[INTTOPTR]](p0), [[INTTOPTR1]](p0)
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p0>)
+    %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+    %1:_(<2 x p0>) = G_INTTOPTR %0
+    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
+...
+
+---
+name: test_inttoptr_v2s32_to_v2p0
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+
+    ; CHECK-LABEL: name: test_inttoptr_v2s32_to_v2p0
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UV]](s32)
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ZEXT]](s64)
+    ; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[UV1]](s32)
+    ; CHECK: [[INTTOPTR1:%[0-9]+]]:_(p0) = G_INTTOPTR [[ZEXT1]](s64)
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[INTTOPTR]](p0), [[INTTOPTR1]](p0)
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p0>)
+    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    %1:_(<2 x p0>) = G_INTTOPTR %0
+    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
 ...