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Differential D56914

[MIPS GlobalISel] Combine extending loads
ClosedPublic

Authored by Petar.Avramovic on Jan 18 2019, 8:07 AM.

Details

Reviewers
atanasyan
petarj
dsanders
Commits
rGb5a939d24653: [MIPS GlobalISel] Combine extending loads
rL352037: [MIPS GlobalISel] Combine extending loads
Summary

Use CombinerHelper to combine extending load instructions.
G_LOAD combined with G_ZEXT, G_SEXT or G_ANYEXT gives G_ZEXTLOAD,
G_SEXTLOAD or G_LOAD with same type as def of extending instruction respectively.
Similarly G_ZEXTLOAD combined with G_ZEXT gives G_ZEXTLOAD and
G_SEXTLOAD combined with G_SEXT gives G_SEXTLOAD with same type
as def of extending instruction.

Diff Detail

Repository
rL LLVM

Event Timeline

Petar.Avramovic created this revision.Jan 18 2019, 8:07 AM
Herald added subscribers: volkan, arichardson, kristof.beyls and 2 others. · View Herald TranscriptJan 18 2019, 8:07 AM
Petar.Avramovic added a child revision: D57099: [MIPS GlobalISel] Select zero extending and sign extending load.Jan 23 2019, 6:41 AM
atanasyan accepted this revision.Jan 23 2019, 12:13 PM

LGTM

This revision is now accepted and ready to land.Jan 23 2019, 12:13 PM
Closed by commit rL352037: [MIPS GlobalISel] Combine extending loads (authored by Petar.Avramovic). · Explain WhyJan 24 2019, 2:11 AM
This revision was automatically updated to reflect the committed changes.
Herald added subscribers: llvm-commits, jrtc27. · View Herald TranscriptJan 24 2019, 2:11 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
11 lines
test/
CodeGen/
Mips/
GlobalISel/
mips-prelegalizer-combiner/
50 lines
188 lines

Diff 183270

llvm/trunk/lib/Target/Mips/MipsPreLegalizerCombiner.cpp

//=== lib/CodeGen/GlobalISel/MipsPreLegalizerCombiner.cpp --------------===// //=== lib/CodeGen/GlobalISel/MipsPreLegalizerCombiner.cpp --------------===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This pass does combining of machine instructions at the generic MI level, // This pass does combining of machine instructions at the generic MI level,
// before the legalizer. // before the legalizer.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "MipsTargetMachine.h" #include "MipsTargetMachine.h"
#include "llvm/CodeGen/GlobalISel/Combiner.h" #include "llvm/CodeGen/GlobalISel/Combiner.h"
#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
#include "llvm/CodeGen/GlobalISel/CombinerInfo.h" #include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TargetPassConfig.h"
#define DEBUG_TYPE "mips-prelegalizer-combiner" #define DEBUG_TYPE "mips-prelegalizer-combiner"
using namespace llvm; using namespace llvm;
namespace { namespace {
class MipsPreLegalizerCombinerInfo : public CombinerInfo { class MipsPreLegalizerCombinerInfo : public CombinerInfo {
public: public:
MipsPreLegalizerCombinerInfo() MipsPreLegalizerCombinerInfo()
: CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false, : CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
/*LegalizerInfo*/ nullptr) {} /*LegalizerInfo*/ nullptr) {}
virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI, virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
MachineIRBuilder &B) const override; MachineIRBuilder &B) const override;
}; };
bool MipsPreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer, bool MipsPreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
MachineInstr &MI, MachineInstr &MI,
MachineIRBuilder &B) const { MachineIRBuilder &B) const {
CombinerHelper Helper(Observer, B);
switch (MI.getOpcode()) {
default:
return false;
case TargetOpcode::G_LOAD:
case TargetOpcode::G_SEXTLOAD:
case TargetOpcode::G_ZEXTLOAD:
return Helper.tryCombineExtendingLoads(MI);
}
return false; return false;
} }
// Pass boilerplate // Pass boilerplate
// ================ // ================
class MipsPreLegalizerCombiner : public MachineFunctionPass { class MipsPreLegalizerCombiner : public MachineFunctionPass {
public: public:
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=mips-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @load1_s8_to_load1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_load2_s32(i16* %px) {entry: ret void}
...
---
name: load1_s8_to_load1_s32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load1_s8_to_load1_s32
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1 from %ir.px)
; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
%2:_(s32) = G_ANYEXT %1(s8)
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: load2_s16_to_load2_s32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load2_s16_to_load2_s32
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2 from %ir.px)
; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.px)
%2:_(s32) = G_ANYEXT %1(s16)
$v0 = COPY %2(s32)
RetRA implicit $v0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=mips-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void}
...
---
name: load1_s8_to_zextLoad1_s32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
%2:_(s32) = G_ZEXT %1(s8)
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: load2_s16_to_zextLoad2_s32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2 from %ir.px)
; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.px)
%2:_(s32) = G_ZEXT %1(s16)
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: load1_s8_to_zextLoad1_s16
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s16) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXTLOAD]](s16)
; MIPS32: $v0 = COPY [[ANYEXT]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
%2:_(s16) = G_ZEXT %1(s8)
%3:_(s32) = G_ANYEXT %2(s16)
$v0 = COPY %3(s32)
RetRA implicit $v0
...
---
name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
%2:_(s16) = G_ZEXT %1(s8)
%3:_(s32) = G_ZEXT %2(s16)
$v0 = COPY %3(s32)
RetRA implicit $v0
...
---
name: load1_s8_to_sextLoad1_s32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
%2:_(s32) = G_SEXT %1(s8)
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: load2_s16_to_sextLoad2_s32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2 from %ir.px)
; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.px)
%2:_(s32) = G_SEXT %1(s16)
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: load1_s8_to_sextLoad1_s16
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s16) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXTLOAD]](s16)
; MIPS32: $v0 = COPY [[ANYEXT]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
%2:_(s16) = G_SEXT %1(s8)
%3:_(s32) = G_ANYEXT %2(s16)
$v0 = COPY %3(s32)
RetRA implicit $v0
...
---
name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
%2:_(s16) = G_SEXT %1(s8)
%3:_(s32) = G_SEXT %2(s16)
$v0 = COPY %3(s32)
RetRA implicit $v0
...