[PPC64][PPC] add tests for R_PPC64_REL14 R_PPC_REL14

[martell]

Summary

As a follow up to rLLD348255
I wanted to add some tests to ensure we don't regress the creation of these relocations in future on the generation side from llvm

[martell]

add context

[nemanjai]

@sfertile Do you have any comments regarding this as you're most familiar with this part of the PPC backend?

[sfertile]

Overall patch LGTM. Thanks for adding this. I have one small question about the llvm-readobj test though. IIUC the python file is used to generate the output files for test/tools/llvm-readobj/reloc-types.test. Do we need to run the python script to get the updated relocs.obj.elf-ppc64 file and update the checks for the added relocations in reloc-types.test?

test/MC/PowerPC/ppc-reloc.s

 # RUN: llvm-mc -triple=powerpc-unknown-linux-gnu -filetype=obj %s | \
 # RUN: llvm-readobj -r | FileCheck %s
   .section .text
 
   .globl foo
   .type foo,@function
   .align 2
 foo:
   bl printf@plt
+  bl printf
+  beq printf
   bl _GLOBAL_OFFSET_TABLE_@local-4
 .LC1:
   .size foo, . - foo
 
 # CHECK:      Relocations [
 # CHECK-NEXT:   Section {{.*}} .rela.text {
 # CHECK-NEXT:     0x0 R_PPC_PLTREL24 printf 0x0
-# CHECK-NEXT:     0x4 R_PPC_LOCAL24PC _GLOBAL_OFFSET_TABLE_ 0xFFFFFFFC
+# CHECK-NEXT:     0x4 R_PPC_REL24 printf 0x0
+# CHECK-NEXT:     0x8 R_PPC_REL14 printf 0x0
+# CHECK-NEXT:     0xC R_PPC_LOCAL24PC _GLOBAL_OFFSET_TABLE_ 0xFFFFFFFC
 # CHECK-NEXT:   }
 # CHECK-NEXT: ]

test/MC/PowerPC/ppc64-relocs-01.s

 # RUN: llvm-mc -triple=powerpc64-unknown-linux-gnu -filetype=obj %s | \
 # RUN: llvm-readobj -r | FileCheck %s
 
         .section .opd,"aw",@progbits
 access_int64:
         .quad .L.access_int64
         .quad .TOC.@tocbase
         .quad 0
         .text
 .L.access_int64:
         ld 4, .LC1@toc(2)
         bl sin
+        beq sin
 
         .section .toc,"aw",@progbits
 .LC1:
         .tc number64[TC],number64
         .data
         .globl number64
 number64:
         .quad 10
 
 # CHECK:      Relocations [
 
 # The relocations in .rela.text are the 'number64' load using a
 # R_PPC64_TOC16_DS against the .toc and the 'sin' external function
 # address using a R_PPC64_REL24
 # CHECK:        Section ({{[0-9]+}}) .rela.text {
 # CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_DS .toc
 # CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_REL24    sin
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_REL14    sin
 # CHECK-NEXT:   }
 
 # The .opd entry for the 'access_int64' function creates 2 relocations:
 # 1. A R_PPC64_ADDR64 against the .text segment plus addend (the function
 #    address itself);
 # 2. And a R_PPC64_TOC against no symbol (the linker will replace for the
 #    module's TOC base).
 # CHECK:        Section ({{[0-9]+}}) .rela.opd {

test/tools/llvm-readobj/Inputs/relocs.py

 
 class Relocs_Elf_PPC64(Enum):
   R_PPC64_NONE                = 0
   R_PPC64_ADDR32              = 1
   R_PPC64_ADDR16_LO           = 4
   R_PPC64_ADDR16_HI           = 5
   R_PPC64_ADDR14              = 7
   R_PPC64_REL24               = 10
+  R_PPC64_REL14               = 11
+  R_PPC64_REL14_BRTAKEN       = 12
+  R_PPC64_REL14_BRNTAKEN      = 13
   R_PPC64_REL32               = 26
   R_PPC64_ADDR64              = 38
   R_PPC64_ADDR16_HIGHER       = 39
   R_PPC64_ADDR16_HIGHEST      = 41
   R_PPC64_REL64               = 44
   R_PPC64_TOC16               = 47
   R_PPC64_TOC16_LO            = 48
   R_PPC64_TOC16_HA            = 50