[PowerPC] Fix a conversion is not considered when the ISD::BR_CC node making the instruction selection

[HLJ2009]

Summary

Now llc produces the same code for the following ir code.

define i64 @testi64slt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
entry:
  %cmp1 = icmp eq i64 %c3, %c4
  %cmp3tmp = icmp eq i64 %c1, %c2
  %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
  br i1 %cmp3, label %iftrue, label %iffalse
iftrue:
  ret i64 %a1
iffalse:
  ret i64 %a2
}

define i64 @testi64ult(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
entry:
  %cmp1 = icmp eq i64 %c3, %c4
  %cmp3tmp = icmp eq i64 %c1, %c2
  %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
  br i1 %cmp3, label %iftrue, label %iffalse
iftrue:
  ret i64 %a1
iffalse:
  ret i64 %a2
}

But from the semantics of ir, these are not equivalent. Because a signed comparison of i1
values produces the opposite result to an unsigned one if the condition code includes
less-than or greater-than. This is so because 1 is the most negative signed i1 number and
the most positive unsigned i1 number. The CR-logical operations used for such comparisons
are non-commutative so for signed comparisons vs. unsigned ones, the input operands just
need to be swapped.

[HLJ2009]

Test cases have been modified to make code changes

[HLJ2009]

Using the suggestion to modify the code. Thanks to Steven and Nemanjai.

[steven.zhang]

LGTM.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

if (N->getOperand(2).getValueType() == MVT::i1) {
       case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true;  break;
       case PPC::PRED_LE: Opc = PPC::CRORC;  Swap = true;  break;
       case PPC::PRED_EQ: Opc = PPC::CREQV;  Swap = false; break;
       case PPC::PRED_GE: Opc = PPC::CRORC;  Swap = false; break;
       case PPC::PRED_GT: Opc = PPC::CRANDC; Swap = false; break;
       case PPC::PRED_NE: Opc = PPC::CRXOR;  Swap = false; break;
       }
 
+      // A signed comparison of i1 values produces the opposite result to an
+      // unsigned one if the condition code includes less-than or greater-than.
+      // This is because 1 is the most negative signed i1 number and the most
+      // positive unsigned i1 number. The CR-logical operations used for such
+      // comparisons are non-commutative so for signed comparisons vs. unsigned
+      // ones, the input operands just need to be swapped.
+      if (ISD::isSignedIntSetCC(CC))
+        Swap = !Swap;
+
       SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
                                              N->getOperand(Swap ? 3 : 2),
                                              N->getOperand(Swap ? 2 : 3)), 0);
       CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other, BitComp, N->getOperand(4),
                            N->getOperand(0));
       return;
     }
 

llvm/test/CodeGen/PowerPC/brcond.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
 
 define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
 ; CHECK-LABEL: testi32slt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw 0, 5, 6
 ; CHECK-NEXT:    cmpw 1, 3, 4
-; CHECK-NEXT:    crorc 20, 6, 2
+; CHECK-NEXT:    crorc 20, 2, 6
 ; CHECK-NEXT:    bc 12, 20, .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    extsw 3, 7
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB0_2: # %iffalse
 ; CHECK-NEXT:    extsw 3, 8
 ; CHECK-NEXT:    blr
 entry:
iffalse:
   ret i32 %a2
 }
 
 define signext i32 @testi32sle(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
 ; CHECK-LABEL: testi32sle:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw 0, 5, 6
 ; CHECK-NEXT:    cmpw 1, 3, 4
-; CHECK-NEXT:    crandc 20, 6, 2
+; CHECK-NEXT:    crandc 20, 2, 6
 ; CHECK-NEXT:    bc 12, 20, .LBB2_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    extsw 3, 7
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB2_2: # %iffalse
 ; CHECK-NEXT:    extsw 3, 8
 ; CHECK-NEXT:    blr
 entry:
iffalse:
   ret i32 %a2
 }
 
 define signext i32 @testi32sge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
 ; CHECK-LABEL: testi32sge:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw 0, 5, 6
 ; CHECK-NEXT:    cmpw 1, 3, 4
-; CHECK-NEXT:    crandc 20, 2, 6
+; CHECK-NEXT:    crandc 20, 6, 2
 ; CHECK-NEXT:    bc 12, 20, .LBB5_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    extsw 3, 7
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB5_2: # %iffalse
 ; CHECK-NEXT:    extsw 3, 8
 ; CHECK-NEXT:    blr
 entry:
iffalse:
   ret i32 %a2
 }
 
 define signext i32 @testi32sgt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
 ; CHECK-LABEL: testi32sgt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw 0, 5, 6
 ; CHECK-NEXT:    cmpw 1, 3, 4
-; CHECK-NEXT:    crorc 20, 2, 6
+; CHECK-NEXT:    crorc 20, 6, 2
 ; CHECK-NEXT:    bc 12, 20, .LBB7_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    extsw 3, 7
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB7_2: # %iffalse
 ; CHECK-NEXT:    extsw 3, 8
 ; CHECK-NEXT:    blr
 entry:
iffalse:
   ret i32 %a2
 }
 
 define i64 @testi64slt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
 ; CHECK-LABEL: testi64slt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd 5, 6
 ; CHECK-NEXT:    cmpd 1, 3, 4
-; CHECK-NEXT:    crorc 20, 6, 2
+; CHECK-NEXT:    crorc 20, 2, 6
 ; CHECK-NEXT:    bc 12, 20, .LBB10_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    mr 3, 7
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB10_2: # %iffalse
 ; CHECK-NEXT:    mr 3, 8
 ; CHECK-NEXT:    blr
 entry:
iffalse:
   ret i64 %a2
 }
 
 define i64 @testi64sle(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
 ; CHECK-LABEL: testi64sle:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd 5, 6
 ; CHECK-NEXT:    cmpd 1, 3, 4
-; CHECK-NEXT:    crandc 20, 6, 2
+; CHECK-NEXT:    crandc 20, 2, 6
 ; CHECK-NEXT:    bc 12, 20, .LBB12_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    mr 3, 7
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB12_2: # %iffalse
 ; CHECK-NEXT:    mr 3, 8
 ; CHECK-NEXT:    blr
 entry:
iffalse:
   ret i64 %a2
 }
 
 define i64 @testi64sge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
 ; CHECK-LABEL: testi64sge:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd 5, 6
 ; CHECK-NEXT:    cmpd 1, 3, 4
-; CHECK-NEXT:    crandc 20, 2, 6
+; CHECK-NEXT:    crandc 20, 6, 2
 ; CHECK-NEXT:    bc 12, 20, .LBB15_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    mr 3, 7
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB15_2: # %iffalse
 ; CHECK-NEXT:    mr 3, 8
 ; CHECK-NEXT:    blr
 entry:
iffalse:
   ret i64 %a2
 }
 
 define i64 @testi64sgt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
 ; CHECK-LABEL: testi64sgt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpd 5, 6
 ; CHECK-NEXT:    cmpd 1, 3, 4
-; CHECK-NEXT:    crorc 20, 2, 6
+; CHECK-NEXT:    crorc 20, 6, 2
 ; CHECK-NEXT:    bc 12, 20, .LBB17_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    mr 3, 7
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB17_2: # %iffalse
 ; CHECK-NEXT:    mr 3, 8
 ; CHECK-NEXT:    blr
 entry:
iffalse:
   ret i64 %a2
 }
 
 define float @testfloatslt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
 ; CHECK-LABEL: testfloatslt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NEXT:    fcmpu 1, 1, 2
-; CHECK-NEXT:    crorc 20, 6, 2
+; CHECK-NEXT:    crorc 20, 2, 6
 ; CHECK-NEXT:    bc 12, 20, .LBB20_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB20_2: # %iffalse
 ; CHECK-NEXT:    fmr 1, 6
 ; CHECK-NEXT:    blr
 entry:
iffalse:
   ret float %a2
 }
 
 define float @testfloatsle(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
 ; CHECK-LABEL: testfloatsle:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NEXT:    fcmpu 1, 1, 2
-; CHECK-NEXT:    crandc 20, 6, 2
+; CHECK-NEXT:    crandc 20, 2, 6
 ; CHECK-NEXT:    bc 12, 20, .LBB22_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB22_2: # %iffalse
 ; CHECK-NEXT:    fmr 1, 6
 ; CHECK-NEXT:    blr
 entry:
iffalse:
   ret float %a2
 }
 
 define float @testfloatsge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
 ; CHECK-LABEL: testfloatsge:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NEXT:    fcmpu 1, 1, 2
-; CHECK-NEXT:    crandc 20, 2, 6
+; CHECK-NEXT:    crandc 20, 6, 2
 ; CHECK-NEXT:    bc 12, 20, .LBB25_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB25_2: # %iffalse
 ; CHECK-NEXT:    fmr 1, 6
 ; CHECK-NEXT:    blr
 entry:
iffalse:
   ret float %a2
 }
 
 define float @testfloatsgt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
 ; CHECK-LABEL: testfloatsgt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NEXT:    fcmpu 1, 1, 2
-; CHECK-NEXT:    crorc 20, 2, 6
+; CHECK-NEXT:    crorc 20, 6, 2
 ; CHECK-NEXT:    bc 12, 20, .LBB27_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB27_2: # %iffalse
 ; CHECK-NEXT:    fmr 1, 6
 ; CHECK-NEXT:    blr
 entry:
iffalse:
   ret float %a2
 }
 
 define double @testdoubleslt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
 ; CHECK-LABEL: testdoubleslt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NEXT:    fcmpu 1, 1, 2
-; CHECK-NEXT:    crorc 20, 6, 2
+; CHECK-NEXT:    crorc 20, 2, 6
 ; CHECK-NEXT:    bc 12, 20, .LBB30_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB30_2: # %iffalse
 ; CHECK-NEXT:    fmr 1, 6
 ; CHECK-NEXT:    blr
 entry:
iffalse:
   ret double %a2
 }
 
 define double @testdoublesle(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
 ; CHECK-LABEL: testdoublesle:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NEXT:    fcmpu 1, 1, 2
-; CHECK-NEXT:    crandc 20, 6, 2
+; CHECK-NEXT:    crandc 20, 2, 6
 ; CHECK-NEXT:    bc 12, 20, .LBB32_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB32_2: # %iffalse
 ; CHECK-NEXT:    fmr 1, 6
 ; CHECK-NEXT:    blr
 entry:
iffalse:
   ret double %a2
 }
 
 define double @testdoublesge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
 ; CHECK-LABEL: testdoublesge:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NEXT:    fcmpu 1, 1, 2
-; CHECK-NEXT:    crandc 20, 2, 6
+; CHECK-NEXT:    crandc 20, 6, 2
 ; CHECK-NEXT:    bc 12, 20, .LBB35_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB35_2: # %iffalse
 ; CHECK-NEXT:    fmr 1, 6
 ; CHECK-NEXT:    blr
 entry:
iffalse:
   ret double %a2
 }
 
 define double @testdoublesgt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
 ; CHECK-LABEL: testdoublesgt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NEXT:    fcmpu 1, 1, 2
-; CHECK-NEXT:    crorc 20, 2, 6
+; CHECK-NEXT:    crorc 20, 6, 2
 ; CHECK-NEXT:    bc 12, 20, .LBB37_2
 ; CHECK-NEXT:  # %bb.1: # %iftrue
 ; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB37_2: # %iffalse
 ; CHECK-NEXT:    fmr 1, 6
 ; CHECK-NEXT:    blr
 entry: