[COFF, ARM64] Add __getReg intrinsic

[mgrang]

I have some questions about the behavior of getReg:

__getReg ultimately invokes getRegisterByName in http://llvm.org/doxygen/AArch64ISelLowering_8cpp_source.html.

You can __getReg only those registers which appear in the switch-case inside that function. Even then the logic there checks if the requested register is reserved. If not, then it makes the reg = 0 which results in "Invalid register name" error.

I am not sure how this should be dealt with. Is it fine to add all regs (0-31) to the switch-case in getRegisterByName? And should the checks for isRegReserved be bypassed for COFF?

[mstorsjo]

In D52838#1253998, @mgrang wrote:

I have some questions about the behavior of getReg:

__getReg ultimately invokes getRegisterByName in http://llvm.org/doxygen/AArch64ISelLowering_8cpp_source.html.

You can __getReg only those registers which appear in the switch-case inside that function. Even then the logic there checks if the requested register is reserved. If not, then it makes the reg = 0 which results in "Invalid register name" error.

I am not sure how this should be dealt with. Is it fine to add all regs (0-31) to the switch-case in getRegisterByName? And should the checks for isRegReserved be bypassed for COFF?

I don't really know about this one, I'll add a few more people who might be able to comment on it. @efriedma @peter.smith

[efriedma]

read_register only allows reading reserved registers because reading an allocatable register is meaningless (the compiler can store arbitrary data in allocatable registers).

The same applies to __getReg; given that, I would assume real code doesn't use anything other than __getReg(18) or __getReg(31), so we can just reject any other constant.

lib/CodeGen/CGBuiltin.cpp

6583

Semantic checks belong in SemaChecking, not here. IIRC you can request constant checking in the .def file, although I don't remember the syntax off the top of my head.

6592

There is no register named x31. Maybe you need a special case here to use "sp" if the input is 31?

[efriedma]

lib/CodeGen/CGBuiltin.cpp

6589

Could you just write this as std::string Reg = Value == 31 ? "sp" : "x" + Value.toString(10);, and get rid of StrVal?

[efriedma]

Needs a testcase for the error message like we have for other intrinsics in test/Sema/builtins-arm64.c . Otherwise LGTM.

[efriedma]

LGTM

include/clang/Basic/BuiltinsAArch64.def

 TARGET_HEADER_BUILTIN(_InterlockedExchange64,    "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd64, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedExchangeSub64, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedIncrement64,   "LLiLLiD*",    "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedOr64,          "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedXor64,         "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 
 TARGET_HEADER_BUILTIN(_ReadWriteBarrier, "v", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(__getReg, "ULLii", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 
 #undef BUILTIN
 #undef LANGBUILTIN
 #undef TARGET_HEADER_BUILTIN

lib/CodeGen/CGBuiltin.cpp

if (BuiltinID == AArch64::BI__builtin_arm_strex ||
 
     Function *F = CGM.getIntrinsic(BuiltinID == AArch64::BI__builtin_arm_stlex
                                        ? Intrinsic::aarch64_stlxr
                                        : Intrinsic::aarch64_stxr,
                                    StoreAddr->getType());
     return Builder.CreateCall(F, {StoreVal, StoreAddr}, "stxr");
   }
 
+  if (BuiltinID == AArch64::BI__getReg) {
+    APSInt Value;
+    if (!E->getArg(0)->EvaluateAsInt(Value, CGM.getContext()))
+      llvm_unreachable("Sema will ensure that the parameter is constant");
+
+    LLVMContext &Context = CGM.getLLVMContext();
+    std::string Reg = Value == 31 ? "sp" : "x" + Value.toString(10);
+
+    llvm::Metadata *Ops[] = {llvm::MDString::get(Context, Reg)};
+    llvm::MDNode *RegName = llvm::MDNode::get(Context, Ops);
+    llvm::Value *Metadata = llvm::MetadataAsValue::get(Context, RegName);
+
+    llvm::Value *F =
+        CGM.getIntrinsic(llvm::Intrinsic::read_register, {Int64Ty});
+    return Builder.CreateCall(F, Metadata);
+  }
+
   if (BuiltinID == AArch64::BI__builtin_arm_clrex) {
     Function *F = CGM.getIntrinsic(Intrinsic::aarch64_clrex);
     return Builder.CreateCall(F);
   }
 
   if (BuiltinID == AArch64::BI_ReadWriteBarrier)
     return Builder.CreateFence(llvm::AtomicOrdering::SequentiallyConsistent,
                                llvm::SyncScope::SingleThread);

lib/Headers/intrin.h

 }
 static __inline__ void __DEFAULT_FN_ATTRS
 __nop(void) {
   __asm__ volatile ("nop");
 }
 #endif
 
 /*----------------------------------------------------------------------------*\
+|* MS AArch64 specific
+\*----------------------------------------------------------------------------*/
+#if defined(__aarch64__)
+unsigned __int64 __getReg(int);
+#endif
+
+/*----------------------------------------------------------------------------*\
 |* Privileged intrinsics
 \*----------------------------------------------------------------------------*/
 #if defined(__i386__) || defined(__x86_64__)
 static __inline__ unsigned __int64 __DEFAULT_FN_ATTRS
 __readmsr(unsigned long __register) {
   // Loads the contents of a 64-bit model specific register (MSR) specified in
   // the ECX register into registers EDX:EAX. The EDX register is loaded with
   // the high-order 32 bits of the MSR and the EAX register is loaded with the

lib/Sema/SemaChecking.cpp

if (BuiltinID == AArch64::BI__builtin_arm_rsr64 ||
     return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, true);
 
   if (BuiltinID == AArch64::BI__builtin_arm_rsr ||
       BuiltinID == AArch64::BI__builtin_arm_rsrp ||
       BuiltinID == AArch64::BI__builtin_arm_wsr ||
       BuiltinID == AArch64::BI__builtin_arm_wsrp)
     return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, true);
 
+  if (BuiltinID == AArch64::BI__getReg)
+    return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31);
+
   if (CheckNeonBuiltinFunctionCall(BuiltinID, TheCall))
     return true;
 
   // For intrinsics which take an immediate value as part of the instruction,
   // range check them here.
   unsigned i = 0, l = 0, u = 0;
   switch (BuiltinID) {
   default: return false;

test/CodeGen/arm64-microsoft-intrinsics.c

 // CHECK-LINUX: error: implicit declaration of function '__sevl'
 
 void check_ReadWriteBarrier() {
   _ReadWriteBarrier();
 }
 
 // CHECK-MSVC: fence syncscope("singlethread")
 // CHECK-LINUX: error: implicit declaration of function '_ReadWriteBarrier'
+
+unsigned __int64 check_getReg() {
+  unsigned volatile __int64 reg;
+  reg = __getReg(18);
+  reg = __getReg(31);
+  return reg;
+}
+
+// CHECK-MSVC: call i64 @llvm.read_register.i64(metadata !2)
+// CHECK-MSVC: call i64 @llvm.read_register.i64(metadata !3)
+// CHECK-MSVC: !2 = !{!"x18"}
+// CHECK-MSVC: !3 = !{!"sp"}