[AMDGPU] Rename pass "isel" to amdgpu-isel

[MaskRay]

Summary

"isel" is a misleading name

[echristo]

LGTM.

[arsenm]

Why do other targets do this? -debug already behaves weirdly since -debug prints more during SelectionDAG than -debug-only=isel, and this will make that worse?

[MaskRay]

In D52759#1251949, @arsenm wrote:

Why do other targets do this? -debug already behaves weirdly since -debug prints more during SelectionDAG than -debug-only=isel, and this will make that worse?

Other targets don't have a *-isel pass. I am unclear why AMDGPU has the isel that misguided people to do things like -stop-after=isel (which does not work if they don't build the AMDGPU target)

[arsenm]

In D52759#1252115, @MaskRay wrote:

In D52759#1251949, @arsenm wrote:

Why do other targets do this? -debug already behaves weirdly since -debug prints more during SelectionDAG than -debug-only=isel, and this will make that worse?

Other targets don't have a *-isel pass. I am unclear why AMDGPU has the isel that misguided people to do things like -stop-after=isel (which does not work if they don't build the AMDGPU target)

This sounds broken. The target "owns" the isel pass, so I would expect every target to call this isel, and it wouldn't matter what target you're using

[arsenm]

LGTM. The pass name system here is really broken. I don't see how this would break -stop-after without building the target

[MaskRay]

In D52759#1253434, @arsenm wrote:

LGTM. The pass name system here is really broken. I don't see how this would break -stop-after without building the target

Thanks. It is just that the pass name does not have a namespace... AMDGPU used the generic name "isel" which might make people confused.

If they don't build the AMDGPU target and think "isel" is a valid pass:

% llc -stop-after=isel -o - test/CodeGen/AArch64/sdag-store-merging-bug.ll
LLVM ERROR: "isel" pass is not registered.

llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

public:
   bool runOnMachineFunction(MachineFunction &MF) override;
 protected:
   // Include the pieces autogenerated from the target description.
 #include "R600GenDAGISel.inc"
 };
 
 }  // end anonymous namespace
 
-INITIALIZE_PASS_BEGIN(AMDGPUDAGToDAGISel, "isel",
+INITIALIZE_PASS_BEGIN(AMDGPUDAGToDAGISel, "amdgpu-isel",
                       "AMDGPU DAG->DAG Pattern Instruction Selection", false, false)
 INITIALIZE_PASS_DEPENDENCY(AMDGPUArgumentUsageInfo)
 INITIALIZE_PASS_DEPENDENCY(AMDGPUPerfHintAnalysis)
 INITIALIZE_PASS_DEPENDENCY(LegacyDivergenceAnalysis)
-INITIALIZE_PASS_END(AMDGPUDAGToDAGISel, "isel",
+INITIALIZE_PASS_END(AMDGPUDAGToDAGISel, "amdgpu-isel",
                     "AMDGPU DAG->DAG Pattern Instruction Selection", false, false)
 
 /// This pass converts a legalized DAG into a AMDGPU-specific
 // DAG, ready for instruction scheduling.
 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine *TM,
                                         CodeGenOpt::Level OptLevel) {
   return new AMDGPUDAGToDAGISel(TM, OptLevel);
 }

llvm/trunk/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll

-; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -stop-after=isel -o - %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefix=GCN %s
 
 ; Type legalization for illegal FP type results was dropping invariant
 ; and dereferenceable flags.
 
 ; GCN: BUFFER_LOAD_USHORT{{.*}} :: (dereferenceable invariant load 2 from %ir.ptr, addrspace 4)
 define half @legalize_f16_load(half addrspace(4)* dereferenceable(4) %ptr) {
   %load = load half, half addrspace(4)* %ptr, !invariant.load !0
   %add = fadd half %load, 1.0
   ret half %add
 }
 
 !0 = !{}

llvm/trunk/test/CodeGen/AMDGPU/print-mir-custom-pseudo.ll

-; RUN: llc -mtriple=amdgcn--amdpal -mcpu=fiji -print-after=isel -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=fiji -print-after=amdgpu-isel -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=SI %s
 
 ; This checks that the -print-after of MIR containing a target custom pseudo
 ; value works correctly.
 
 ; SI: TargetCustom
 
 target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
 target triple = "amdgcn--amdpal"
 
 define dllexport amdgpu_ps <2 x float> @_amdgpu_ps_main(i32 inreg, i32 inreg, i32 inreg, i32 inreg, <2 x float>, <2 x float>, <2 x float>, <3 x float>, <2 x float>, <2 x float>, <2 x float>, float, float, float, float, float, i32, i32, i32, i32) local_unnamed_addr {
 .entry:
   %res = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
   ret <2 x float> %res
 }
 
 declare <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32)