[ARM] Remove non-existent cpu arm1176j-s and use mpcore for v6k

[peter.smith]

Summary

The ARMTargetParser.def contains an entry for arm1176j-s which is the default for the ArmV6K architecture. This cpu does not exist, there are only arm1176jz-s and arm1176jzf-s and they are both architecture ArmV6KZ. The only CPUs that are actually ArmV6K are the mpcore, mpcore_nofpu and later revisions of the arm1136 family r1px (which we don't have a table entry for).

This patch removes the arm1176j-s and makes mpcore the default for armv6k. I'll post the update to the clang tests to account for this change in a separate review.

It is difficult to find a simple canonical location for all the different CPUs and what architectures they have. The allowable trademarks for arm11 CPUs are available in https://www.arm.com/company/policies/trademarks/arm-trademark-list/arm11-trademark . The architecture each CPU implements is available in the Technical Reference Manual (TRM) on the Arm website http://infocenter.arm.com/help/topic/com.arm.doc.set.arm11/index.html

This is an alternative fix for D18086

[falstaff84]

With that building CONFIG_ARCH_MULTI_V6=y seems to work. Also LLVM emits the correct CPU:

...
	.cpu	mpcore
...

[rengolin]

Thanks Peter! LGTM.

llvm/trunk/include/llvm/Support/ARMTargetParser.def

 ARM_CPU_NAME("arm968e-s", ARMV5TE, FK_NONE, false, ARM::AEK_NONE)
 ARM_CPU_NAME("arm10e", ARMV5TE, FK_NONE, false, ARM::AEK_NONE)
 ARM_CPU_NAME("arm1020e", ARMV5TE, FK_NONE, false, ARM::AEK_NONE)
 ARM_CPU_NAME("arm1022e", ARMV5TE, FK_NONE, true, ARM::AEK_NONE)
 ARM_CPU_NAME("arm926ej-s", ARMV5TEJ, FK_NONE, true, ARM::AEK_NONE)
 ARM_CPU_NAME("arm1136j-s", ARMV6, FK_NONE, false, ARM::AEK_NONE)
 ARM_CPU_NAME("arm1136jf-s", ARMV6, FK_VFPV2, true, ARM::AEK_NONE)
 ARM_CPU_NAME("arm1136jz-s", ARMV6, FK_NONE, false, ARM::AEK_NONE)
-ARM_CPU_NAME("arm1176j-s", ARMV6K, FK_NONE, true, ARM::AEK_NONE)
-ARM_CPU_NAME("arm1176jz-s", ARMV6KZ, FK_NONE, false, ARM::AEK_NONE)
-ARM_CPU_NAME("mpcore", ARMV6K, FK_VFPV2, false, ARM::AEK_NONE)
+ARM_CPU_NAME("mpcore", ARMV6K, FK_VFPV2, true, ARM::AEK_NONE)
 ARM_CPU_NAME("mpcorenovfp", ARMV6K, FK_NONE, false, ARM::AEK_NONE)
+ARM_CPU_NAME("arm1176jz-s", ARMV6KZ, FK_NONE, false, ARM::AEK_NONE)
 ARM_CPU_NAME("arm1176jzf-s", ARMV6KZ, FK_VFPV2, true, ARM::AEK_NONE)
 ARM_CPU_NAME("arm1156t2-s", ARMV6T2, FK_NONE, true, ARM::AEK_NONE)
 ARM_CPU_NAME("arm1156t2f-s", ARMV6T2, FK_VFPV2, false, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-m0", ARMV6M, FK_NONE, true, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-m0plus", ARMV6M, FK_NONE, false, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-m1", ARMV6M, FK_NONE, false, ARM::AEK_NONE)
 ARM_CPU_NAME("sc000", ARMV6M, FK_NONE, false, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-a5", ARMV7A, FK_NEON_VFPV4, false,

llvm/trunk/unittests/Support/TargetParserTest.cpp

TEST(TargetParserTest, testARMCPU) {
   EXPECT_TRUE(testARMCPU("arm926ej-s", "armv5tej", "none",
                          ARM::AEK_DSP, "5TEJ"));
   EXPECT_TRUE(testARMCPU("arm1136j-s", "armv6", "none",
                          ARM::AEK_DSP, "6"));
   EXPECT_TRUE(testARMCPU("arm1136jf-s", "armv6", "vfpv2",
                          ARM::AEK_DSP, "6"));
   EXPECT_TRUE(testARMCPU("arm1136jz-s", "armv6", "none",
                          ARM::AEK_DSP, "6"));
-  EXPECT_TRUE(testARMCPU("arm1176j-s", "armv6k", "none",
-                         ARM::AEK_DSP, "6K"));
   EXPECT_TRUE(testARMCPU("arm1176jz-s", "armv6kz", "none",
                          ARM::AEK_SEC | ARM::AEK_DSP, "6KZ"));
   EXPECT_TRUE(testARMCPU("mpcore", "armv6k", "vfpv2",
                          ARM::AEK_DSP, "6K"));
   EXPECT_TRUE(testARMCPU("mpcorenovfp", "armv6k", "none",
                          ARM::AEK_DSP, "6K"));
   EXPECT_TRUE(testARMCPU("arm1176jzf-s", "armv6kz", "vfpv2",
                          ARM::AEK_SEC | ARM::AEK_DSP, "6KZ"));
EXPECT_TRUE(testARMCPU("iwmmxt", "iwmmxt", "none",
                          ARM::AEK_NONE, "iwmmxt"));
   EXPECT_TRUE(testARMCPU("xscale", "xscale", "none",
                          ARM::AEK_NONE, "xscale"));
   EXPECT_TRUE(testARMCPU("swift", "armv7s", "neon-vfpv4",
                          ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
                          "7-S"));
 }
 
-static constexpr unsigned NumARMCPUArchs = 83;
+static constexpr unsigned NumARMCPUArchs = 82;
 
 TEST(TargetParserTest, testARMCPUArchList) {
   SmallVector<StringRef, NumARMCPUArchs> List;
   ARM::fillValidCPUArchList(List);
 
   // No list exists for these in this test suite, so ensure all are
   // valid, and match the expected 'magic' count.
   EXPECT_EQ(List.size(), NumARMCPUArchs);
EXPECT_TRUE(
                           ARMBuildAttrs::CPUArch::v5TE));
   EXPECT_TRUE(
       testARMArch("armv5tej", "arm926ej-s", "v5e",
                           ARMBuildAttrs::CPUArch::v5TEJ));
   EXPECT_TRUE(
       testARMArch("armv6", "arm1136jf-s", "v6",
                           ARMBuildAttrs::CPUArch::v6));
   EXPECT_TRUE(
-      testARMArch("armv6k", "arm1176j-s", "v6k",
+      testARMArch("armv6k", "mpcore", "v6k",
                           ARMBuildAttrs::CPUArch::v6K));
   EXPECT_TRUE(
       testARMArch("armv6t2", "arm1156t2-s", "v6t2",
                           ARMBuildAttrs::CPUArch::v6T2));
   EXPECT_TRUE(
       testARMArch("armv6kz", "arm1176jzf-s", "v6kz",
                           ARMBuildAttrs::CPUArch::v6KZ));
   EXPECT_TRUE(