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Differential D52009

[WebAssembly] SIMD neg
ClosedPublic

Authored by tlively on Sep 12 2018, 6:34 PM.

Details

Reviewers
aheejin
dschuff
Commits
rG88b7443f9455: [WebAssembly] SIMD neg
rL342296: [WebAssembly] SIMD neg
Summary

Depends on D52007.

Diff Detail

Repository
rL LLVM

Event Timeline

tlively created this revision.Sep 12 2018, 6:34 PM
Herald added subscribers: llvm-commits, sunfish, jgravelle-google, sbc100. · View Herald TranscriptSep 12 2018, 6:34 PM
Harbormaster completed remote builds in B22574: Diff 165191.Sep 12 2018, 6:34 PM
tlively updated this revision to Diff 165192.Sep 12 2018, 6:43 PM
  • Add encoding tests (and fix encoding)
Harbormaster completed remote builds in B22575: Diff 165192.Sep 12 2018, 6:43 PM
aheejin edited parent revisions, added: D52007: [WebAssembly][NFC] Move SIMD encoding tests to dedicated file; removed: D5007: [BUG] Fix regression in the instruction combiner after r214385.Sep 12 2018, 6:58 PM

I think this is dependent on D52007. Fixed it. By the way, the diff looks like it contains D52007's diff too. Could you fix it? You can do relative diff by
arc diff --update D52009 DIVISION_TO_COMPARE

tlively edited the summary of this revision. (Show Details)Sep 13 2018, 12:00 AM
tlively updated this revision to Diff 165205.Sep 13 2018, 12:04 AM
  • Diff from correct revision
tlively added a comment.Sep 13 2018, 12:05 AM

Fixed! Sorry about that. It's much more sane now.

aheejin added inline comments.Sep 14 2018, 2:24 PM
lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
157 ↗(On Diff #165205)

Can't this be 0.0 or something like the integer case?

tlively added inline comments.Sep 14 2018, 2:49 PM
lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
157 ↗(On Diff #165205)

No, unfortunately tablegen does not support floating point literals. This is the standard solution used in multiple backends.

aheejin accepted this revision.Sep 14 2018, 3:11 PM
This revision is now accepted and ready to land.Sep 14 2018, 3:11 PM
Closed by commit rL342296: [WebAssembly] SIMD neg (authored by tlively). · Explain WhySep 14 2018, 3:36 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
WebAssembly/
30 lines
test/
CodeGen/
WebAssembly/
69 lines
MC/
WebAssembly/
18 lines

Diff 165600

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

Show First 20 Lines • Show All 128 Lines • ▼ Show 20 Linesmulticlass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 1)>; defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 1)>;
} }
multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop> { multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop> {
defm "" : SIMDBinary<v16i8, "v128", node, name, simdop>; defm "" : SIMDBinary<v16i8, "v128", node, name, simdop>;
defm "" : SIMDBinary<v8i16, "v128", node, name, simdop>; defm "" : SIMDBinary<v8i16, "v128", node, name, simdop>;
defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>; defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>;
defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>; defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>;
} }
multiclass SIMDNeg<ValueType vec_t, string vec, PatFrag splat_pat,
ValueType lane_t, SDNode node, dag lane, bits<32> simdop> {
defm NEG_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec),
(outs), (ins),
[(set
(vec_t V128:$dst),
(vec_t (node
(vec_t (splat_pat lane)),
(vec_t V128:$vec)
))
)],
vec#".neg\t$dst, $vec", vec#".neg", simdop>;
}
multiclass SIMDNegInt<ValueType vec_t, string vec, PatFrag splat_pat,
ValueType lane_t, bits<32> simdop> {
defm "" : SIMDNeg<vec_t, vec, splat_pat, lane_t, sub, (lane_t 0), simdop>;
}
def fpimm0 : FPImmLeaf<fAny, [{ return Imm.isExactlyValue(+0.0); }]>;
multiclass SIMDNegFP<ValueType vec_t, string vec, PatFrag splat_pat,
ValueType lane_t, bits<32> simdop> {
defm "" : SIMDNeg<vec_t, vec, splat_pat, lane_t, fsub, (lane_t fpimm0),
simdop>;
}
multiclass SIMDNot<ValueType vec_t, PatFrag splat_pat, ValueType lane_t> { multiclass SIMDNot<ValueType vec_t, PatFrag splat_pat, ValueType lane_t> {
defm NOT_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), defm NOT_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec),
(outs), (ins), (outs), (ins),
[(set [(set
(vec_t V128:$dst), (vec_t V128:$dst),
(vec_t (xor (vec_t (xor
(vec_t V128:$vec), (vec_t V128:$vec),
(vec_t (splat_pat (lane_t -1))) (vec_t (splat_pat (lane_t -1)))
▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
defm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 32>; defm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 32>;
defm MUL : SIMDBinaryFP<fmul, "mul", 128>; defm MUL : SIMDBinaryFP<fmul, "mul", 128>;
} // isCommutable = 1 } // isCommutable = 1
defm SUB : SIMDBinaryInt<sub, "sub", 28>; defm SUB : SIMDBinaryInt<sub, "sub", 28>;
defm SUB : SIMDBinaryFP<fsub, "sub", 124>; defm SUB : SIMDBinaryFP<fsub, "sub", 124>;
defm DIV : SIMDBinaryFP<fdiv, "div", 126>; defm DIV : SIMDBinaryFP<fdiv, "div", 126>;
defm "" : SIMDNegInt<v16i8, "i8x16", splat16, i32, 35>;
defm "" : SIMDNegInt<v8i16, "i16x8", splat8, i32, 36>;
defm "" : SIMDNegInt<v4i32, "i32x4", splat4, i32, 37>;
defm "" : SIMDNegInt<v2i64, "i64x2", splat2, i64, 38>;
defm "" : SIMDNegFP<v4f32, "f32x4", splat4, f32, 114>;
defm "" : SIMDNegFP<v2f64, "f64x2", splat2, f64, 115>;
let isCommutable = 1 in { let isCommutable = 1 in {
defm AND : SIMDBitwise<and, "and", 59>; defm AND : SIMDBitwise<and, "and", 59>;
defm OR : SIMDBitwise<or, "or", 60>; defm OR : SIMDBitwise<or, "or", 60>;
defm XOR : SIMDBitwise<xor, "xor", 61>; defm XOR : SIMDBitwise<xor, "xor", 61>;
} // isCommutable = 1 } // isCommutable = 1
defm "" : SIMDNot<v16i8, splat16, i32>; defm "" : SIMDNot<v16i8, splat16, i32>;
defm "" : SIMDNot<v8i16, splat8, i32>; defm "" : SIMDNot<v8i16, splat8, i32>;
▲ Show 20 Lines • Show All 213 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/WebAssembly/simd-arith.ll

Show All 40 Lines
; SIMD128-NEXT: .result v128{{$}} ; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i8x16.mul $push0=, $0, $1{{$}} ; SIMD128-NEXT: i8x16.mul $push0=, $0, $1{{$}}
; SIMD128-NEXT: return $pop0{{$}} ; SIMD128-NEXT: return $pop0{{$}}
define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) { define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) {
%a = mul <16 x i8> %x, %y %a = mul <16 x i8> %x, %y
ret <16 x i8> %a ret <16 x i8> %a
} }
; CHECK-LABEL: neg_v16i8:
; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .param v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i8x16.neg $push0=, $0{{$}}
; SIMD128-NEXT: return $pop0{{$}}
define <16 x i8> @neg_v16i8(<16 x i8> %x) {
%a = sub <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0,
i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>,
%x
ret <16 x i8> %a
}
; CHECK-LABEL: and_v16i8: ; CHECK-LABEL: and_v16i8:
; NO-SIMD128-NOT: v128 ; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .param v128, v128{{$}} ; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}} ; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: v128.and $push0=, $0, $1{{$}} ; SIMD128-NEXT: v128.and $push0=, $0, $1{{$}}
; SIMD128-NEXT: return $pop0{{$}} ; SIMD128-NEXT: return $pop0{{$}}
define <16 x i8> @and_v16i8(<16 x i8> %x, <16 x i8> %y) { define <16 x i8> @and_v16i8(<16 x i8> %x, <16 x i8> %y) {
%a = and <16 x i8> %x, %y %a = and <16 x i8> %x, %y
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; SIMD128-NEXT: .result v128{{$}} ; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i16x8.mul $push0=, $0, $1{{$}} ; SIMD128-NEXT: i16x8.mul $push0=, $0, $1{{$}}
; SIMD128-NEXT: return $pop0{{$}} ; SIMD128-NEXT: return $pop0{{$}}
define <8 x i16> @mul_v8i16(<8 x i16> %x, <8 x i16> %y) { define <8 x i16> @mul_v8i16(<8 x i16> %x, <8 x i16> %y) {
%a = mul <8 x i16> %x, %y %a = mul <8 x i16> %x, %y
ret <8 x i16> %a ret <8 x i16> %a
} }
; CHECK-LABEL: neg_v8i16:
; NO-SIMD128-NOT: i16x8
; SIMD128-NEXT: .param v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i16x8.neg $push0=, $0{{$}}
; SIMD128-NEXT: return $pop0{{$}}
define <8 x i16> @neg_v8i16(<8 x i16> %x) {
%a = sub <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>,
%x
ret <8 x i16> %a
}
; CHECK-LABEL: and_v8i16: ; CHECK-LABEL: and_v8i16:
; NO-SIMD128-NOT: v128 ; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .param v128, v128{{$}} ; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}} ; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: v128.and $push0=, $0, $1{{$}} ; SIMD128-NEXT: v128.and $push0=, $0, $1{{$}}
; SIMD128-NEXT: return $pop0{{$}} ; SIMD128-NEXT: return $pop0{{$}}
define <8 x i16> @and_v8i16(<8 x i16> %x, <8 x i16> %y) { define <8 x i16> @and_v8i16(<8 x i16> %x, <8 x i16> %y) {
%a = and <8 x i16> %x, %y %a = and <8 x i16> %x, %y
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; SIMD128-NEXT: .result v128{{$}} ; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i32x4.mul $push0=, $0, $1{{$}} ; SIMD128-NEXT: i32x4.mul $push0=, $0, $1{{$}}
; SIMD128-NEXT: return $pop0{{$}} ; SIMD128-NEXT: return $pop0{{$}}
define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) {
%a = mul <4 x i32> %x, %y %a = mul <4 x i32> %x, %y
ret <4 x i32> %a ret <4 x i32> %a
} }
; CHECK-LABEL: neg_v4i32:
; NO-SIMD128-NOT: i32x4
; SIMD128-NEXT: .param v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i32x4.neg $push0=, $0{{$}}
; SIMD128-NEXT: return $pop0{{$}}
define <4 x i32> @neg_v4i32(<4 x i32> %x) {
%a = sub <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %x
ret <4 x i32> %a
}
; CHECK-LABEL: and_v4i32: ; CHECK-LABEL: and_v4i32:
; NO-SIMD128-NOT: v128 ; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .param v128, v128{{$}} ; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}} ; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: v128.and $push0=, $0, $1{{$}} ; SIMD128-NEXT: v128.and $push0=, $0, $1{{$}}
; SIMD128-NEXT: return $pop0{{$}} ; SIMD128-NEXT: return $pop0{{$}}
define <4 x i32> @and_v4i32(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @and_v4i32(<4 x i32> %x, <4 x i32> %y) {
%a = and <4 x i32> %x, %y %a = and <4 x i32> %x, %y
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; SIMD128-NOT: i64x2.mul ; SIMD128-NOT: i64x2.mul
; SIMD128: i64x2.extract_lane ; SIMD128: i64x2.extract_lane
; SIMD128: i64.mul ; SIMD128: i64.mul
define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
%a = mul <2 x i64> %x, %y %a = mul <2 x i64> %x, %y
ret <2 x i64> %a ret <2 x i64> %a
} }
; CHECK-LABEL: neg_v2i64:
; NO-SIMD128-NOT: i64x2
; SIMD128-NEXT: .param v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i64x2.neg $push0=, $0{{$}}
; SIMD128-NEXT: return $pop0{{$}}
define <2 x i64> @neg_v2i64(<2 x i64> %x) {
%a = sub <2 x i64> <i64 0, i64 0>, %x
ret <2 x i64> %a
}
; CHECK-LABEL: and_v2i64: ; CHECK-LABEL: and_v2i64:
; NO-SIMD128-NOT: v128 ; NO-SIMD128-NOT: v128
; SIMD128-VM-NOT: v128 ; SIMD128-VM-NOT: v128
; SIMD128-NEXT: .param v128, v128{{$}} ; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}} ; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: v128.and $push0=, $0, $1{{$}} ; SIMD128-NEXT: v128.and $push0=, $0, $1{{$}}
; SIMD128-NEXT: return $pop0{{$}} ; SIMD128-NEXT: return $pop0{{$}}
define <2 x i64> @and_v2i64(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @and_v2i64(<2 x i64> %x, <2 x i64> %y) {
Show All 35 Lines
define <2 x i64> @not_v2i64(<2 x i64> %x) { define <2 x i64> @not_v2i64(<2 x i64> %x) {
%a = xor <2 x i64> %x, <i64 -1, i64 -1> %a = xor <2 x i64> %x, <i64 -1, i64 -1>
ret <2 x i64> %a ret <2 x i64> %a
} }
; ============================================================================== ; ==============================================================================
; 4 x float ; 4 x float
; ============================================================================== ; ==============================================================================
; CHECK-LABEL: neg_v4f32:
; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: f32x4.neg $push0=, $0{{$}}
; SIMD128-NEXT: return $pop0{{$}}
define <4 x float> @neg_v4f32(<4 x float> %x) {
%a = fsub <4 x float> <float 0., float 0., float 0., float 0.>, %x
ret <4 x float> %a
}
; CHECK-LABEL: add_v4f32: ; CHECK-LABEL: add_v4f32:
; NO-SIMD128-NOT: f32x4 ; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .param v128, v128{{$}} ; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}} ; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: f32x4.add $push0=, $0, $1{{$}} ; SIMD128-NEXT: f32x4.add $push0=, $0, $1{{$}}
; SIMD128-NEXT: return $pop0{{$}} ; SIMD128-NEXT: return $pop0{{$}}
define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) { define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) {
%a = fadd <4 x float> %x, %y %a = fadd <4 x float> %x, %y
Show All 31 Lines
define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) { define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) {
%a = fmul <4 x float> %x, %y %a = fmul <4 x float> %x, %y
ret <4 x float> %a ret <4 x float> %a
} }
; ============================================================================== ; ==============================================================================
; 2 x double ; 2 x double
; ============================================================================== ; ==============================================================================
; CHECK-LABEL: neg_v2f64:
; NO-SIMD128-NOT: f64x2
; SIMD128-NEXT: .param v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: f64x2.neg $push0=, $0{{$}}
; SIMD128-NEXT: return $pop0{{$}}
define <2 x double> @neg_v2f64(<2 x double> %x) {
%a = fsub <2 x double> <double 0., double 0.>, %x
ret <2 x double> %a
}
; CHECK-LABEL: add_v2f64: ; CHECK-LABEL: add_v2f64:
; NO-SIMD128-NOT: f64x2 ; NO-SIMD128-NOT: f64x2
; SIMD128-VM-NOT: f62x2 ; SIMD128-VM-NOT: f62x2
; SIMD128-NEXT: .param v128, v128{{$}} ; SIMD128-NEXT: .param v128, v128{{$}}
; SIMD128-NEXT: .result v128{{$}} ; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: f64x2.add $push0=, $0, $1{{$}} ; SIMD128-NEXT: f64x2.add $push0=, $0, $1{{$}}
; SIMD128-NEXT: return $pop0{{$}} ; SIMD128-NEXT: return $pop0{{$}}
define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) { define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) {
Show All 39 Lines

llvm/trunk/test/MC/WebAssembly/simd-encodings.s

Show First 20 Lines • Show All 127 Lines • ▼ Show 20 Lines# RUN: llvm-mc -show-encoding -triple=wasm32-unkown-unknown -mattr=+sign-ext,+simd128 < %s | FileCheck %s
i8x16.mul i8x16.mul
# CHECK: i16x8.mul # encoding: [0xfd,0x21] # CHECK: i16x8.mul # encoding: [0xfd,0x21]
i16x8.mul i16x8.mul
# CHECK: i32x4.mul # encoding: [0xfd,0x22] # CHECK: i32x4.mul # encoding: [0xfd,0x22]
i32x4.mul i32x4.mul
# CHECK: i8x16.neg # encoding: [0xfd,0x23]
i8x16.neg
# CHECK: i16x8.neg # encoding: [0xfd,0x24]
i16x8.neg
# CHECK: i32x4.neg # encoding: [0xfd,0x25]
i32x4.neg
# CHECK: i64x2.neg # encoding: [0xfd,0x26]
i64x2.neg
# CHECK: v128.and # encoding: [0xfd,0x3b] # CHECK: v128.and # encoding: [0xfd,0x3b]
v128.and v128.and
# CHECK: v128.or # encoding: [0xfd,0x3c] # CHECK: v128.or # encoding: [0xfd,0x3c]
v128.or v128.or
# CHECK: v128.xor # encoding: [0xfd,0x3d] # CHECK: v128.xor # encoding: [0xfd,0x3d]
v128.xor v128.xor
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines# RUN: llvm-mc -show-encoding -triple=wasm32-unkown-unknown -mattr=+sign-ext,+simd128 < %s | FileCheck %s
i32x4.ge_u i32x4.ge_u
# CHECK: f32x4.ge # encoding: [0xfd,0x70] # CHECK: f32x4.ge # encoding: [0xfd,0x70]
f32x4.ge f32x4.ge
# CHECK: f64x2.ge # encoding: [0xfd,0x71] # CHECK: f64x2.ge # encoding: [0xfd,0x71]
f64x2.ge f64x2.ge
# CHECK: f32x4.neg # encoding: [0xfd,0x72]
f32x4.neg
# CHECK: f64x2.neg # encoding: [0xfd,0x73]
f64x2.neg
# CHECK: f32x4.add # encoding: [0xfd,0x7a] # CHECK: f32x4.add # encoding: [0xfd,0x7a]
f32x4.add f32x4.add
# CHECK: f64x2.add # encoding: [0xfd,0x7b] # CHECK: f64x2.add # encoding: [0xfd,0x7b]
f64x2.add f64x2.add
# CHECK: f32x4.sub # encoding: [0xfd,0x7c] # CHECK: f32x4.sub # encoding: [0xfd,0x7c]
f32x4.sub f32x4.sub
Show All 17 Lines