[WebAssembly] SIMD neg

[tlively]

Summary

Depends on D52007.

[tlively]

• Add encoding tests (and fix encoding)

[aheejin]

I think this is dependent on D52007. Fixed it. By the way, the diff looks like it contains D52007's diff too. Could you fix it? You can do relative diff by
arc diff --update D52009 DIVISION_TO_COMPARE

[tlively]

• Diff from correct revision

[tlively]

Fixed! Sorry about that. It's much more sane now.

[aheejin]

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

157

Can't this be 0.0 or something like the integer case?

[tlively]

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

157

No, unfortunately tablegen does not support floating point literals. This is the standard solution used in multiple backends.

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 1)>;
 }
 multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop> {
   defm "" : SIMDBinary<v16i8, "v128", node, name, simdop>;
   defm "" : SIMDBinary<v8i16, "v128", node, name, simdop>;
   defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>;
   defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>;
 }
+multiclass SIMDNeg<ValueType vec_t, string vec, PatFrag splat_pat,
+                   ValueType lane_t, SDNode node, dag lane, bits<32> simdop> {
+  defm NEG_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec),
+                           (outs), (ins),
+                           [(set
+                             (vec_t V128:$dst),
+                             (vec_t (node
+                               (vec_t (splat_pat lane)),
+                               (vec_t V128:$vec)
+                             ))
+                           )],
+                           vec#".neg\t$dst, $vec", vec#".neg", simdop>;
+}
+multiclass SIMDNegInt<ValueType vec_t, string vec, PatFrag splat_pat,
+                      ValueType lane_t, bits<32> simdop> {
+  defm "" : SIMDNeg<vec_t, vec, splat_pat, lane_t, sub, (lane_t 0), simdop>;
+}
+def fpimm0 : FPImmLeaf<fAny, [{ return Imm.isExactlyValue(+0.0); }]>;
+multiclass SIMDNegFP<ValueType vec_t, string vec, PatFrag splat_pat,
+                     ValueType lane_t, bits<32> simdop> {
+  defm "" : SIMDNeg<vec_t, vec, splat_pat, lane_t, fsub, (lane_t fpimm0),
+                    simdop>;
+}
 multiclass SIMDNot<ValueType vec_t, PatFrag splat_pat, ValueType lane_t> {
   defm NOT_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec),
                            (outs), (ins),
                            [(set
                              (vec_t V128:$dst),
                              (vec_t (xor
                                (vec_t V128:$vec),
                                (vec_t (splat_pat (lane_t -1)))

 defm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 32>;
 defm MUL : SIMDBinaryFP<fmul, "mul", 128>;
 } // isCommutable = 1
 
 defm SUB : SIMDBinaryInt<sub, "sub", 28>;
 defm SUB : SIMDBinaryFP<fsub, "sub", 124>;
 defm DIV : SIMDBinaryFP<fdiv, "div", 126>;
 
+defm "" : SIMDNegInt<v16i8, "i8x16", splat16, i32, 35>;
+defm "" : SIMDNegInt<v8i16, "i16x8", splat8, i32, 36>;
+defm "" : SIMDNegInt<v4i32, "i32x4", splat4, i32, 37>;
+defm "" : SIMDNegInt<v2i64, "i64x2", splat2, i64, 38>;
+defm "" : SIMDNegFP<v4f32, "f32x4", splat4, f32, 37>;
+defm "" : SIMDNegFP<v2f64, "f64x2", splat2, f64, 38>;
+
 let isCommutable = 1 in {
 defm AND : SIMDBitwise<and, "and", 59>;
 defm OR : SIMDBitwise<or, "or", 60>;
 defm XOR : SIMDBitwise<xor, "xor", 61>;
 } // isCommutable = 1
 
 defm "" : SIMDNot<v16i8, splat16, i32>;
 defm "" : SIMDNot<v8i16, splat8, i32>;

test/CodeGen/WebAssembly/simd-arith.ll

 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: i8x16.mul $push0=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop0{{$}}
 define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = mul <16 x i8> %x, %y
   ret <16 x i8> %a
 }
 
+; CHECK-LABEL: neg_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i8x16.neg $push0=, $0{{$}}
+; SIMD128-NEXT: return $pop0{{$}}
+define <16 x i8> @neg_v16i8(<16 x i8> %x) {
+  %a = sub <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0,
+                      i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>,
+                     %x
+  ret <16 x i8> %a
+}
+
 ; CHECK-LABEL: and_v16i8:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .param v128, v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: v128.and $push0=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop0{{$}}
 define <16 x i8> @and_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = and <16 x i8> %x, %y

 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: i16x8.mul $push0=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop0{{$}}
 define <8 x i16> @mul_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = mul <8 x i16> %x, %y
   ret <8 x i16> %a
 }
 
+; CHECK-LABEL: neg_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i16x8.neg $push0=, $0{{$}}
+; SIMD128-NEXT: return $pop0{{$}}
+define <8 x i16> @neg_v8i16(<8 x i16> %x) {
+  %a = sub <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>,
+                     %x
+  ret <8 x i16> %a
+}
+
 ; CHECK-LABEL: and_v8i16:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .param v128, v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: v128.and $push0=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop0{{$}}
 define <8 x i16> @and_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = and <8 x i16> %x, %y

 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: i32x4.mul $push0=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop0{{$}}
 define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %a = mul <4 x i32> %x, %y
   ret <4 x i32> %a
 }
 
+; CHECK-LABEL: neg_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32x4.neg $push0=, $0{{$}}
+; SIMD128-NEXT: return $pop0{{$}}
+define <4 x i32> @neg_v4i32(<4 x i32> %x) {
+  %a = sub <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %x
+  ret <4 x i32> %a
+}
+
 ; CHECK-LABEL: and_v4i32:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-NEXT: .param v128, v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: v128.and $push0=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop0{{$}}
 define <4 x i32> @and_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %a = and <4 x i32> %x, %y

 ; SIMD128-NOT: i64x2.mul
 ; SIMD128: i64x2.extract_lane
 ; SIMD128: i64.mul
 define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = mul <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
+; CHECK-LABEL: neg_v2i64:
+; NO-SIMD128-NOT: i64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i64x2.neg $push0=, $0{{$}}
+; SIMD128-NEXT: return $pop0{{$}}
+define <2 x i64> @neg_v2i64(<2 x i64> %x) {
+  %a = sub <2 x i64> <i64 0, i64 0>, %x
+  ret <2 x i64> %a
+}
+
 ; CHECK-LABEL: and_v2i64:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .param v128, v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: v128.and $push0=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop0{{$}}
 define <2 x i64> @and_v2i64(<2 x i64> %x, <2 x i64> %y) {

 define <2 x i64> @not_v2i64(<2 x i64> %x) {
   %a = xor <2 x i64> %x, <i64 -1, i64 -1>
   ret <2 x i64> %a
 }
 
 ; ==============================================================================
 ; 4 x float
 ; ==============================================================================
+; CHECK-LABEL: neg_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.neg $push0=, $0{{$}}
+; SIMD128-NEXT: return $pop0{{$}}
+define <4 x float> @neg_v4f32(<4 x float> %x) {
+  %a = fsub <4 x float> <float 0., float 0., float 0., float 0.>, %x
+  ret <4 x float> %a
+}
+
 ; CHECK-LABEL: add_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128-NEXT: .param v128, v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f32x4.add $push0=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop0{{$}}
 define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fadd <4 x float> %x, %y

 define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fmul <4 x float> %x, %y
   ret <4 x float> %a
 }
 
 ; ==============================================================================
 ; 2 x double
 ; ==============================================================================
+; CHECK-LABEL: neg_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.neg $push0=, $0{{$}}
+; SIMD128-NEXT: return $pop0{{$}}
+define <2 x double> @neg_v2f64(<2 x double> %x) {
+  %a = fsub <2 x double> <double 0., double 0.>, %x
+  ret <2 x double> %a
+}
+
 ; CHECK-LABEL: add_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f62x2
 ; SIMD128-NEXT: .param v128, v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f64x2.add $push0=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop0{{$}}
 define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) {