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AMDGPU: Generate VALU ThreeOp Integer instructions
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Authored by nhaehnle on Sep 12 2018, 9:54 AM.

Details

Summary

Original patch by: Fabian Wahlster <razor@singul4rity.com>

Change-Id: I148f692a88432541fad468963f58da9ddf79fac5

Diff Detail

Repository
rL LLVM

Event Timeline

nhaehnle created this revision.Sep 12 2018, 9:54 AM
rampitec added inline comments.Sep 12 2018, 12:13 PM
lib/Target/AMDGPU/VOP3Instructions.td
481 ↗(On Diff #165109)

This deserves an explanation I guess.

524 ↗(On Diff #165109)

Remove commented code.

rampitec added inline comments.Sep 12 2018, 2:34 PM
lib/Target/AMDGPU/VOP3Instructions.td
481 ↗(On Diff #165109)

Also it seems too restrictive. It prohibits the selection even if scalar value is an inlinable literal.

Needs some edge case tests where the values are uniform but still need to be in a VGPR

test/CodeGen/AMDGPU/add3.ll
1–2 ↗(On Diff #165109)

Needs a run line with a target that doesn't have these instructions to make sure they aren't emitted

nhaehnle updated this revision to Diff 165218.Sep 13 2018, 2:02 AM
nhaehnle marked 2 inline comments as done.
  • Cleaned up the pattern condition to take inline constants into account
  • Add tests for inline constants and uniform values ending up in VGPRs
  • update_llc-ify the tests
nhaehnle added inline comments.Sep 13 2018, 2:08 AM
lib/Target/AMDGPU/VOP3Instructions.td
524 ↗(On Diff #165109)

Ah, I thought the idea was to comment what this matches. I'm making this clearer.

This revision is now accepted and ready to land.Sep 13 2018, 8:58 AM
nhaehnle updated this revision to Diff 171895.Oct 31 2018, 5:16 AM

Add missing V_XAD_U32 pattern.

This revision was automatically updated to reflect the committed changes.