[TableGen] Add Logical operands info emission

[m4yers]

Summary

This patch is part of a bigger one D50314. It adds a possibility to emit a
logical operands info.

This feature can be used to simplify CISC machine code emission as it done in
M68K D50314 patch. You can check out M680x0MCCodeEmitter.cpp to see how it is
used. In short, it gives a "logical view" onto machine instruction operands
list, as it was defined in the tablegen files.

The main changes are in MCInstrDesc.h and InstrInfoEmitter.cpp, the rest of the
diff is just renaming for consistency sake.

[lebedev.ri]

The main changes are in MCInstrDesc.h and InstrInfoEmitter.cpp,
the rest of the diff is just renaming for consistency sake.

Which results in a *lot* of noise.
It would be best to further split this into the actual changes, and a follow-up "just renaming for consistency sake."

[m4yers]

In D50856#1202925, @lebedev.ri wrote:

The main changes are in MCInstrDesc.h and InstrInfoEmitter.cpp,
the rest of the diff is just renaming for consistency sake.

Which results in a *lot* of noise.
It would be best to further split this into the actual changes, and a follow-up "just renaming for consistency sake."

Will do, thanks!

[m4yers]

Remove noise changes

When(if?) this diff lands another will follow, renaming:

• NumOperands -> NumMCOperands
• OpInfo -> MCOpInfo

for consistency

[RKSimon]

@m4yers Abandon this now that the m68k target has landed?

include/llvm/MC/MCInstrDesc.h

 #ifndef LLVM_MC_MCINSTRDESC_H
 #define LLVM_MC_MCINSTRDESC_H
 
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/DataTypes.h"
 #include <string>
 
 namespace llvm {
-  class MCInst;
-  class MCSubtargetInfo;
-  class FeatureBitset;
 
 //===----------------------------------------------------------------------===//
 // Machine Operand Flags and Description
 //===----------------------------------------------------------------------===//
 
 namespace MCOI {
 // Operand constraints
 enum OperandConstraint {
enum OperandType {
   OPERAND_GENERIC_3 = 9,
   OPERAND_GENERIC_4 = 10,
   OPERAND_GENERIC_5 = 11,
   OPERAND_LAST_GENERIC = 11,
 
   OPERAND_FIRST_TARGET = 12,
 };
 
-}
+} // namespace MCOI
 
 /// This holds information about one operand of a machine instruction,
 /// indicating the register class for register operands, etc.
 class MCOperandInfo {
 public:
   /// This specifies the register class enumeration of the operand
   /// if the operand is a register.  If isLookupPtrRegClass is set, then this is
   /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
enum Flag {
   ExtraDefRegAllocReq,
   RegSequence,
   ExtractSubreg,
   InsertSubreg,
   Convergent,
   Add,
   Trap
 };
-}
+} // namespace MCID
+
+/// \brief Defines an operand group.
+///
+/// Many machine operands are aggregates of multiple target operands (e.g.
+/// register, immediate) and during codegen it is not always clear how many
+/// those operands to read. This type provides this information.
+class MIOperandInfo {
+public:
+  int16_t MINo;
+  int16_t Type;
+  int16_t OpsNum;
+
+  bool isTargetType() { return Type >= MCOI::OPERAND_FIRST_TARGET; };
+};
 
 /// Describe properties that are true of each instruction in the target
 /// description file.  This captures information about side effects, register
 /// use and many other things.  There is one instance of this struct for each
 /// target instruction class, and the MachineInstr class points to this struct
 /// directly to describe itself.
 class MCInstrDesc {
 public:
   unsigned short Opcode;         // The opcode number
-  unsigned short NumOperands;    // Num of args (may be more if variable_ops)
+  unsigned short NumMIOperands;  // Num of logical operands
+  unsigned short NumMCOperands;  // Num of args (may be more if variable_ops)
   unsigned char NumDefs;         // Num of args that are definitions
   unsigned char Size;            // Number of bytes in encoding.
   unsigned short SchedClass;     // enum identifying instr sched class
   uint64_t Flags;                // Flags identifying machine instr class
   uint64_t TSFlags;              // Target Specific Flag values
   const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
   const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
-  const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
+  const MIOperandInfo *MIOpInfo; // 'NumMIOperands' entries about operands
+  const MCOperandInfo *MCOpInfo; // 'NumMCOperands' entries about operands
   // Subtarget feature that this is deprecated on, if any
   // -1 implies this is not deprecated by any single feature. It may still be
   // deprecated due to a "complex" reason, below.
   int64_t DeprecatedFeature;
 
   // A complex method to determine if a certain instruction is deprecated or
   // not, and return the reason for deprecation.
   bool (*ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &,
                                  std::string &);
 
   /// Returns the value of the specific constraint if
   /// it is set. Returns -1 if it is not set.
   int getOperandConstraint(unsigned OpNum,
                            MCOI::OperandConstraint Constraint) const {
-    if (OpNum < NumOperands &&
-        (OpInfo[OpNum].Constraints & (1 << Constraint))) {
+    if (OpNum < NumMCOperands &&
+        (MCOpInfo[OpNum].Constraints & (1 << Constraint))) {
       unsigned Pos = 16 + Constraint * 4;
-      return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
+      return (int)(MCOpInfo[OpNum].Constraints >> Pos) & 0xf;
     }
     return -1;
   }
 
   /// Returns true if a certain instruction is deprecated and if so
   /// returns the reason in \p Info.
   bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
                          std::string &Info) const;
 
   /// Return the opcode number for this descriptor.
   unsigned getOpcode() const { return Opcode; }
 
   /// Return the number of declared MachineOperands for this
   /// MachineInstruction.  Note that variadic (isVariadic() returns true)
   /// instructions may have additional operands at the end of the list, and note
   /// that the machine instruction may include implicit register def/uses as
   /// well.
-  unsigned getNumOperands() const { return NumOperands; }
+  unsigned getNumOperands() const { return NumMCOperands; }
 
   using const_opInfo_iterator = const MCOperandInfo *;
 
-  const_opInfo_iterator opInfo_begin() const { return OpInfo; }
-  const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; }
+  const_opInfo_iterator opInfo_begin() const { return MCOpInfo; }
+  const_opInfo_iterator opInfo_end() const { return MCOpInfo + NumMCOperands; }
 
   iterator_range<const_opInfo_iterator> operands() const {
     return make_range(opInfo_begin(), opInfo_end());
   }
 
   /// Return the number of MachineOperands that are register
   /// definitions.  Register definitions always occur at the start of the
   /// machine operand list.  This is the number of "outs" in the .td file,
public:
   /// Returns true if this is a conditional, unconditional, or
   /// indirect branch.  Predicates below can be used to discriminate between
   /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
   /// get more information.
   bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
 
   /// Return true if this is an indirect branch, such as a
   /// branch through a register.
-  bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
+  bool isIndirectBranch() const {
+    return Flags & (1ULL << MCID::IndirectBranch);
+  }
 
   /// Return true if this is a branch which may fall
   /// through to the next instruction or may transfer control flow to some other
   /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
   /// information about this branch.
   bool isConditionalBranch() const {
     return isBranch() & !isBarrier() & !isIndirectBranch();
   }
public:
   /// E.g., on ARM,
   /// dX = VSETLNi32 dY, rZ, Imm
   /// is equivalent to a INSERT_SUBREG:
   /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
   ///
   /// Note that for the optimizers to be able to take advantage of
   /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
   /// override accordingly.
-  bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
-
+  bool isInsertSubregLike() const {
+    return Flags & (1ULL << MCID::InsertSubreg);
+  }
 
   /// Return true if this instruction is convergent.
   ///
   /// Convergent instructions may not be made control-dependent on any
   /// additional values.
   bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
 
   //===--------------------------------------------------------------------===//
public:
   bool usesCustomInsertionHook() const {
     return Flags & (1ULL << MCID::UsesCustomInserter);
   }
 
   /// Return true if this instruction requires *adjustment* after
   /// instruction selection by calling a target hook. For example, this can be
   /// used to fill in ARM 's' optional operand depending on whether the
   /// conditional flag register is used.
-  bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
+  bool hasPostISelHook() const {
+    return Flags & (1ULL << MCID::HasPostISelHook);
+  }
 
   /// Returns true if this instruction is a candidate for remat. This
   /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
   ///
   /// If this flag is set, the isReallyTriviallyReMaterializable()
   /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
   /// the instruction is really rematable.
   bool isRematerializable() const {
public:
   unsigned getSize() const { return Size; }
 
   /// Find the index of the first operand in the
   /// operand list that is used to represent the predicate. It returns -1 if
   /// none is found.
   int findFirstPredOperandIdx() const {
     if (isPredicable()) {
       for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
-        if (OpInfo[i].isPredicate())
+        if (MCOpInfo[i].isPredicate())
           return i;
     }
     return -1;
   }
 
   /// Return true if this instruction defines the specified physical
   /// register, either explicitly or implicitly.
   bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
                        const MCRegisterInfo &RI) const;
 };
 
 } // end namespace llvm
 
 #endif

lib/CodeGen/GlobalISel/LegalizerInfo.cpp

LegalizerInfo::getAction(const LegalityQuery &Query) const {
   return {Legal, 0, LLT{}};
 }
 
 LegalizeActionStep
 LegalizerInfo::getAction(const MachineInstr &MI,
                          const MachineRegisterInfo &MRI) const {
   SmallVector<LLT, 2> Types;
   SmallBitVector SeenTypes(8);
-  const MCOperandInfo *OpInfo = MI.getDesc().OpInfo;
+  const MCOperandInfo *OpInfo = MI.getDesc().MCOpInfo;
   // FIXME: probably we'll need to cache the results here somehow?
   for (unsigned i = 0; i < MI.getDesc().getNumOperands(); ++i) {
     if (!OpInfo[i].isGenericType())
       continue;
 
     // We must only record actions once for each TypeIdx; otherwise we'd
     // try to legalize operands multiple times down the line.
     unsigned TypeIdx = OpInfo[i].getGenericTypeIndex();

lib/CodeGen/MachineInstr.cpp

 int MachineInstr::findFirstPredOperandIdx() const {
   // Don't call MCID.findFirstPredOperandIdx() because this variant
   // is sometimes called on an instruction that's not yet complete, and
   // so the number of operands is less than the MCID indicates. In
   // particular, the PTX target does this.
   const MCInstrDesc &MCID = getDesc();
   if (MCID.isPredicable()) {
     for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
-      if (MCID.OpInfo[i].isPredicate())
+      if (MCID.MCOpInfo[i].isPredicate())
         return i;
   }
 
   return -1;
 }
 
 // MachineOperand::TiedTo is 4 bits wide.
 const unsigned TiedMax = 15;
LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
                                  const MachineRegisterInfo &MRI) const {
   const MachineOperand &Op = getOperand(OpIdx);
   if (!Op.isReg())
     return LLT{};
 
   if (isVariadic() || OpIdx >= getNumExplicitOperands())
     return MRI.getType(Op.getReg());
 
-  auto &OpInfo = getDesc().OpInfo[OpIdx];
+  auto &OpInfo = getDesc().MCOpInfo[OpIdx];
   if (!OpInfo.isGenericType())
     return MRI.getType(Op.getReg());
 
   if (PrintedTypes[OpInfo.getGenericTypeIndex()])
     return LLT{};
 
   LLT TypeToPrint = MRI.getType(Op.getReg());
   // Don't mark the type index printed if it wasn't actually printed: maybe

lib/CodeGen/MachineVerifier.cpp

void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
 
   if (isPreISelGenericOpcode(MCID.getOpcode())) {
     if (isFunctionSelected)
       report("Unexpected generic instruction in a Selected function", MI);
 
     // Check types.
     SmallVector<LLT, 4> Types;
     for (unsigned I = 0; I < MCID.getNumOperands(); ++I) {
-      if (!MCID.OpInfo[I].isGenericType())
+      if (!MCID.MCOpInfo[I].isGenericType())
         continue;
       // Generic instructions specify type equality constraints between some of
       // their operands. Make sure these are consistent.
-      size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
+      size_t TypeIdx = MCID.MCOpInfo[I].getGenericTypeIndex();
       Types.resize(std::max(TypeIdx + 1, Types.size()));
 
       const MachineOperand *MO = &MI->getOperand(I);
       LLT OpTy = MRI->getType(MO->getReg());
       // Don't report a type mismatch if there is no actual mismatch, only a
       // type missing, to reduce noise:
       if (OpTy.isValid()) {
         // Only the first valid type for a type index will be printed: don't
MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
   const MachineInstr *MI = MO->getParent();
   const MCInstrDesc &MCID = MI->getDesc();
   unsigned NumDefs = MCID.getNumDefs();
   if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
     NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
 
   // The first MCID.NumDefs operands must be explicit register defines
   if (MONum < NumDefs) {
-    const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
+    const MCOperandInfo &MCOI = MCID.MCOpInfo[MONum];
     if (!MO->isReg())
       report("Explicit definition must be a register", MO, MONum);
     else if (!MO->isDef() && !MCOI.isOptionalDef())
       report("Explicit definition marked as use", MO, MONum);
     else if (MO->isImplicit())
       report("Explicit definition marked as implicit", MO, MONum);
   } else if (MONum < MCID.getNumOperands()) {
-    const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
+    const MCOperandInfo &MCOI = MCID.MCOpInfo[MONum];
     // Don't check if it's the last operand in a variadic instruction. See,
     // e.g., LDM_RET in the arm back end.
     if (MO->isReg() &&
         !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
       if (MO->isDef() && !MCOI.isOptionalDef())
         report("Explicit operand marked as def", MO, MONum);
       if (MO->isImplicit())
         report("Explicit operand marked as implicit", MO, MONum);

lib/CodeGen/SelectionDAG/InstrEmitter.cpp

if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
       const TargetRegisterClass *VTRC =
         TLI->getRegClassFor(Node->getSimpleValueType(i));
       if (RC)
         VTRC = TRI->getCommonSubClass(RC, VTRC);
       if (VTRC)
         RC = VTRC;
     }
 
-    if (II.OpInfo[i].isOptionalDef()) {
+    if (II.MCOpInfo[i].isOptionalDef()) {
       // Optional def must be a physical register.
       VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
       assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
       MIB.addReg(VRBase, RegState::Define);
     }
 
     if (!VRBase && !IsClone && !IsCloned)
       for (SDNode *User : Node->uses()) {
InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
   assert(Op.getValueType() != MVT::Other &&
          Op.getValueType() != MVT::Glue &&
          "Chain and glue operands should occur at end of operand list!");
   // Get/emit the operand.
   unsigned VReg = getVR(Op, VRBaseMap);
 
   const MCInstrDesc &MCID = MIB->getDesc();
   bool isOptDef = IIOpNum < MCID.getNumOperands() &&
-    MCID.OpInfo[IIOpNum].isOptionalDef();
+    MCID.MCOpInfo[IIOpNum].isOptionalDef();
 
   // If the instruction requires a register in a different class, create
   // a new virtual register and copy the value into it, but first attempt to
   // shrink VReg's register class within reason.  For example, if VReg == GR32
   // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
   if (II) {
     const TargetRegisterClass *OpRC = nullptr;
     if (IIOpNum < II->getNumOperands())

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) {
 
     const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
     if (MCID.hasOptionalDef()) {
       // Most ARM instructions have an OptionalDef for CPSR, to model the S-bit.
       // This operand can be either a def of CPSR, if the S bit is set; or a use
       // of %noreg.  When the OptionalDef is set to a valid register, we need to
       // handle it in the same way as an ImplicitDef.
       for (unsigned i = 0; i < MCID.getNumDefs(); ++i)
-        if (MCID.OpInfo[i].isOptionalDef()) {
+        if (MCID.MCOpInfo[i].isOptionalDef()) {
           const SDValue &OptionalDef = Node->getOperand(i - Node->getNumValues());
           unsigned Reg = cast<RegisterSDNode>(OptionalDef)->getReg();
           CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
         }
     }
     if (!MCID.ImplicitDefs)
       continue;
     for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg)

lib/CodeGen/TargetInstrInfo.cpp

 
 const TargetRegisterClass*
 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
                              const TargetRegisterInfo *TRI,
                              const MachineFunction &MF) const {
   if (OpNum >= MCID.getNumOperands())
     return nullptr;
 
-  short RegClass = MCID.OpInfo[OpNum].RegClass;
-  if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
+  short RegClass = MCID.MCOpInfo[OpNum].RegClass;
+  if (MCID.MCOpInfo[OpNum].isLookupPtrRegClass())
     return TRI->getPointerRegClass(MF, RegClass);
 
   // Instructions like INSERT_SUBREG do not have fixed register classes.
   if (RegClass < 0)
     return nullptr;
 
   // Otherwise just look it up normally.
   return TRI->getRegClass(RegClass);
bool TargetInstrInfo::PredicateInstruction(
   assert(!MI.isBundle() &&
          "TargetInstrInfo::PredicateInstruction() can't handle bundles");
 
   const MCInstrDesc &MCID = MI.getDesc();
   if (!MI.isPredicable())
     return false;
 
   for (unsigned j = 0, i = 0, e = MI.getNumOperands(); i != e; ++i) {
-    if (MCID.OpInfo[i].isPredicate()) {
+    if (MCID.MCOpInfo[i].isPredicate()) {
       MachineOperand &MO = MI.getOperand(i);
       if (MO.isReg()) {
         MO.setReg(Pred[j].getReg());
         MadeChange = true;
       } else if (MO.isImm()) {
         MO.setImm(Pred[j].getImm());
         MadeChange = true;
       } else if (MO.isMBB()) {

lib/CodeGen/TargetSchedule.cpp

if (DefIdx < SCDesc->NumWriteLatencyEntries) {
     if (Advance > 0 && (unsigned)Advance > Latency) // unsigned wrap
       return 0;
     return Latency - Advance;
   }
   // If DefIdx does not exist in the model (e.g. implicit defs), then return
   // unit latency (defaultDefLatency may be too conservative).
 #ifndef NDEBUG
   if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
-      && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
+      && !DefMI->getDesc().MCOpInfo[DefOperIdx].isOptionalDef()
       && SchedModel.isComplete()) {
     errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
            << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)";
     llvm_unreachable("incomplete machine model");
   }
 #endif
   // FIXME: Automatically giving all implicit defs defaultDefLatency is
   // undesirable. We should only do it for defs that are known to the MC

lib/MC/MCInstrAnalysis.cpp

 bool MCInstrAnalysis::isDependencyBreaking(const MCSubtargetInfo &STI,
                                            const MCInst &Inst) const {
   return false;
 }
 
 bool MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
                                      uint64_t Size, uint64_t &Target) const {
   if (Inst.getNumOperands() == 0 ||
-      Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
+      Info->get(Inst.getOpcode()).MCOpInfo[0].OperandType != MCOI::OPERAND_PCREL)
     return false;
 
   int64_t Imm = Inst.getOperand(0).getImm();
   Target = Addr+Size+Imm;
   return true;
 }

lib/MC/MCInstrDesc.cpp

bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI,
   if (PC == 0)
     return false;
   if (hasDefOfPhysReg(MI, PC, RI))
     return true;
   // A variadic instruction may define PC in the variable operand list.
   // There's currently no indication of which entries in a variable
   // list are defs and which are uses. While that's the case, this function
   // needs to assume they're defs in order to be conservatively correct.
-  for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
+  for (int i = NumMCOperands, e = MI.getNumOperands(); i != e; ++i) {
     if (MI.getOperand(i).isReg() &&
         RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
       return true;
   }
   return false;
 }
 
 bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,

lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C,
   MachineBasicBlock::iterator ChainBegin = G->begin();
   assert(ChainBegin != ChainEnd && "Chain should contain instructions");
   do {
     --I;
     Units.accumulate(*I);
   } while (I != ChainBegin);
 
   // Make sure we allocate in-order, to get the cheapest registers first.
-  unsigned RegClassID = ChainBegin->getDesc().OpInfo[0].RegClass;
+  unsigned RegClassID = ChainBegin->getDesc().MCOpInfo[0].RegClass;
   auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
   for (auto Reg : Ord) {
     if (!Units.available(Reg))
       continue;
     if (C == getColor(Reg))
       return Reg;
   }
 

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

public:
 
   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
                       uint64_t &Target) const override {
     // Search for a PC-relative argument.
     // This will handle instructions like bcc (where the first argument is the
     // condition code) and cbz (where it is a register).
     const auto &Desc = Info->get(Inst.getOpcode());
     for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) {
-      if (Desc.OpInfo[i].OperandType == MCOI::OPERAND_PCREL) {
+      if (Desc.MCOpInfo[i].OperandType == MCOI::OPERAND_PCREL) {
         int64_t Imm = Inst.getOperand(i).getImm() * 4;
         Target = Addr + Imm;
         return true;
       }
     }
     return false;
   }
 };

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
 
   switch (N->getMachineOpcode()) {
   default: {
     const MCInstrDesc &Desc =
         Subtarget->getInstrInfo()->get(N->getMachineOpcode());
     unsigned OpIdx = Desc.getNumDefs() + OpNo;
     if (OpIdx >= Desc.getNumOperands())
       return nullptr;
-    int RegClass = Desc.OpInfo[OpIdx].RegClass;
+    int RegClass = Desc.MCOpInfo[OpIdx].RegClass;
     if (RegClass == -1)
       return nullptr;
 
     return Subtarget->getRegisterInfo()->getRegClass(RegClass);
   }
   case AMDGPU::REG_SEQUENCE: {
     unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
     const TargetRegisterClass *SuperRC =

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const {
 
   if (ApplyModifiers) {
     assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum));
     const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum);
     Val = applyInputFPModifiers(Val, Size);
   }
 
   APInt Literal(64, Val);
-  uint8_t OpTy = InstDesc.OpInfo[OpNum].OperandType;
+  uint8_t OpTy = InstDesc.MCOpInfo[OpNum].OperandType;
 
   if (Imm.IsFPImm) { // We got fp literal token
     switch (OpTy) {
     case AMDGPU::OPERAND_REG_IMM_INT64:
     case AMDGPU::OPERAND_REG_IMM_FP64:
     case AMDGPU::OPERAND_REG_INLINE_C_INT64:
     case AMDGPU::OPERAND_REG_INLINE_C_FP64:
       if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),
bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,
   auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx);
 
   switch (OpSize) { // expected operand size
   case 8:
     return AMDGPU::isInlinableLiteral64(Val, hasInv2PiInlineImm());
   case 4:
     return AMDGPU::isInlinableLiteral32(Val, hasInv2PiInlineImm());
   case 2: {
-    const unsigned OperandType = Desc.OpInfo[OpIdx].OperandType;
+    const unsigned OperandType = Desc.MCOpInfo[OpIdx].OperandType;
     if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2INT16 ||
         OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2FP16) {
       return AMDGPU::isInlinableLiteralV216(Val, hasInv2PiInlineImm());
     } else {
       return AMDGPU::isInlinableLiteral16(Val, hasInv2PiInlineImm());
     }
   }
   default:
if ((OpSel & (1 << SrcNum)) != 0) {
     int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
     uint32_t ModVal = Inst.getOperand(ModIdx).getImm();
     Inst.getOperand(ModIdx).setImm(ModVal | SISrcMods::DST_OP_SEL);
   }
 }
 
 static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) {
       // 1. This operand is input modifiers
-  return Desc.OpInfo[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS
+  return Desc.MCOpInfo[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS
       // 2. This is not last operand
-      && Desc.NumOperands > (OpNum + 1)
+      && Desc.NumMCOperands > (OpNum + 1)
       // 3. Next operand is register class
-      && Desc.OpInfo[OpNum + 1].RegClass != -1
+      && Desc.MCOpInfo[OpNum + 1].RegClass != -1
       // 4. Next register is not tied to any other operand
       && Desc.getOperandConstraint(OpNum + 1, MCOI::OperandConstraint::TIED_TO) == -1;
 }
 
 void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)
 {
   OptionalImmIndexMap OptionalIdx;
   unsigned Opc = Inst.getOpcode();

lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

if (IsGather4) {
     else
       return MCDisassembler::Success;
   } else {
     NewOpcode = AMDGPU::getMaskedMIMGOp(MI.getOpcode(), DstSize);
     if (NewOpcode == -1)
       return MCDisassembler::Success;
   }
 
-  auto RCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
+  auto RCID = MCII->get(NewOpcode).MCOpInfo[VDataIdx].RegClass;
 
   // Get first subregister of VData
   unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
   unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
   Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
 
   // Widen the register to the correct number of enabled channels.
   auto NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,

lib/Target/AMDGPU/GCNHazardRecognizer.cpp

int GCNHazardRecognizer::createsVALUHazard(const MachineInstr &MI) {
 
   const SIInstrInfo *TII = ST.getInstrInfo();
   unsigned Opcode = MI.getOpcode();
   const MCInstrDesc &Desc = MI.getDesc();
 
   int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);
   int VDataRCID = -1;
   if (VDataIdx != -1)
-    VDataRCID = Desc.OpInfo[VDataIdx].RegClass;
+    VDataRCID = Desc.MCOpInfo[VDataIdx].RegClass;
 
   if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) {
     // There is no hazard if the instruction does not use vector regs
     // (like wbinvl1)
     if (VDataIdx == -1)
       return -1;
     // For MUBUF/MTBUF instructions this hazard only exists if the
     // instruction is not using a register in the soffset field.
     const MachineOperand *SOffset =
         TII->getNamedOperand(MI, AMDGPU::OpName::soffset);
     // If we have no soffset operand, then assume this field has been
     // hardcoded to zero.
     if (AMDGPU::getRegBitWidth(VDataRCID) > 64 &&
         (!SOffset || !SOffset->isReg()))
       return VDataIdx;
   }
 
   // MIMG instructions create a hazard if they don't use a 256-bit T# and
   // the store size is greater than 8 bytes and they have more than two bits
   // of their dmask set.
   // All our MIMG definitions use a 256-bit T#, so we can skip checking for them.
   if (TII->isMIMG(MI)) {
     int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc);
     assert(SRsrcIdx != -1 &&
-           AMDGPU::getRegBitWidth(Desc.OpInfo[SRsrcIdx].RegClass) == 256);
+           AMDGPU::getRegBitWidth(Desc.MCOpInfo[SRsrcIdx].RegClass) == 256);
     (void)SRsrcIdx;
   }
 
   if (TII->isFLAT(MI)) {
     int DataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);
-    if (AMDGPU::getRegBitWidth(Desc.OpInfo[DataIdx].RegClass) > 64)
+    if (AMDGPU::getRegBitWidth(Desc.MCOpInfo[DataIdx].RegClass) > 64)
       return DataIdx;
   }
 
   return -1;
 }
 
 int GCNHazardRecognizer::checkVALUHazardsHelper(const MachineOperand &Def,
             const MachineRegisterInfo &MRI) {

lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

if (OpNo >= MI->getNumOperands()) {
     return;
   }
 
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     printRegOperand(Op.getReg(), O, MRI);
   } else if (Op.isImm()) {
     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
-    switch (Desc.OpInfo[OpNo].OperandType) {
+    switch (Desc.MCOpInfo[OpNo].OperandType) {
     case AMDGPU::OPERAND_REG_IMM_INT32:
     case AMDGPU::OPERAND_REG_IMM_FP32:
     case AMDGPU::OPERAND_REG_INLINE_C_INT32:
     case AMDGPU::OPERAND_REG_INLINE_C_FP32:
     case MCOI::OPERAND_IMMEDIATE:
       printImmediate32(Op.getImm(), STI, O);
       break;
     case AMDGPU::OPERAND_REG_IMM_INT64:
default:
       llvm_unreachable("unexpected immediate operand type");
     }
   } else if (Op.isFPImm()) {
     // We special case 0.0 because otherwise it will be printed as an integer.
     if (Op.getFPImm() == 0.0)
       O << "0.0";
     else {
       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
-      int RCID = Desc.OpInfo[OpNo].RegClass;
+      int RCID = Desc.MCOpInfo[OpNo].RegClass;
       unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
       if (RCBits == 32)
         printImmediate32(FloatToBits(Op.getFPImm()), STI, O);
       else if (RCBits == 64)
         printImmediate64(DoubleToBits(Op.getFPImm()), STI, O);
       else
         llvm_unreachable("Invalid register class size");
     }

lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
   for (unsigned i = 0, e = Desc.getNumOperands(); i < e; ++i) {
 
     // Check if this operand should be encoded as [SV]Src
     if (!AMDGPU::isSISrcOperand(Desc, i))
       continue;
 
     // Is this operand a literal immediate?
     const MCOperand &Op = MI.getOperand(i);
-    if (getLitEncoding(Op, Desc.OpInfo[i], STI) != 255)
+    if (getLitEncoding(Op, Desc.MCOpInfo[i], STI) != 255)
       continue;
 
     // Yes! Encode it
     int64_t Imm = 0;
 
     if (Op.isImm())
       Imm = Op.getImm();
     else if (Op.isExpr()) {
if (MO.isReg()) {
     RegEnc |= MRI.getEncodingValue(Reg);
     RegEnc &= SDWA9EncValues::SRC_VGPR_MASK;
     if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) {
       RegEnc |= SDWA9EncValues::SRC_SGPR_MASK;
     }
     return RegEnc;
   } else {
     const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
-    uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
+    uint32_t Enc = getLitEncoding(MO, Desc.MCOpInfo[OpNo], STI);
     if (Enc != ~0U && Enc != 255) {
       return Enc | SDWA9EncValues::SRC_SGPR_MASK;
     }
   }
 
   llvm_unreachable("Unsupported operand kind");
   return 0;
 }
uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
   unsigned OpNo = 0;
   for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
     if (&MO == &MI.getOperand(OpNo))
       break;
   }
 
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
-    uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
+    uint32_t Enc = getLitEncoding(MO, Desc.MCOpInfo[OpNo], STI);
     if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4))
       return Enc;
 
   } else if (MO.isImm())
     return MO.getImm();
 
   llvm_unreachable("Encoding of this operand type is not supported yet.");
   return 0;
 }
 
 #define ENABLE_INSTR_PREDICATE_VERIFIER
 #include "AMDGPUGenMCCodeEmitter.inc"

lib/Target/AMDGPU/SIFoldOperands.cpp

case AMDGPU::V_FMAC_F32_e64: {
     int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
     if (static_cast<int>(OpNo) == Src2Idx) {
       bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e64;
       bool IsF32 = Opc == AMDGPU::V_MAC_F32_e64;
 
       unsigned Opc = IsFMA ?
         AMDGPU::V_FMA_F32 : (IsF32 ? AMDGPU::V_MAD_F32 : AMDGPU::V_MAD_F16);
       const MCInstrDesc &MadDesc = TII->get(Opc);
-      return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType);
+      return TII->isInlineConstant(OpToFold, MadDesc.MCOpInfo[OpNo].OperandType);
     }
     return false;
   }
   default:
     return false;
   }
 }
 
if (FoldingImm && UseMI->isCopy()) {
     CopiesToReplace.push_back(UseMI);
   } else {
     const MCInstrDesc &UseDesc = UseMI->getDesc();
 
     // Don't fold into target independent nodes.  Target independent opcodes
     // don't have defined register classes.
     if (UseDesc.isVariadic() ||
         UseOp.isImplicit() ||
-        UseDesc.OpInfo[UseOpIdx].RegClass == -1)
+        UseDesc.MCOpInfo[UseOpIdx].RegClass == -1)
       return;
   }
 
   if (!FoldingImm) {
     tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII);
 
     // FIXME: We could try to change the instruction from 64-bit to 32-bit
     // to enable more folding opportunites.  The shrink operands pass
     // already does this.
     return;
   }
 
 
   const MCInstrDesc &FoldDesc = OpToFold.getParent()->getDesc();
   const TargetRegisterClass *FoldRC =
-    TRI->getRegClass(FoldDesc.OpInfo[0].RegClass);
+    TRI->getRegClass(FoldDesc.MCOpInfo[0].RegClass);
 
 
   // Split 64-bit constants into 32-bits for folding.
   if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) {
     unsigned UseReg = UseOp.getReg();
     const TargetRegisterClass *UseRC
       = TargetRegisterInfo::isVirtualRegister(UseReg) ?
       MRI->getRegClass(UseReg) :

lib/Target/AMDGPU/SIInstrInfo.h

public:
 
   /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
   /// be an inline immediate.
   bool isInlineConstant(const MachineInstr &MI,
                         const MachineOperand &UseMO,
                         const MachineOperand &DefMO) const {
     assert(UseMO.getParent() == &MI);
     int OpIdx = MI.getOperandNo(&UseMO);
-    if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
+    if (!MI.getDesc().MCOpInfo || OpIdx >= MI.getDesc().NumMCOperands) {
       return false;
     }
 
-    return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
+    return isInlineConstant(DefMO, MI.getDesc().MCOpInfo[OpIdx]);
   }
 
   /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
   /// immediate.
   bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
     const MachineOperand &MO = MI.getOperand(OpIdx);
-    return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
+    return isInlineConstant(MO, MI.getDesc().MCOpInfo[OpIdx].OperandType);
   }
 
   bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
                         const MachineOperand &MO) const {
-    if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
+    if (!MI.getDesc().MCOpInfo || OpIdx >= MI.getDesc().NumMCOperands)
       return false;
 
     if (MI.isCopy()) {
       unsigned Size = getOpSize(MI, OpIdx);
       assert(Size == 8 || Size == 4);
 
       uint8_t OpType = (Size == 8) ?
         AMDGPU::OPERAND_REG_IMM_INT64 : AMDGPU::OPERAND_REG_IMM_INT32;
       return isInlineConstant(MO, OpType);
     }
 
-    return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
+    return isInlineConstant(MO, MI.getDesc().MCOpInfo[OpIdx].OperandType);
   }
 
   bool isInlineConstant(const MachineOperand &MO) const {
     const MachineInstr *Parent = MO.getParent();
     return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
   }
 
   bool isLiteralConstant(const MachineOperand &MO,
public:
   /// the register class of its machine operand.
   /// to infer the correct register class base on the other operands.
   const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
                                            unsigned OpNo) const;
 
   /// Return the size in bytes of the operand OpNo on the given
   // instruction opcode.
   unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
-    const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
+    const MCOperandInfo &OpInfo = get(Opcode).MCOpInfo[OpNo];
 
     if (OpInfo.RegClass == -1) {
       // If this is an immediate operand, this must be a 32-bit literal.
       assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
       return 4;
     }
 
     return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;

lib/Target/AMDGPU/SIInstrInfo.cpp

case MachineOperand::MO_Immediate:
     return Op0.getImm() == Op1.getImm();
   default:
     llvm_unreachable("Didn't expect to be comparing these operand types");
   }
 }
 
 bool SIInstrInfo::isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
                                     const MachineOperand &MO) const {
-  const MCOperandInfo &OpInfo = get(MI.getOpcode()).OpInfo[OpNo];
+  const MCOperandInfo &OpInfo = get(MI.getOpcode()).MCOpInfo[OpNo];
 
   assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
 
   if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
     return true;
 
   if (OpInfo.RegClass < 0)
     return false;
bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
   // Make sure the register classes are correct.
   for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
     if (MI.getOperand(i).isFPImm()) {
       ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
                 "all fp values to integers.";
       return false;
     }
 
-    int RegClass = Desc.OpInfo[i].RegClass;
+    int RegClass = Desc.MCOpInfo[i].RegClass;
 
-    switch (Desc.OpInfo[i].OperandType) {
+    switch (Desc.MCOpInfo[i].OperandType) {
     case MCOI::OPERAND_REGISTER:
       if (MI.getOperand(i).isImm()) {
         ErrInfo = "Illegal immediate value for operand.";
         return false;
       }
       break;
     case AMDGPU::OPERAND_REG_IMM_INT32:
     case AMDGPU::OPERAND_REG_IMM_FP32:
if (Desc.getOpcode() != AMDGPU::V_WRITELANE_B32
     unsigned SGPRUsed = findImplicitSGPRRead(MI);
     if (SGPRUsed != AMDGPU::NoRegister)
       ++ConstantBusCount;
 
     for (int OpIdx : OpIndices) {
       if (OpIdx == -1)
         break;
       const MachineOperand &MO = MI.getOperand(OpIdx);
-      if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
+      if (usesConstantBus(MRI, MO, MI.getDesc().MCOpInfo[OpIdx])) {
         if (MO.isReg()) {
           if (MO.getReg() != SGPRUsed)
             ++ConstantBusCount;
           SGPRUsed = MO.getReg();
         } else {
           ++ConstantBusCount;
           ++LiteralCount;
         }
unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
   }
 }
 
 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
                                                       unsigned OpNo) const {
   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
   const MCInstrDesc &Desc = get(MI.getOpcode());
   if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
-      Desc.OpInfo[OpNo].RegClass == -1) {
+      Desc.MCOpInfo[OpNo].RegClass == -1) {
     unsigned Reg = MI.getOperand(OpNo).getReg();
 
     if (TargetRegisterInfo::isVirtualRegister(Reg))
       return MRI.getRegClass(Reg);
     return RI.getPhysRegClass(Reg);
   }
 
-  unsigned RCID = Desc.OpInfo[OpNo].RegClass;
+  unsigned RCID = Desc.MCOpInfo[OpNo].RegClass;
   return RI.getRegClass(RCID);
 }
 
 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
   switch (MI.getOpcode()) {
   case AMDGPU::COPY:
   case AMDGPU::REG_SEQUENCE:
   case AMDGPU::PHI:
   case AMDGPU::INSERT_SUBREG:
     return RI.hasVGPRs(getOpRegClass(MI, 0));
   default:
     return RI.hasVGPRs(getOpRegClass(MI, OpNo));
   }
 }
 
 void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
   MachineBasicBlock::iterator I = MI;
   MachineBasicBlock *MBB = MI.getParent();
   MachineOperand &MO = MI.getOperand(OpIdx);
   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
-  unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass;
+  unsigned RCID = get(MI.getOpcode()).MCOpInfo[OpIdx].RegClass;
   const TargetRegisterClass *RC = RI.getRegClass(RCID);
   unsigned Opcode = AMDGPU::V_MOV_B32_e32;
   if (MO.isReg())
     Opcode = AMDGPU::COPY;
   else if (RI.isSGPRClass(RC))
     Opcode = AMDGPU::S_MOV_B32;
 
   const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,
   assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
   return true;
 }
 
 bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
                                  const MachineOperand *MO) const {
   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
   const MCInstrDesc &InstDesc = MI.getDesc();
-  const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
+  const MCOperandInfo &OpInfo = InstDesc.MCOpInfo[OpIdx];
   const TargetRegisterClass *DefinedRC =
       OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
   if (!MO)
     MO = &MI.getOperand(OpIdx);
 
   if (isVALU(MI) && usesConstantBus(MRI, *MO, OpInfo)) {
 
     RegSubRegPair SGPRUsed;
     if (MO->isReg())
       SGPRUsed = RegSubRegPair(MO->getReg(), MO->getSubReg());
 
     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
       if (i == OpIdx)
         continue;
       const MachineOperand &Op = MI.getOperand(i);
       if (Op.isReg()) {
         if ((Op.getReg() != SGPRUsed.Reg || Op.getSubReg() != SGPRUsed.SubReg) &&
-            usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) {
+            usesConstantBus(MRI, Op, InstDesc.MCOpInfo[i])) {
           return false;
         }
-      } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {
+      } else if (InstDesc.MCOpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {
         return false;
       }
     }
   }
 
   if (MO->isReg()) {
     assert(DefinedRC);
     return isLegalRegOperand(MRI, OpInfo, *MO);
if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) {
           .add(Src1);
       Src1.ChangeToRegister(Reg, false);
     }
     return;
   }
 
   // VOP2 src0 instructions support all operand types, so we don't need to check
   // their legality. If src1 is already legal, we don't need to do anything.
-  if (isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src1))
+  if (isLegalRegOperand(MRI, InstrDesc.MCOpInfo[Src1Idx], Src1))
     return;
 
   // Special case: V_READLANE_B32 accepts only immediate or SGPR operands for
   // lane select. Fix up using V_READFIRSTLANE, since we assume that the lane
   // select is uniform.
   if (Opc == AMDGPU::V_READLANE_B32 && Src1.isReg() &&
       RI.isVGPR(MRI, Src1.getReg())) {
     unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,
   MachineOperand &Src0 = MI.getOperand(Src0Idx);
 
   // If src0 can be used as src1, commuting will make the operands legal.
   // Otherwise we have to give up and insert a move.
   //
   // TODO: Other immediate-like operand kinds could be commuted if there was a
   // MachineOperand::ChangeTo* for them.
   if ((!Src1.isImm() && !Src1.isReg()) ||
-      !isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) {
+      !isLegalRegOperand(MRI, InstrDesc.MCOpInfo[Src1Idx], Src0)) {
     legalizeOpWithMove(MI, Src1Idx);
     return;
   }
 
   int CommutedOpc = commuteOpcode(MI);
   if (CommutedOpc == -1) {
     legalizeOpWithMove(MI, Src1Idx);
     return;
void SIInstrInfo::legalizeOperands(MachineInstr &MI) const {
   // FIXME: If we start using the non-addr64 instructions for compute, we
   // may need to legalize them as above. This especially applies to the
   // buffer_load_format_* variants and variants with idxen (or bothen).
   int SRsrcIdx =
       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
   if (SRsrcIdx != -1) {
     // We have an MUBUF instruction
     MachineOperand *SRsrc = &MI.getOperand(SRsrcIdx);
-    unsigned SRsrcRC = get(MI.getOpcode()).OpInfo[SRsrcIdx].RegClass;
+    unsigned SRsrcRC = get(MI.getOpcode()).MCOpInfo[SRsrcIdx].RegClass;
     if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
                                              RI.getRegClass(SRsrcRC))) {
       // The operands are legal.
       // FIXME: We may need to legalize operands besided srsrc.
       return;
     }
 
     MachineBasicBlock &MBB = *MI.getParent();
if (Idx == -1)
       break;
 
     const MachineOperand &MO = MI.getOperand(Idx);
     if (!MO.isReg())
       continue;
 
     // Is this operand statically required to be an SGPR based on the operand
     // constraints?
-    const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
+    const TargetRegisterClass *OpRC = RI.getRegClass(Desc.MCOpInfo[Idx].RegClass);
     bool IsRequiredSGPR = RI.isSGPRClass(OpRC);
     if (IsRequiredSGPR)
       return MO.getReg();
 
     // If this could be a VGPR or an SGPR, Check the dynamic register class.
     unsigned Reg = MO.getReg();
     const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
     if (RI.isSGPRClass(RegRC))
unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
 
   // 4-byte instructions may have a 32-bit literal encoded after them. Check
   // operands that coud ever be literals.
   if (isVALU(MI) || isSALU(MI)) {
     int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
     if (Src0Idx == -1)
       return 4; // No operands.
 
-    if (isLiteralConstantLike(MI.getOperand(Src0Idx), Desc.OpInfo[Src0Idx]))
+    if (isLiteralConstantLike(MI.getOperand(Src0Idx), Desc.MCOpInfo[Src0Idx]))
       return 8;
 
     int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
     if (Src1Idx == -1)
       return 4;
 
-    if (isLiteralConstantLike(MI.getOperand(Src1Idx), Desc.OpInfo[Src1Idx]))
+    if (isLiteralConstantLike(MI.getOperand(Src1Idx), Desc.MCOpInfo[Src1Idx]))
       return 8;
 
     return 4;
   }
 
   if (DescSize == 4)
     return 4;
 
bool SIInstrInfo::isBufferSMRD(const MachineInstr &MI) const {
   if (!isSMRD(MI))
     return false;
 
   // Check that it is using a buffer resource.
   int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sbase);
   if (Idx == -1) // e.g. s_memtime
     return false;
 
-  const auto RCID = MI.getDesc().OpInfo[Idx].RegClass;
+  const auto RCID = MI.getDesc().MCOpInfo[Idx].RegClass;
   return RCID == AMDGPU::SReg_128RegClassID;
 }
 
 // This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
 enum SIEncodingFamily {
   SI = 0,
   VI = 1,
   SDWA = 2,

lib/Target/AMDGPU/SIPeepholeSDWA.cpp

void SIPeepholeSDWA::legalizeScalarOperands(MachineInstr &MI,
                                             const GCNSubtarget &ST) const {
   const MCInstrDesc &Desc = TII->get(MI.getOpcode());
   unsigned ConstantBusCount = 0;
   for (MachineOperand &Op : MI.explicit_uses()) {
     if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg())))
       continue;
 
     unsigned I = MI.getOperandNo(&Op);
-    if (Desc.OpInfo[I].RegClass == -1 ||
-       !TRI->hasVGPRs(TRI->getRegClass(Desc.OpInfo[I].RegClass)))
+    if (Desc.MCOpInfo[I].RegClass == -1 ||
+       !TRI->hasVGPRs(TRI->getRegClass(Desc.MCOpInfo[I].RegClass)))
       continue;
 
     if (ST.hasSDWAScalar() && ConstantBusCount == 0 && Op.isReg() &&
         TRI->isSGPRReg(*MRI, Op.getReg())) {
       ++ConstantBusCount;
       continue;
     }
 

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
 
   default:
     llvm_unreachable("unhandled operand type");
   }
 }
 
 LLVM_READNONE
 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
-  return getOperandSize(Desc.OpInfo[OpNo]);
+  return getOperandSize(Desc.MCOpInfo[OpNo]);
 }
 
 /// Is this literal inlinable
 LLVM_READNONE
 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
 
 LLVM_READNONE
 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

unsigned mc2PseudoReg(unsigned Reg) {
   MAP_REG2REG
 }
 
 #undef CASE_CI_VI
 #undef CASE_VI_GFX9
 #undef MAP_REG2REG
 
 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
-  assert(OpNo < Desc.NumOperands);
-  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
+  assert(OpNo < Desc.NumMCOperands);
+  unsigned OpType = Desc.MCOpInfo[OpNo].OperandType;
   return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
          OpType <= AMDGPU::OPERAND_SRC_LAST;
 }
 
 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
-  assert(OpNo < Desc.NumOperands);
-  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
+  assert(OpNo < Desc.NumMCOperands);
+  unsigned OpType = Desc.MCOpInfo[OpNo].OperandType;
   switch (OpType) {
   case AMDGPU::OPERAND_REG_IMM_FP32:
   case AMDGPU::OPERAND_REG_IMM_FP64:
   case AMDGPU::OPERAND_REG_IMM_FP16:
   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
     return true;
   default:
     return false;
   }
 }
 
 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
-  assert(OpNo < Desc.NumOperands);
-  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
+  assert(OpNo < Desc.NumMCOperands);
+  unsigned OpType = Desc.MCOpInfo[OpNo].OperandType;
   return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
          OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST;
 }
 
 // Avoid using MCRegisterClass::getSize, since that function will go away
 // (move from MC* level to Target* level). Return size in bits.
 unsigned getRegBitWidth(unsigned RCID) {
   switch (RCID) {

 }
 
 unsigned getRegBitWidth(const MCRegisterClass &RC) {
   return getRegBitWidth(RC.getID());
 }
 
 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
                            unsigned OpNo) {
-  assert(OpNo < Desc.NumOperands);
-  unsigned RCID = Desc.OpInfo[OpNo].RegClass;
+  assert(OpNo < Desc.NumMCOperands);
+  unsigned RCID = Desc.MCOpInfo[OpNo].RegClass;
   return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
 }
 
 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
   if (Literal >= -16 && Literal <= 64)
     return true;
 
   uint64_t Val = static_cast<uint64_t>(Literal);

lib/Target/ARM/ARMBaseInstrInfo.cpp

ARMBaseInstrInfo::optimizeSelect(MachineInstr &MI,
   // Create a new predicated version of DefMI.
   // Rfalse is the first use.
   MachineInstrBuilder NewMI =
       BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
 
   // Copy all the DefMI operands, excluding its (null) predicate.
   const MCInstrDesc &DefDesc = DefMI->getDesc();
   for (unsigned i = 1, e = DefDesc.getNumOperands();
-       i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
+       i != e && !DefDesc.MCOpInfo[i].isPredicate(); ++i)
     NewMI.add(DefMI->getOperand(i));
 
   unsigned CondCode = MI.getOperand(3).getImm();
   if (Invert)
     NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
   else
     NewMI.addImm(CondCode);
   NewMI.add(MI.getOperand(4));

lib/Target/ARM/ARMISelLowering.cpp

if (Subtarget->isThumb1Only()) {
       ccOutIdx = 1;
     } else
       ccOutIdx = MCID->getNumOperands() - 1;
   } else
     ccOutIdx = MCID->getNumOperands() - 1;
 
   // Any ARM instruction that sets the 's' bit should specify an optional
   // "cc_out" operand in the last operand position.
-  if (!MI.hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
+  if (!MI.hasOptionalDef() || !MCID->MCOpInfo[ccOutIdx].isOptionalDef()) {
     assert(!NewOpc && "Optional cc_out operand required");
     return;
   }
   // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
   // since we already have an optional CPSR def.
   bool definesCPSR = false;
   bool deadCPSR = false;
   for (unsigned i = MCID->getNumOperands(), e = MI.getNumOperands(); i != e;

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
   // suffix depending on whether they're in an IT block or not.
   unsigned Opc = Inst.getOpcode();
   const MCInstrDesc &MCID = MII.get(Opc);
   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
     assert(MCID.hasOptionalDef() &&
            "optionally flag setting instruction missing optional def operand");
-    assert(MCID.NumOperands == Inst.getNumOperands() &&
+    assert(MCID.NumMCOperands == Inst.getNumOperands() &&
            "operand count mismatch!");
     // Find the optional-def operand (cc_out).
     unsigned OpNo;
     for (OpNo = 0;
-         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
+         !MCID.MCOpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumMCOperands;
          ++OpNo)
       ;
     // If we're parsing Thumb1, reject it completely.
     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
       return Match_RequiresFlagSetting;
     // If we're parsing Thumb2, which form is legal depends on whether we're
     // in an IT block.
     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   }
 
   // Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of
   // ARMv8-A.
   if ((Inst.getOpcode() == ARM::VMRS || Inst.getOpcode() == ARM::VMSR) &&
       Inst.getOperand(0).getReg() == ARM::SP && (isThumb() && !hasV8Ops()))
     return Match_InvalidOperand;
 
-  for (unsigned I = 0; I < MCID.NumOperands; ++I)
-    if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
+  for (unsigned I = 0; I < MCID.NumMCOperands; ++I)
+    if (MCID.MCOpInfo[I].RegClass == ARM::rGPRRegClassID) {
       // rGPRRegClass excludes PC, and also excluded SP before ARMv8
       if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops())
         return Match_RequiresV8;
       else if (Inst.getOperand(I).getReg() == ARM::PC)
         return Match_InvalidOperand;
     }
 
   return Match_Success;

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
   Dis->tryAddingPcLoadReferenceComment(Value, Address);
 }
 
 // Thumb1 instructions don't have explicit S bits.  Rather, they
 // implicitly set CPSR.  Since it's not represented in the encoding, the
 // auto-generated decoder won't inject the CPSR operand.  We need to fix
 // that as a post-pass.
 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
-  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
-  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
+  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].MCOpInfo;
+  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumMCOperands;
   MCInst::iterator I = MI.begin();
   for (unsigned i = 0; i < NumOps; ++i, ++I) {
     if (I == MI.end()) break;
     if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
       if (i > 0 && OpInfo[i-1].isPredicate()) continue;
       MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
       return;
     }
ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
   // assume a predicate of AL.
   unsigned CC;
   CC = ITBlock.getITCC();
   if (CC == 0xF)
     CC = ARMCC::AL;
   if (ITBlock.instrInITBlock())
     ITBlock.advanceITState();
 
-  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
-  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
+  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].MCOpInfo;
+  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumMCOperands;
   MCInst::iterator I = MI.begin();
   for (unsigned i = 0; i < NumOps; ++i, ++I) {
     if (I == MI.end()) break;
     if (OpInfo[i].isPredicate()) {
       I = MI.insert(I, MCOperand::createImm(CC));
       ++I;
       if (CC == ARMCC::AL)
         MI.insert(I, MCOperand::createReg(0));

 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
   unsigned CC;
   CC = ITBlock.getITCC();
   if (CC == 0xF)
     CC = ARMCC::AL;
   if (ITBlock.instrInITBlock())
     ITBlock.advanceITState();
 
-  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
+  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].MCOpInfo;
   MCInst::iterator I = MI.begin();
-  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
+  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumMCOperands;
   for (unsigned i = 0; i < NumOps; ++i, ++I) {
     if (OpInfo[i].isPredicate() ) {
       I->setImm(CC);
       ++I;
       if (CC == ARMCC::AL)
         I->setReg(0);
       else
         I->setReg(ARM::CPSR);

lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

bool isConditionalBranch(const MCInst &Inst) const override {
     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
       return false;
     return MCInstrAnalysis::isConditionalBranch(Inst);
   }
 
   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
                       uint64_t Size, uint64_t &Target) const override {
     // We only handle PCRel branches for now.
-    if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
+    if (Info->get(Inst.getOpcode()).MCOpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
       return false;
 
     int64_t Imm = Inst.getOperand(0).getImm();
     Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
     return true;
   }
 };
 
 class ThumbMCInstrAnalysis : public ARMMCInstrAnalysis {
 public:
   ThumbMCInstrAnalysis(const MCInstrInfo *Info) : ARMMCInstrAnalysis(Info) {}
 
   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
                       uint64_t Size, uint64_t &Target) const override {
     // We only handle PCRel branches for now.
-    if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
+    if (Info->get(Inst.getOpcode()).MCOpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
       return false;
 
     int64_t Imm = Inst.getOperand(0).getImm();
     Target = Addr+Imm+4; // In Thumb mode the PC is always off by 4 bytes.
     return true;
   }
 };
 

lib/Target/ARM/Thumb2SizeReduction.cpp

Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
   MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
   MIB.add(MI->getOperand(0));
   if (NewMCID.hasOptionalDef())
     MIB.add(HasCC ? t1CondCodeOp(CCDead) : condCodeOp());
 
   // Transfer the rest of operands.
   unsigned NumOps = MCID.getNumOperands();
   for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
-    if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
+    if (i < NumOps && MCID.MCOpInfo[i].isOptionalDef())
       continue;
-    if (SkipPred && MCID.OpInfo[i].isPredicate())
+    if (SkipPred && MCID.MCOpInfo[i].isPredicate())
       continue;
     MIB.add(MI->getOperand(i));
   }
 
   // Transfer MI flags.
   MIB.setMIFlags(MI->getFlags());
 
   LLVM_DEBUG(errs() << "Converted 32-bit: " << *MI
if (!OptimizeSize && Entry.AvoidMovs && STI->avoidMOVsShifterOperand())
     return false;
 
   unsigned Limit = ~0U;
   if (Entry.Imm1Limit)
     Limit = (1 << Entry.Imm1Limit) - 1;
 
   const MCInstrDesc &MCID = MI->getDesc();
   for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
-    if (MCID.OpInfo[i].isPredicate())
+    if (MCID.MCOpInfo[i].isPredicate())
       continue;
     const MachineOperand &MO = MI->getOperand(i);
     if (MO.isReg()) {
       unsigned Reg = MO.getReg();
       if (!Reg || Reg == ARM::CPSR)
         continue;
       if (Entry.LowRegs1 && !isARMLowRegister(Reg))
         return false;
     } else if (MO.isImm() &&
-               !MCID.OpInfo[i].isPredicate()) {
+               !MCID.MCOpInfo[i].isPredicate()) {
       if (((unsigned)MO.getImm()) > Limit)
         return false;
     }
   }
 
   // Check if it's possible / necessary to transfer the predicate.
   const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1);
   unsigned PredReg = 0;
Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
   MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
   MIB.add(MI->getOperand(0));
   if (NewMCID.hasOptionalDef())
     MIB.add(HasCC ? t1CondCodeOp(CCDead) : condCodeOp());
 
   // Transfer the rest of operands.
   unsigned NumOps = MCID.getNumOperands();
   for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
-    if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
+    if (i < NumOps && MCID.MCOpInfo[i].isOptionalDef())
       continue;
     if ((MCID.getOpcode() == ARM::t2RSBSri ||
          MCID.getOpcode() == ARM::t2RSBri ||
          MCID.getOpcode() == ARM::t2SXTB ||
          MCID.getOpcode() == ARM::t2SXTH ||
          MCID.getOpcode() == ARM::t2UXTB ||
          MCID.getOpcode() == ARM::t2UXTH) && i == 2)
       // Skip the zero immediate operand, it's now implicit.
       continue;
-    bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate());
+    bool isPred = (i < NumOps && MCID.MCOpInfo[i].isPredicate());
     if (SkipPred && isPred)
         continue;
     const MachineOperand &MO = MI->getOperand(i);
     if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
       // Skip implicit def of CPSR. Either it's modeled as an optional
       // def now or it's already an implicit def on the new instruction.
       continue;
     MIB.add(MO);

lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp

if (std::get<2>(Producer).Register == Consumer.Register &&
           std::get<0>(Producer)->getLoc(),
           "Register producer has the opposite predicate sense as consumer");
       reportError(I.getLoc(),
                   "Instruction does not have a valid new register producer");
       return false;
     }
     MCInstrDesc const &Desc =
         HexagonMCInstrInfo::getDesc(MCII, *std::get<0>(Producer));
-    if (Desc.OpInfo[std::get<1>(Producer)].RegClass ==
+    if (Desc.MCOpInfo[std::get<1>(Producer)].RegClass ==
         Hexagon::DoubleRegsRegClassID) {
       reportNote(std::get<0>(Producer)->getLoc(),
                  "Double registers cannot be new-value producers");
       reportError(I.getLoc(),
                   "Instruction does not have a valid new register producer");
       return false;
     }
     if ((Desc.mayLoad() && std::get<1>(Producer) == 1) ||

lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp

 }
 
 HexagonMCInstrInfo::PredicateInfo
 HexagonMCInstrInfo::predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI) {
   if (!isPredicated(MCII, MCI))
     return {0, 0, false};
   MCInstrDesc const &Desc = getDesc(MCII, MCI);
   for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; ++I)
-    if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
+    if (Desc.MCOpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
       return {MCI.getOperand(I).getReg(), I, isPredicatedTrue(MCII, MCI)};
   return {0, 0, false};
 }
 
 bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII,
                                       MCInst const &MCI) {
   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
   return (F >> HexagonII::PrefersSlot3Pos) & HexagonII::PrefersSlot3Mask;

lib/Target/Lanai/LanaiInstrInfo.cpp

LanaiInstrInfo::optimizeSelect(MachineInstr &MI,
 
   // Create a new predicated version of DefMI.
   MachineInstrBuilder NewMI =
       BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
 
   // Copy all the DefMI operands, excluding its (null) predicate.
   const MCInstrDesc &DefDesc = DefMI->getDesc();
   for (unsigned i = 1, e = DefDesc.getNumOperands();
-       i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
+       i != e && !DefDesc.MCOpInfo[i].isPredicate(); ++i)
     NewMI.add(DefMI->getOperand(i));
 
   unsigned CondCode = MI.getOperand(3).getImm();
   if (Invert)
     NewMI.addImm(getOppositeCondition(LPCC::CondCode(CondCode)));
   else
     NewMI.addImm(CondCode);
   NewMI.copyImplicitOps(MI);

lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp

public:
   explicit LanaiMCInstrAnalysis(const MCInstrInfo *Info)
       : MCInstrAnalysis(Info) {}
 
   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
                       uint64_t &Target) const override {
     if (Inst.getNumOperands() == 0)
       return false;
 
-    if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType ==
+    if (Info->get(Inst.getOpcode()).MCOpInfo[0].OperandType ==
         MCOI::OPERAND_PCREL) {
       int64_t Imm = Inst.getOperand(0).getImm();
       Target = Addr + Size + Imm;
       return true;
     } else {
       int64_t Imm = Inst.getOperand(0).getImm();
 
       // Skip case where immediate is 0 as that occurs in file that isn't linked

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

if ((Inst.getOpcode() == Mips::JAL || Inst.getOpcode() == Mips::JAL_MM) &&
     ExpandedJalSym = true;
   }
 
   bool IsPCRelativeLoad = (MCID.TSFlags & MipsII::IsPCRelativeLoad) != 0;
   if ((MCID.mayLoad() || MCID.mayStore()) && !IsPCRelativeLoad) {
     // Check the offset of memory operand, if it is a symbol
     // reference or immediate we may have to expand instructions.
     for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
-      const MCOperandInfo &OpInfo = MCID.OpInfo[i];
+      const MCOperandInfo &OpInfo = MCID.MCOpInfo[i];
       if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
           (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
         MCOperand &Op = Inst.getOperand(i);
         if (Op.isImm()) {
           int64_t MemOffset = Op.getImm();
           if (MemOffset < -32768 || MemOffset > 32767) {
             // Offset can't exceed 16bit value.
             expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad());
for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
       }
     } // for
   }   // if load/store
 
   if (inMicroMipsMode()) {
     if (MCID.mayLoad() && Inst.getOpcode() != Mips::LWP_MM) {
       // Try to create 16-bit GP relative load instruction.
       for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
-        const MCOperandInfo &OpInfo = MCID.OpInfo[i];
+        const MCOperandInfo &OpInfo = MCID.MCOpInfo[i];
         if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
             (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
           MCOperand &Op = Inst.getOperand(i);
           if (Op.isImm()) {
             int MemOffset = Op.getImm();
             MCOperand &DstReg = Inst.getOperand(0);
             MCOperand &BaseReg = Inst.getOperand(1);
             if (isInt<9>(MemOffset) && (MemOffset % 4 == 0) &&
void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
   const MCOperand &OffsetOp = Inst.getOperand(2);
 
   MipsTargetStreamer &TOut = getTargetStreamer();
   unsigned DstReg = DstRegOp.getReg();
   unsigned BaseReg = BaseRegOp.getReg();
   unsigned TmpReg = DstReg;
 
   const MCInstrDesc &Desc = getInstDesc(Inst.getOpcode());
-  int16_t DstRegClass = Desc.OpInfo[0].RegClass;
+  int16_t DstRegClass = Desc.MCOpInfo[0].RegClass;
   unsigned DstRegClassID =
       getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
   bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
                (DstRegClassID == Mips::GPR64RegClassID);
 
   if (!IsLoad || !IsGPR || (BaseReg == DstReg)) {
     // At this point we need AT to perform the expansions
     // and we exit if it is not available.

lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp

 public:
   MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
 
   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
                       uint64_t &Target) const override {
     unsigned NumOps = Inst.getNumOperands();
     if (NumOps == 0)
       return false;
-    switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {
+    switch (Info->get(Inst.getOpcode()).MCOpInfo[NumOps - 1].OperandType) {
     case MCOI::OPERAND_UNKNOWN:
     case MCOI::OPERAND_IMMEDIATE:
       // jal, bal ...
       Target = Inst.getOperand(NumOps - 1).getImm();
       return true;
     case MCOI::OPERAND_PCREL:
       // b, j, beq ...
       Target = Addr + Inst.getOperand(NumOps - 1).getImm();

lib/Target/Mips/MipsSEInstrInfo.cpp

void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator I) const {
   BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
 }
 
 std::pair<bool, bool>
 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
                                  const MachineFunction &MF) const {
   const MCInstrDesc &Desc = get(Opc);
-  assert(Desc.NumOperands == 2 && "Unary instruction expected.");
+  assert(Desc.NumMCOperands == 2 && "Unary instruction expected.");
   const MipsRegisterInfo *RI = &getRegisterInfo();
   unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF));
   unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF));
 
   return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
 }
 
 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,

lib/Target/PowerPC/PPCInstrInfo.cpp

bool PPCInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
   for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
     if (UseMI.getOperand(UseIdx).isReg() &&
         UseMI.getOperand(UseIdx).getReg() == Reg)
       break;
 
   assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
   assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
 
-  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
+  const MCOperandInfo *UseInfo = &UseMCID.MCOpInfo[UseIdx];
 
   // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
   // register (which might also be specified as a pointer class kind).
   if (UseInfo->isLookupPtrRegClass()) {
     if (UseInfo->RegClass /* Kind */ != 1)
       return false;
   } else {
     if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&

utils/TableGen/InstrInfoEmitter.cpp

private:
   void emitTIIHelperMethods(raw_ostream &OS, StringRef TargetName);
 
   /// Expand TIIPredicate definitions to functions that accept a const MCInst
   /// reference.
   void emitMCIIHelperMethods(raw_ostream &OS, StringRef TargetName);
   void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                   Record *InstrInfo,
                   std::map<std::vector<Record*>, unsigned> &EL,
-                  const OperandInfoMapTy &OpInfo,
+                  const OperandInfoMapTy &MIOpInfo,
+                  const OperandInfoMapTy &MCOpInfo,
                   raw_ostream &OS);
   void emitOperandTypesEnum(raw_ostream &OS, const CodeGenTarget &Target);
   void initOperandMapData(
             ArrayRef<const CodeGenInstruction *> NumberedInstructions,
             StringRef Namespace,
             std::map<std::string, unsigned> &Operands,
             OpNameMapTy &OperandMap);
   void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target,
             ArrayRef<const CodeGenInstruction*> NumberedInstructions);
 
   // Operand information.
-  void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
-  std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
+  void EmitMIOperandInfo(raw_ostream &OS, OperandInfoMapTy &MCOperandInfoIDs);
+  std::vector<std::string> GetMIOperandInfo(const CodeGenTarget &Target,
+                                            const CodeGenInstruction &Inst);
+
+  void EmitMCOperandInfo(raw_ostream &OS, OperandInfoMapTy &MCOperandInfoIDs);
+  std::vector<std::string> GetMCOperandInfo(const CodeGenInstruction &Inst);
 };
 
 } // end anonymous namespace
 
 static void PrintDefList(const std::vector<Record*> &Uses,
                          unsigned Num, raw_ostream &OS) {
   OS << "static const MCPhysReg ImplicitList" << Num << "[] = { ";
   for (Record *U : Uses)
     OS << getQualifiedName(U) << ", ";
   OS << "0 };\n";
 }
 
 //===----------------------------------------------------------------------===//
 // Operand Info Emission.
 //===----------------------------------------------------------------------===//
 
 std::vector<std::string>
-InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
+InstrInfoEmitter::GetMIOperandInfo(const CodeGenTarget &Target,
+                                   const CodeGenInstruction &Inst) {
+
+  std::vector<std::string> Result;
+
+  const std::string &Namespace = Target.getInstNamespace();
+
+  for (auto &Op : Inst.Operands) {
+
+    // One record
+    std::string Res;
+
+    // This might be a multiple operand thing.  Targets like X86 have
+    // registers in their multi-operand operands.  It may also be an anonymous
+    // operand, which has a single operand, but no declared class for the
+    // operand.
+    DagInit *MIOI = Op.MIOperandInfo;
+
+    if (!MIOI || MIOI->getNumArgs() == 0) {
+      Res = std::to_string(Op.MIOperandNo) + ", " + Op.OperandType + ", 1";
+    } else {
+      Res = std::to_string(Op.MIOperandNo) + ", " + Namespace +
+            "::MIOpTypes::" + Op.Rec->getName().str() + ", " +
+            std::to_string(Op.MINumOperands);
+    }
+
+    Result.push_back(Res);
+  }
+
+  return Result;
+}
+
+void InstrInfoEmitter::EmitMIOperandInfo(raw_ostream &OS,
+                                         OperandInfoMapTy &MIOperandInfoIDs) {
+  // ID #0 is for no operand info.
+  unsigned OperandListNum = 0;
+  MIOperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
+
+  OS << "\n";
+  const CodeGenTarget &Target = CDP.getTargetInfo();
+  for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
+    std::vector<std::string> OperandInfo = GetMIOperandInfo(Target, *Inst);
+    unsigned &N = MIOperandInfoIDs[OperandInfo];
+    if (N != 0)
+      continue;
+
+    N = ++OperandListNum;
+    OS << "static const MIOperandInfo MIOperandInfo" << N << "[] = { ";
+    for (const std::string &Info : OperandInfo)
+      OS << "{ " << Info << " }, ";
+    OS << "};\n";
+  }
+}
+
+std::vector<std::string>
+InstrInfoEmitter::GetMCOperandInfo(const CodeGenInstruction &Inst) {
   std::vector<std::string> Result;
 
   for (auto &Op : Inst.Operands) {
     // Handle aggregate operands and normal operands the same way by expanding
     // either case into a list of operands for this op.
     std::vector<CGIOperandList::OperandInfo> OperandList;
 
     // This might be a multiple operand thing.  Targets like X86 have
for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
 
       Result.push_back(Res);
     }
   }
 
   return Result;
 }
 
-void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
-                                       OperandInfoMapTy &OperandInfoIDs) {
+void InstrInfoEmitter::EmitMCOperandInfo(raw_ostream &OS,
+                                         OperandInfoMapTy &MCOperandInfoIDs) {
   // ID #0 is for no operand info.
   unsigned OperandListNum = 0;
-  OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
+  MCOperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
 
   OS << "\n";
   const CodeGenTarget &Target = CDP.getTargetInfo();
   for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
-    std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
-    unsigned &N = OperandInfoIDs[OperandInfo];
+    std::vector<std::string> OperandInfo = GetMCOperandInfo(*Inst);
+    unsigned &N = MCOperandInfoIDs[OperandInfo];
     if (N != 0) continue;
 
     N = ++OperandListNum;
-    OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
+    OS << "static const MCOperandInfo MCOperandInfo" << N << "[] = { ";
     for (const std::string &Info : OperandInfo)
       OS << "{ " << Info << " }, ";
     OS << "};\n";
   }
 }
 
 /// Initialize data structures for generating operand name mappings.
-/// 
+///
 /// \param Operands [out] A map used to generate the OpName enum with operand
 ///        names as its keys and operand enum values as its values.
 /// \param OperandMap [out] A map for representing the operand name mappings for
 ///        each instructions.  This is used to generate the OperandMap table as
 ///        well as the getNamedOperandIdx() function.
 void InstrInfoEmitter::initOperandMapData(
         ArrayRef<const CodeGenInstruction *> NumberedInstructions,
         StringRef Namespace,

 /// llvm::TargetNamespace::OpTypes namespace.
 /// Operand types are all definitions derived of the Operand Target.td class.
 void InstrInfoEmitter::emitOperandTypesEnum(raw_ostream &OS,
                                             const CodeGenTarget &Target) {
 
   StringRef Namespace = Target.getInstNamespace();
   std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
 
-  OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
-  OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
-  OS << "namespace llvm {\n";
   OS << "namespace " << Namespace << " {\n";
-  OS << "namespace OpTypes {\n";
-  OS << "enum OperandType {\n";
+  OS << "namespace MIOpTypes {\n";
+  OS << "enum MIOperandType {\n";
 
-  unsigned EnumVal = 0;
+  bool First = true;
   for (const Record *Op : Operands) {
-    if (!Op->isAnonymous())
-      OS << "  " << Op->getName() << " = " << EnumVal << ",\n";
-    ++EnumVal;
+    OS << "  " << Op->getName();
+    if (First) {
+      OS << " = llvm::MCOI::OPERAND_FIRST_TARGET";
+      First = false;
+    }
+    OS << ",\n";
   }
 
   OS << "  OPERAND_TYPE_LIST_END" << "\n};\n";
   OS << "} // end namespace OpTypes\n";
   OS << "} // end namespace " << Namespace << "\n";
-  OS << "} // end namespace llvm\n";
-  OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n\n";
 }
 
 void InstrInfoEmitter::emitMCIIHelperMethods(raw_ostream &OS,
                                              StringRef TargetName) {
   RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
   if (TIIPredicates.empty())
     return;
 

 // Main Output.
 //===----------------------------------------------------------------------===//
 
 // run - Emit the main instruction description records for the target...
 void InstrInfoEmitter::run(raw_ostream &OS) {
   emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS);
   emitEnums(OS);
 
+  // Get the MI types separately from data
+  OS << "#ifdef GET_INSTRINFO_MI_OPS_INFO\n";
+  OS << "#undef GET_INSTRINFO_MI_OPS_INFO\n";
+  OS << "namespace llvm {\n\n";
+
+  emitOperandTypesEnum(OS, CDP.getTargetInfo());
+
+  OS << "} // end llvm namespace\n";
+  OS << "#endif // GET_INSTRINFO_MI_OPS_INFO\n\n";
+
   OS << "#ifdef GET_INSTRINFO_MC_DESC\n";
   OS << "#undef GET_INSTRINFO_MC_DESC\n";
 
   OS << "namespace llvm {\n\n";
 
+  emitOperandTypesEnum(OS, CDP.getTargetInfo());
+
   CodeGenTarget &Target = CDP.getTargetInfo();
   const std::string &TargetName = Target.getName();
   Record *InstrInfo = Target.getInstructionSet();
 
   // Keep track of all of the def lists we have emitted already.
   std::map<std::vector<Record*>, unsigned> EmittedLists;
   unsigned ListNumber = 0;
 
   // Emit all of the instruction's implicit uses and defs.
   for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
     Record *Inst = II->TheDef;
     std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
     if (!Uses.empty()) {
       unsigned &IL = EmittedLists[Uses];
       if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
     }
     std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
     if (!Defs.empty()) {
       unsigned &IL = EmittedLists[Defs];
       if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
     }
   }
 
-  OperandInfoMapTy OperandInfoIDs;
+  OperandInfoMapTy MIOperandInfoIDs;
+  OperandInfoMapTy MCOperandInfoIDs;
 
   // Emit all of the operand info records.
-  EmitOperandInfo(OS, OperandInfoIDs);
+  EmitMIOperandInfo(OS, MIOperandInfoIDs);
+  EmitMCOperandInfo(OS, MCOperandInfoIDs);
 
   // Emit all of the MCInstrDesc records in their ENUM ordering.
   //
   OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
   ArrayRef<const CodeGenInstruction*> NumberedInstructions =
     Target.getInstructionsByEnumValue();
 
   SequenceToOffsetTable<std::string> InstrNames;
   unsigned Num = 0;
   for (const CodeGenInstruction *Inst : NumberedInstructions) {
     // Keep a list of the instruction names.
     InstrNames.add(Inst->TheDef->getName());
     // Emit the record into the table.
-    emitRecord(*Inst, Num++, InstrInfo, EmittedLists, OperandInfoIDs, OS);
+    emitRecord(
+        *Inst, Num++, InstrInfo, EmittedLists,
+        MIOperandInfoIDs, MCOperandInfoIDs, OS);
   }
   OS << "};\n\n";
 
   // Emit the array of instruction names.
   InstrNames.layout();
   OS << "extern const char " << TargetName << "InstrNameData[] = {\n";
   InstrNames.emit(OS, printChar);
   OS << "};\n\n";
OS << ClassName << "::" << ClassName
      << "InstrNameIndices, " << TargetName << "InstrNameData, "
      << NumberedInstructions.size() << ");\n}\n";
   OS << "} // end llvm namespace\n";
 
   OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n";
 
   emitOperandNameMappings(OS, Target, NumberedInstructions);
 
-  emitOperandTypesEnum(OS, Target);
-
   emitMCIIHelperMethods(OS, TargetName);
 }
 
 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                                   Record *InstrInfo,
-                         std::map<std::vector<Record*>, unsigned> &EmittedLists,
-                                  const OperandInfoMapTy &OpInfo,
+                         std::map<std::vector<Record *>, unsigned> &EmittedLists,
+                                  const OperandInfoMapTy &MIOpInfo,
+                                  const OperandInfoMapTy &MCOpInfo,
                                   raw_ostream &OS) {
   int MinOperands = 0;
-  if (!Inst.Operands.empty())
+  if (!Inst.Operands.empty()) {
+
     // Each logical operand can be multiple MI operands.
     MinOperands = Inst.Operands.back().MIOperandNo +
                   Inst.Operands.back().MINumOperands;
+  }
 
   OS << "  { ";
-  OS << Num << ",\t" << MinOperands << ",\t"
+  OS << Num << ",\t"
+     << Inst.Operands.size() << ",\t"
+     << MinOperands << ",\t"
      << Inst.Operands.NumDefs << ",\t"
      << Inst.TheDef->getValueAsInt("Size") << ",\t"
      << SchedModels.getSchedClassIdx(Inst) << ",\t0";
 
   CodeGenTarget &Target = CDP.getTargetInfo();
 
   // Emit all of the target independent flags...
   if (Inst.isPseudo)           OS << "|(1ULL<<MCID::Pseudo)";
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
 
   std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
   if (DefList.empty())
     OS << "nullptr, ";
   else
     OS << "ImplicitList" << EmittedLists[DefList] << ", ";
 
   // Emit the operand info.
-  std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
-  if (OperandInfo.empty())
+  std::vector<std::string> MIOperandInfo =
+      GetMIOperandInfo(CDP.getTargetInfo(), Inst);
+  if (MIOperandInfo.empty())
+    OS << "nullptr";
+  else
+    OS << "MIOperandInfo" << MIOpInfo.find(MIOperandInfo)->second;
+  OS << ", ";
+
+  std::vector<std::string> MCOperandInfo = GetMCOperandInfo(Inst);
+  if (MCOperandInfo.empty())
     OS << "nullptr";
   else
-    OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
+    OS << "MCOperandInfo" << MCOpInfo.find(MCOperandInfo)->second;
 
   if (Inst.HasComplexDeprecationPredicate)
     // Emit a function pointer to the complex predicate method.
     OS << ", -1 "
        << ",&get" << Inst.DeprecatedReason << "DeprecationInfo";
   else if (!Inst.DeprecatedReason.empty())
     // Emit the Subtarget feature.
     OS << ", " << Target.getInstNamespace() << "::" << Inst.DeprecatedReason