[TableGen] Add Logical operands info emission

[m4yers]

Summary

This patch is part of a bigger one D50314. It adds a possibility to emit a
logical operands info.

This feature can be used to simplify CISC machine code emission as it done in
M68K D50314 patch. You can check out M680x0MCCodeEmitter.cpp to see how it is
used. In short, it gives a "logical view" onto machine instruction operands
list, as it was defined in the tablegen files.

The main changes are in MCInstrDesc.h and InstrInfoEmitter.cpp, the rest of the
diff is just renaming for consistency sake.

[lebedev.ri]

The main changes are in MCInstrDesc.h and InstrInfoEmitter.cpp,
the rest of the diff is just renaming for consistency sake.

Which results in a *lot* of noise.
It would be best to further split this into the actual changes, and a follow-up "just renaming for consistency sake."

[m4yers]

In D50856#1202925, @lebedev.ri wrote:

The main changes are in MCInstrDesc.h and InstrInfoEmitter.cpp,
the rest of the diff is just renaming for consistency sake.

Which results in a *lot* of noise.
It would be best to further split this into the actual changes, and a follow-up "just renaming for consistency sake."

Will do, thanks!

[m4yers]

Remove noise changes

When(if?) this diff lands another will follow, renaming:

• NumOperands -> NumMCOperands
• OpInfo -> MCOpInfo

for consistency

[RKSimon]

@m4yers Abandon this now that the m68k target has landed?

include/llvm/MC/MCInstrDesc.h

 #ifndef LLVM_MC_MCINSTRDESC_H
 #define LLVM_MC_MCINSTRDESC_H
 
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/DataTypes.h"
 #include <string>
 
 namespace llvm {
-  class MCInst;
-  class MCSubtargetInfo;
-  class FeatureBitset;
 
 //===----------------------------------------------------------------------===//
 // Machine Operand Flags and Description
 //===----------------------------------------------------------------------===//
 
 namespace MCOI {
 // Operand constraints
 enum OperandConstraint {
enum OperandType {
   OPERAND_GENERIC_3 = 9,
   OPERAND_GENERIC_4 = 10,
   OPERAND_GENERIC_5 = 11,
   OPERAND_LAST_GENERIC = 11,
 
   OPERAND_FIRST_TARGET = 12,
 };
 
-}
+} // namespace MCOI
 
 /// This holds information about one operand of a machine instruction,
 /// indicating the register class for register operands, etc.
 class MCOperandInfo {
 public:
   /// This specifies the register class enumeration of the operand
   /// if the operand is a register.  If isLookupPtrRegClass is set, then this is
   /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
enum Flag {
   ExtraDefRegAllocReq,
   RegSequence,
   ExtractSubreg,
   InsertSubreg,
   Convergent,
   Add,
   Trap
 };
-}
+} // namespace MCID
+
+/// \brief Defines an operand group.
+///
+/// Many machine operands are aggregates of multiple target operands (e.g.
+/// register, immediate) and during codegen it is not always clear how many
+/// those operands to read. This type provides this information.
+class MIOperandInfo {
+public:
+  int16_t MINo;
+  int16_t Type;
+  int16_t OpsNum;
+
+  bool isTargetType() { return Type >= MCOI::OPERAND_FIRST_TARGET; };
+};
 
 /// Describe properties that are true of each instruction in the target
 /// description file.  This captures information about side effects, register
 /// use and many other things.  There is one instance of this struct for each
 /// target instruction class, and the MachineInstr class points to this struct
 /// directly to describe itself.
 class MCInstrDesc {
 public:
   unsigned short Opcode;         // The opcode number
+  unsigned short NumMIOperands;  // Num of logical operands
   unsigned short NumOperands;    // Num of args (may be more if variable_ops)
   unsigned char NumDefs;         // Num of args that are definitions
   unsigned char Size;            // Number of bytes in encoding.
   unsigned short SchedClass;     // enum identifying instr sched class
   uint64_t Flags;                // Flags identifying machine instr class
   uint64_t TSFlags;              // Target Specific Flag values
   const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
   const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
+  const MIOperandInfo *MIOpInfo; // 'NumMIOperands' entries about operands
   const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
   // Subtarget feature that this is deprecated on, if any
   // -1 implies this is not deprecated by any single feature. It may still be
   // deprecated due to a "complex" reason, below.
   int64_t DeprecatedFeature;
 
   // A complex method to determine if a certain instruction is deprecated or
   // not, and return the reason for deprecation.
public:
   /// is equivalent to a INSERT_SUBREG:
   /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
   ///
   /// Note that for the optimizers to be able to take advantage of
   /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
   /// override accordingly.
   bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
 
-
   /// Return true if this instruction is convergent.
   ///
   /// Convergent instructions may not be made control-dependent on any
   /// additional values.
   bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
 
   //===--------------------------------------------------------------------===//
   // Side Effect Analysis

utils/TableGen/InstrInfoEmitter.cpp

private:
   void emitTIIHelperMethods(raw_ostream &OS, StringRef TargetName);
 
   /// Expand TIIPredicate definitions to functions that accept a const MCInst
   /// reference.
   void emitMCIIHelperMethods(raw_ostream &OS, StringRef TargetName);
   void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                   Record *InstrInfo,
                   std::map<std::vector<Record*>, unsigned> &EL,
-                  const OperandInfoMapTy &OpInfo,
+                  const OperandInfoMapTy &MIOpInfo,
+                  const OperandInfoMapTy &MCOpInfo,
                   raw_ostream &OS);
   void emitOperandTypesEnum(raw_ostream &OS, const CodeGenTarget &Target);
   void initOperandMapData(
             ArrayRef<const CodeGenInstruction *> NumberedInstructions,
             StringRef Namespace,
             std::map<std::string, unsigned> &Operands,
             OpNameMapTy &OperandMap);
   void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target,
             ArrayRef<const CodeGenInstruction*> NumberedInstructions);
 
   // Operand information.
-  void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
-  std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
+  void EmitMIOperandInfo(raw_ostream &OS, OperandInfoMapTy &MCOperandInfoIDs);
+  std::vector<std::string> GetMIOperandInfo(const CodeGenTarget &Target,
+                                            const CodeGenInstruction &Inst);
+
+  void EmitMCOperandInfo(raw_ostream &OS, OperandInfoMapTy &MCOperandInfoIDs);
+  std::vector<std::string> GetMCOperandInfo(const CodeGenInstruction &Inst);
 };
 
 } // end anonymous namespace
 
 static void PrintDefList(const std::vector<Record*> &Uses,
                          unsigned Num, raw_ostream &OS) {
   OS << "static const MCPhysReg ImplicitList" << Num << "[] = { ";
   for (Record *U : Uses)
     OS << getQualifiedName(U) << ", ";
   OS << "0 };\n";
 }
 
 //===----------------------------------------------------------------------===//
 // Operand Info Emission.
 //===----------------------------------------------------------------------===//
 
 std::vector<std::string>
-InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
+InstrInfoEmitter::GetMIOperandInfo(const CodeGenTarget &Target,
+                                   const CodeGenInstruction &Inst) {
+
+  std::vector<std::string> Result;
+
+  const std::string &Namespace = Target.getInstNamespace();
+
+  for (auto &Op : Inst.Operands) {
+
+    // One record
+    std::string Res;
+
+    // This might be a multiple operand thing.  Targets like X86 have
+    // registers in their multi-operand operands.  It may also be an anonymous
+    // operand, which has a single operand, but no declared class for the
+    // operand.
+    DagInit *MIOI = Op.MIOperandInfo;
+
+    if (!MIOI || MIOI->getNumArgs() == 0) {
+      Res = std::to_string(Op.MIOperandNo) + ", " + Op.OperandType + ", 1";
+    } else {
+      Res = std::to_string(Op.MIOperandNo) + ", " + Namespace +
+            "::MIOpTypes::" + Op.Rec->getName().str() + ", " +
+            std::to_string(Op.MINumOperands);
+    }
+
+    Result.push_back(Res);
+  }
+
+  return Result;
+}
+
+void InstrInfoEmitter::EmitMIOperandInfo(raw_ostream &OS,
+                                         OperandInfoMapTy &MIOperandInfoIDs) {
+  // ID #0 is for no operand info.
+  unsigned OperandListNum = 0;
+  MIOperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
+
+  OS << "\n";
+  const CodeGenTarget &Target = CDP.getTargetInfo();
+  for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
+    std::vector<std::string> OperandInfo = GetMIOperandInfo(Target, *Inst);
+    unsigned &N = MIOperandInfoIDs[OperandInfo];
+    if (N != 0)
+      continue;
+
+    N = ++OperandListNum;
+    OS << "static const MIOperandInfo MIOperandInfo" << N << "[] = { ";
+    for (const std::string &Info : OperandInfo)
+      OS << "{ " << Info << " }, ";
+    OS << "};\n";
+  }
+}
+
+std::vector<std::string>
+InstrInfoEmitter::GetMCOperandInfo(const CodeGenInstruction &Inst) {
   std::vector<std::string> Result;
 
   for (auto &Op : Inst.Operands) {
     // Handle aggregate operands and normal operands the same way by expanding
     // either case into a list of operands for this op.
     std::vector<CGIOperandList::OperandInfo> OperandList;
 
     // This might be a multiple operand thing.  Targets like X86 have
for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
 
       Result.push_back(Res);
     }
   }
 
   return Result;
 }
 
-void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
-                                       OperandInfoMapTy &OperandInfoIDs) {
+void InstrInfoEmitter::EmitMCOperandInfo(raw_ostream &OS,
+                                         OperandInfoMapTy &MCOperandInfoIDs) {
   // ID #0 is for no operand info.
   unsigned OperandListNum = 0;
-  OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
+  MCOperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
 
   OS << "\n";
   const CodeGenTarget &Target = CDP.getTargetInfo();
   for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
-    std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
-    unsigned &N = OperandInfoIDs[OperandInfo];
+    std::vector<std::string> OperandInfo = GetMCOperandInfo(*Inst);
+    unsigned &N = MCOperandInfoIDs[OperandInfo];
     if (N != 0) continue;
 
     N = ++OperandListNum;
-    OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
+    OS << "static const MCOperandInfo MCOperandInfo" << N << "[] = { ";
     for (const std::string &Info : OperandInfo)
       OS << "{ " << Info << " }, ";
     OS << "};\n";
   }
 }
 
 /// Initialize data structures for generating operand name mappings.
-/// 
+///
 /// \param Operands [out] A map used to generate the OpName enum with operand
 ///        names as its keys and operand enum values as its values.
 /// \param OperandMap [out] A map for representing the operand name mappings for
 ///        each instructions.  This is used to generate the OperandMap table as
 ///        well as the getNamedOperandIdx() function.
 void InstrInfoEmitter::initOperandMapData(
         ArrayRef<const CodeGenInstruction *> NumberedInstructions,
         StringRef Namespace,

 /// llvm::TargetNamespace::OpTypes namespace.
 /// Operand types are all definitions derived of the Operand Target.td class.
 void InstrInfoEmitter::emitOperandTypesEnum(raw_ostream &OS,
                                             const CodeGenTarget &Target) {
 
   StringRef Namespace = Target.getInstNamespace();
   std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
 
-  OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
-  OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
-  OS << "namespace llvm {\n";
   OS << "namespace " << Namespace << " {\n";
-  OS << "namespace OpTypes {\n";
-  OS << "enum OperandType {\n";
+  OS << "namespace MIOpTypes {\n";
+  OS << "enum MIOperandType {\n";
 
-  unsigned EnumVal = 0;
+  bool First = true;
   for (const Record *Op : Operands) {
-    if (!Op->isAnonymous())
-      OS << "  " << Op->getName() << " = " << EnumVal << ",\n";
-    ++EnumVal;
+    OS << "  " << Op->getName();
+    if (First) {
+      OS << " = llvm::MCOI::OPERAND_FIRST_TARGET";
+      First = false;
+    }
+    OS << ",\n";
   }
 
   OS << "  OPERAND_TYPE_LIST_END" << "\n};\n";
   OS << "} // end namespace OpTypes\n";
   OS << "} // end namespace " << Namespace << "\n";
-  OS << "} // end namespace llvm\n";
-  OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n\n";
 }
 
 void InstrInfoEmitter::emitMCIIHelperMethods(raw_ostream &OS,
                                              StringRef TargetName) {
   RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
   if (TIIPredicates.empty())
     return;
 

 // Main Output.
 //===----------------------------------------------------------------------===//
 
 // run - Emit the main instruction description records for the target...
 void InstrInfoEmitter::run(raw_ostream &OS) {
   emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS);
   emitEnums(OS);
 
+  // Get the MI types separately from data
+  OS << "#ifdef GET_INSTRINFO_MI_OPS_INFO\n";
+  OS << "#undef GET_INSTRINFO_MI_OPS_INFO\n";
+  OS << "namespace llvm {\n\n";
+
+  emitOperandTypesEnum(OS, CDP.getTargetInfo());
+
+  OS << "} // end llvm namespace\n";
+  OS << "#endif // GET_INSTRINFO_MI_OPS_INFO\n\n";
+
   OS << "#ifdef GET_INSTRINFO_MC_DESC\n";
   OS << "#undef GET_INSTRINFO_MC_DESC\n";
 
   OS << "namespace llvm {\n\n";
 
+  emitOperandTypesEnum(OS, CDP.getTargetInfo());
+
   CodeGenTarget &Target = CDP.getTargetInfo();
   const std::string &TargetName = Target.getName();
   Record *InstrInfo = Target.getInstructionSet();
 
   // Keep track of all of the def lists we have emitted already.
   std::map<std::vector<Record*>, unsigned> EmittedLists;
   unsigned ListNumber = 0;
 
   // Emit all of the instruction's implicit uses and defs.
   for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
     Record *Inst = II->TheDef;
     std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
     if (!Uses.empty()) {
       unsigned &IL = EmittedLists[Uses];
       if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
     }
     std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
     if (!Defs.empty()) {
       unsigned &IL = EmittedLists[Defs];
       if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
     }
   }
 
-  OperandInfoMapTy OperandInfoIDs;
+  OperandInfoMapTy MIOperandInfoIDs;
+  OperandInfoMapTy MCOperandInfoIDs;
 
   // Emit all of the operand info records.
-  EmitOperandInfo(OS, OperandInfoIDs);
+  EmitMIOperandInfo(OS, MIOperandInfoIDs);
+  EmitMCOperandInfo(OS, MCOperandInfoIDs);
 
   // Emit all of the MCInstrDesc records in their ENUM ordering.
   //
   OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
   ArrayRef<const CodeGenInstruction*> NumberedInstructions =
     Target.getInstructionsByEnumValue();
 
   SequenceToOffsetTable<std::string> InstrNames;
   unsigned Num = 0;
   for (const CodeGenInstruction *Inst : NumberedInstructions) {
     // Keep a list of the instruction names.
     InstrNames.add(Inst->TheDef->getName());
     // Emit the record into the table.
-    emitRecord(*Inst, Num++, InstrInfo, EmittedLists, OperandInfoIDs, OS);
+    emitRecord(
+        *Inst, Num++, InstrInfo, EmittedLists,
+        MIOperandInfoIDs, MCOperandInfoIDs, OS);
   }
   OS << "};\n\n";
 
   // Emit the array of instruction names.
   InstrNames.layout();
   OS << "extern const char " << TargetName << "InstrNameData[] = {\n";
   InstrNames.emit(OS, printChar);
   OS << "};\n\n";
OS << ClassName << "::" << ClassName
      << "InstrNameIndices, " << TargetName << "InstrNameData, "
      << NumberedInstructions.size() << ");\n}\n";
   OS << "} // end llvm namespace\n";
 
   OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n";
 
   emitOperandNameMappings(OS, Target, NumberedInstructions);
 
-  emitOperandTypesEnum(OS, Target);
-
   emitMCIIHelperMethods(OS, TargetName);
 }
 
 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                                   Record *InstrInfo,
-                         std::map<std::vector<Record*>, unsigned> &EmittedLists,
-                                  const OperandInfoMapTy &OpInfo,
+                         std::map<std::vector<Record *>, unsigned> &EmittedLists,
+                                  const OperandInfoMapTy &MIOpInfo,
+                                  const OperandInfoMapTy &MCOpInfo,
                                   raw_ostream &OS) {
   int MinOperands = 0;
-  if (!Inst.Operands.empty())
+  if (!Inst.Operands.empty()) {
+
     // Each logical operand can be multiple MI operands.
     MinOperands = Inst.Operands.back().MIOperandNo +
                   Inst.Operands.back().MINumOperands;
+  }
 
   OS << "  { ";
-  OS << Num << ",\t" << MinOperands << ",\t"
+  OS << Num << ",\t"
+     << Inst.Operands.size() << ",\t"
+     << MinOperands << ",\t"
      << Inst.Operands.NumDefs << ",\t"
      << Inst.TheDef->getValueAsInt("Size") << ",\t"
      << SchedModels.getSchedClassIdx(Inst) << ",\t0";
 
   CodeGenTarget &Target = CDP.getTargetInfo();
 
   // Emit all of the target independent flags...
   if (Inst.isPseudo)           OS << "|(1ULL<<MCID::Pseudo)";
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
 
   std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
   if (DefList.empty())
     OS << "nullptr, ";
   else
     OS << "ImplicitList" << EmittedLists[DefList] << ", ";
 
   // Emit the operand info.
-  std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
-  if (OperandInfo.empty())
+  std::vector<std::string> MIOperandInfo =
+      GetMIOperandInfo(CDP.getTargetInfo(), Inst);
+  if (MIOperandInfo.empty())
+    OS << "nullptr";
+  else
+    OS << "MIOperandInfo" << MIOpInfo.find(MIOperandInfo)->second;
+  OS << ", ";
+
+  std::vector<std::string> MCOperandInfo = GetMCOperandInfo(Inst);
+  if (MCOperandInfo.empty())
     OS << "nullptr";
   else
-    OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
+    OS << "MCOperandInfo" << MCOpInfo.find(MCOperandInfo)->second;
 
   if (Inst.HasComplexDeprecationPredicate)
     // Emit a function pointer to the complex predicate method.
     OS << ", -1 "
        << ",&get" << Inst.DeprecatedReason << "DeprecationInfo";
   else if (!Inst.DeprecatedReason.empty())
     // Emit the Subtarget feature.
     OS << ", " << Target.getInstNamespace() << "::" << Inst.DeprecatedReason