[GISel]: Add Opcodes for a few Libm Intrinsics

[aditya_nandakumar]

Summary

Add opcodes for llvm.intrinsic.trunc and round (only a couple for now). Opting for a verbose name with LIBM prefix for clarity.

[aemerson]

I'm a little uneasy about specifying libm in the names of the intrinsics. The langref mentions libm in the description, but the semantics don't exactly match due to ignoring errno. That said, I don't really have a suggestion for a better name, so the only thing I can ask is that we make it a bit more explicit in the documentation what we mean by "LIBM" here.

include/llvm/Target/GenericOpcodes.td

516

Perhaps say "LIBM compatible intrinsics"

[arsenm]

include/llvm/Support/TargetOpcodes.def

271–272

LIBM should definitely be removed from the names

[aditya_nandakumar]

include/llvm/Target/GenericOpcodes.td

516

Would you name it G_FTRUNC? I thought that is very similar to G_FPTRUNC and might lead to confusion. One other name I can think of is G_INTRINSIC_TRUNC which makes it explicit that this is the intrinsic equivalent in llvm IR.

[arsenm]

include/llvm/Target/GenericOpcodes.td

516

Yes

[aditya_nandakumar]

Changed the name based on feedback.

[aemerson]

include/llvm/Target/GenericOpcodes.td

516

Matt can you clarify which of those two suggestions you meant? Aditya named the intrinsics G_INTRINSIC_TRUNC but did you mean we should name them G_FTRUNC?

[dsanders]

This LGTM. I'm ok with the G_INTRINSIC_TRUNC spelling for the trunc() intrinsic but we should reach an agreement on it before committing.

include/llvm/Target/GenericOpcodes.td

516

FWIW, I think we should make it clear in the name that it's the operation performed by trunc() (which isn't a type conversion) and not the type conversion operation performed by fptrunc from LLVM-IR.

test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

1412

If we're dropping libm elsewhere we should probably drop it here too

1422

Likewise

[aditya_nandakumar]

test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

1422

Thanks Daniel. I missed that with my search and replace. I've updated and I'll push.

[aditya_nandakumar]

Pushed in r339977

include/llvm/Support/TargetOpcodes.def

 
 /// Generic int to pointer conversion.
 HANDLE_TARGET_OPCODE(G_INTTOPTR)
 
 /// Generic bitcast. The source and destination types must be different, or a
 /// COPY is the relevant instruction.
 HANDLE_TARGET_OPCODE(G_BITCAST)
 
+/// INTRINSIC trunc intrinsic.
+HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC)
+
+/// INTRINSIC round intrinsic.
+HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND)
+
 /// Generic load (including anyext load)
 HANDLE_TARGET_OPCODE(G_LOAD)
 
 /// Generic signext load
 HANDLE_TARGET_OPCODE(G_SEXTLOAD)
 
 /// Generic zeroext load
 HANDLE_TARGET_OPCODE(G_ZEXTLOAD)

include/llvm/Target/GenericOpcodes.td

 // Floating point base-2 logarithm of a value.
 def G_FLOG2 : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src1);
   let hasSideEffects = 0;
 }
 
 //------------------------------------------------------------------------------
+// Opcodes for LLVM Intrinsics
+//------------------------------------------------------------------------------
+def G_INTRINSIC_TRUNC : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1);
+  let hasSideEffects = 0;
+}
+
+def G_INTRINSIC_ROUND : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1);
+  let hasSideEffects = 0;
+}
+
+//------------------------------------------------------------------------------
 // Memory ops
 //------------------------------------------------------------------------------
 
 // Generic load. Expects a MachineMemOperand in addition to explicit operands.
 def G_LOAD : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins ptype1:$addr);
   let hasSideEffects = 0;

lib/CodeGen/GlobalISel/IRTranslator.cpp

MIRBuilder.buildInstr(TargetOpcode::G_FLOG2)
         .addDef(getOrCreateVReg(CI))
         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
     return true;
   case Intrinsic::fabs:
     MIRBuilder.buildInstr(TargetOpcode::G_FABS)
         .addDef(getOrCreateVReg(CI))
         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
     return true;
+  case Intrinsic::trunc:
+    MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC)
+        .addDef(getOrCreateVReg(CI))
+        .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
+    return true;
+  case Intrinsic::round:
+    MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_ROUND)
+        .addDef(getOrCreateVReg(CI))
+        .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
+    return true;
   case Intrinsic::fma:
     MIRBuilder.buildInstr(TargetOpcode::G_FMA)
         .addDef(getOrCreateVReg(CI))
         .addUse(getOrCreateVReg(*CI.getArgOperand(0)))
         .addUse(getOrCreateVReg(*CI.getArgOperand(1)))
         .addUse(getOrCreateVReg(*CI.getArgOperand(2)));
     return true;
   case Intrinsic::fmuladd: {

test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

 ; CHECK-LABEL: name: test_fabs_intrin
 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FABS [[A]]
 ; CHECK: $s0 = COPY [[RES]]
   %res = call float @llvm.fabs.f32(float %a)
   ret float %res
 }
 
+declare float @llvm.trunc.f32(float)
+define float @test_libm_trunc(float %a) {
+; CHECK-LABEL: name: test_libm_trunc
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[A]]
+; CHECK: $s0 = COPY [[RES]]
+  %res = call float @llvm.trunc.f32(float %a)
+  ret float %res
+}
+
+declare float @llvm.round.f32(float)
+define float @test_libm_round(float %a) {
+; CHECK-LABEL: name: test_libm_round
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[A]]
+; CHECK: $s0 = COPY [[RES]]
+  %res = call float @llvm.round.f32(float %a)
+  ret float %res
+}
+
 declare i32 @llvm.ctlz.i32(i32, i1)
 define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) {
 ; CHECK-LABEL: name: test_ctlz_intrinsic_zero_not_undef
 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w0
 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_CTLZ [[A]]
 ; CHECK: $w0 = COPY [[RES]]
   %res = call i32 @llvm.ctlz.i32(i32 %a, i1 0)
   ret i32 %res