[llvm-exegesis] Proposal to add Exegesis Configuration to td files.

[gchatelet]

Summary

This patch is not to be submitted as is. I'd like to get some input first, but starting with some code will help.
Some instruction's latency depend on the value of its operands (e.g. DIV with NaN or subnormal takes longer to execute than normal numbers).
For llvm-exegesis to explore the latency space of the instructions it needs some special knowledge of the instruction.
I envision that the best place to store this knowledge is the td file.

Let's take the following div example, by choosing special starting values we can make sure that even with 100000 iterations divss will always stay in the normal range.

movss xmm0, 0x3F800000 1.0f
movss xmm1, 0x3F800001 1.0f + 1ulp
.rept 100000
divss xmm0, xmm1
.endr

So an exegesis configuration for divss would be (1.0f, 1.0f + ulp),
Another could be (1.0f, 0.0f) to test infinity generation,
Another could be (NaN, Inf) to test the impact of NaNs...

The configuration should allow to specify the bit precise values and to pack them in case of vector instructions.

This configuration should work for all floating point types (including X87) and for as many arithmetic operations as possible (div, mul, sqrt, ...).

It can be part of the Instruction Records or separated as it is in this Patch.

Addendum

I started a document to gather the different strategies (feel free to comment).
From this it becomes clear that we only need to annotate an Instruction with its semantic, llvm-exegesis would then run strategies depending on the semantic and the type of the arguments (floating point precision, packed/scalar).

I'll update the code with a simpler proposal.

[gchatelet]

• remove unrelated files

[gchatelet]

• remove unrelated files

[gchatelet]

• Added documentation

[gchatelet]

• Simpler version with only the semantic of the instruction.

[gchatelet]

I'm not sure this version will scale, we need to spell out all the instructions we want to support...
The nice thing is that it's pretty orthogonal to the rest of the td files.

Any suggestions?

[RKSimon]

In D50061#1184206, @gchatelet wrote:

I'm not sure this version will scale, we need to spell out all the instructions we want to support...
The nice thing is that it's pretty orthogonal to the rest of the td files.

Any suggestions?

I'm worried about the scalability of this as well - how much can you achieve just be using the domain of the instruction?

[gchatelet]

In D50061#1185808, @RKSimon wrote:

I'm worried about the scalability of this as well - how much can you achieve just be using the domain of the instruction?

By domain you mean register classes of the operands?
If so then not much, DIVPDrr for instance has the following in operands

dag InOperandList = (ins VR128:$src1, VR128:$src2);

VR128 does not tell how many values are packed nor if they are half, float, double or integer values.
Sure you can infer it from the name of the instruction but it's not going to scale to other architectures.

For llvm-exegesis to do a good job we need to add some semantic to the instruction description.

[RKSimon]

I meant the X86 execution domain info:

X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {

uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;

[gchatelet]

In D50061#1187159, @RKSimon wrote:

I meant the X86 execution domain info:

X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {

uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;

Ha I see, well it's very specific to X86 and would not work for other architectures.
Also it still doesn't tell much about the semantic of the instruction which is needed to come up with good testing strategies.

Ultimately I'd like llvm-exegesis to explore instructions and report the ones with varied execution time. Two use cases for this:

• Timing attacks identification,
• Arithmetic performance: floating point operations on subnormal / Inf / NaN may be slower than with normal float. For instance, llvm-exegesis currently reports unrealistic latencies for division (VDIVPDrr is 172 cycles on Skylake)

include/llvm/Target/Target.td

 // Pull in the common support for DAG isel generation.
 //
 include "llvm/Target/GlobalISel/Target.td"
 
 //===----------------------------------------------------------------------===//
 // Pull in the common support for the Global ISel DAG-based selector generation.
 //
 include "llvm/Target/GlobalISel/SelectionDAGCompat.td"
+
+//===----------------------------------------------------------------------===//
+// Pull in the common support for exegesis.
+//
+include "llvm/Target/TargetExegesis.td"

include/llvm/Target/TargetExegesis.td

+//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+class OperandValue;
+
+class ExegesisConfiguration {
+  Instruction Instruction = ?;
+  list<OperandValue> OperandValues;
+}
+
+class ScalarValue : OperandValue;
+
+class PackedValue : OperandValue {
+  ScalarValue       BroadcastValue;
+}
+
+// Floating Point description
+
+class Ieee754Precision;
+def HalfPrecision   : Ieee754Precision;
+def SinglePrecision : Ieee754Precision;
+def DoublePrecision : Ieee754Precision;
+def X87Precision    : Ieee754Precision;
+
+class RawExponentValue;
+def RawExponentZero  : RawExponentValue;
+def RawExponentMax   : RawExponentValue;
+def RawExponentBias  : RawExponentValue;
+
+class MantissaValue;
+def MantissaZero : MantissaValue;
+def MantissaOne  : MantissaValue;
+def MantissaMax  : MantissaValue;
+
+class Ieee754 : ScalarValue {
+  Ieee754Precision  Precision;
+  bit               Sign;
+  RawExponentValue  Exponent;
+  MantissaValue     Mantissa;
+}
+
+// Integer Description.
+
+class Integer : ScalarValue {
+  list<bit> Bits;
+}

lib/Target/X86/X86.td

def X86 : Target {
   let AllowRegisterRenaming = 1;
 }
 
 //===----------------------------------------------------------------------===//
 // Pfm Counters
 //===----------------------------------------------------------------------===//
 
 include "X86PfmCounters.td"
+
+//===----------------------------------------------------------------------===//
+// Exegesis Configurations
+//===----------------------------------------------------------------------===//
+
+include "X86ExegesisConfigurations.td"

lib/Target/X86/X86ExegesisConfigurations.td

+def One : Ieee754 {
+  let Precision = SinglePrecision;
+  let Sign = 0;
+  let Exponent = RawExponentBias;
+  let Mantissa = MantissaZero;
+}
+
+def OnePlusEpsilon : Ieee754 {
+  let Precision = SinglePrecision;
+  let Sign = 0;
+  let Exponent = RawExponentBias;
+  let Mantissa = MantissaOne;
+}
+
+def PackedOnes : PackedValue {
+  let BroadcastValue = One;
+}
+
+def PackedOnePlusEpsilons : PackedValue {
+  let BroadcastValue = OnePlusEpsilon;
+}
+
+let Instruction = VDIVPDrr in {
+  def VDIVPDrrExegesisConfiguration : ExegesisConfiguration {
+    let OperandValues = [PackedOnes, PackedOnePlusEpsilons];
+  }
+}

utils/TableGen/InstrSemInfoEmitter.cpp

+
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
+
+using namespace llvm;
+
+namespace {
+
+class InstrInfoSemEmitter {
+  RecordKeeper &Records;
+
+public:
+  InstrInfoSemEmitter(RecordKeeper &R) : Records(R) {}
+
+  void run(raw_ostream &OS);
+};
+
+void InstrInfoSemEmitter::run(raw_ostream &OS) {
+  { // FPI
+    Record *Class = Records.getClass("FPI");
+    assert(Class);
+    OS << "#FPI\n";
+    for (const auto &D : Records.getDefs())
+      if (D.second->isSubClassOf(Class))
+        OS << D.second->getName() << "\n";
+  }
+  { // PD
+    Record *Class = Records.getClass("PD");
+    assert(Class);
+    OS << "#PD\n";
+    for (const auto &D : Records.getDefs())
+      if (D.second->isSubClassOf(Class))
+        OS << D.second->getName() << "\n";
+  }
+  { // PS
+    Record *Class = Records.getClass("PS");
+    assert(Class);
+    OS << "#PS\n";
+    for (const auto &D : Records.getDefs())
+      if (D.second->isSubClassOf(Class))
+        OS << D.second->getName() << "\n";
+  }
+}
+
+} // end namespace
+
+namespace llvm {
+
+void EmitInstrSemInfo(RecordKeeper &RK, raw_ostream &OS) {
+  InstrInfoSemEmitter(RK).run(OS);
+}
+
+} // namespace llvm
+
+// 0b 0 01111100 01000000000000000000000