[PowerPC] Emit xscpsgndp instead of xxlor when copying floating point scalar registers for P9

[amyk]

Summary

This patch will address using the xscpsgndp instruction to copy floating point scalar registers instead of the xxlor (specifically XXLORf) instruction that is currently used. Additionally, this patch of utilizing xscpsgndp will apply to P9, while pre-P9 will still use xxlor.

This patch includes:

• The change in instruction opcode to utilize xscpsgndp instead of xxlor when copying the floating point scalar registers on P9
• An update of test cases to reflect this behaviour (specifically for P9), while still using xxlor pre-P9
• An update to test cases to include the -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names llc options

[inouehrs]

XSCPSGNDP has longer latency (6 cycles) than XXLOR (2 cycles) on POWER8 while it has higher throughput with the same latency on POWER9. So XXLOR is preferable for pre-P9.

Also, the two instructions have different behavior for a denormal input value in my understanding; XSCPSGNDP does normalization but XXLOR does not. Does this difference matter?

[jedilyn]

In D50004#1182972, @inouehrs wrote:

XSCPSGNDP has longer latency (6 cycles) than XXLOR (2 cycles) on POWER8 while it has higher throughput with the same latency on POWER9. So XXLOR is preferable for pre-P9.

Also, the two instructions have different behavior for a denormal input value in my understanding; XSCPSGNDP does normalization but XXLOR does not. Does this difference matter?

+1, even for Power9 XSCPSGNDP makes pipeline busy longer than XXLOR, XXLOR is still better.

[nemanjai]

+1, even for Power9 XSCPSGNDP makes pipeline busy longer than XXLOR, XXLOR is still better.

Can you clarify this please? Where is this information coming from? According to the UM, XXLOR takes up a whole superslice whereas XSCPSGNDP takes up a single slice so we can dispatch 2 of the former per cycle and 4 of the latter. And the "Pipe Busy Cycles" field for both is 1.

[nemanjai]

In D50004#1182972, @inouehrs wrote:

XSCPSGNDP has longer latency (6 cycles) than XXLOR (2 cycles) on POWER8 while it has higher throughput with the same latency on POWER9. So XXLOR is preferable for pre-P9.

Also, the two instructions have different behavior for a denormal input value in my understanding; XSCPSGNDP does normalization but XXLOR does not. Does this difference matter?

Yes, I agree that we should limit this to Power9. Does the comment about normalization only pertain to ISA 2.07? The text from ISA 3.0 is:

Bit 0 of VSR[XT] is set to the contents of bit 0 of VSR[XA].
Bits 1:63 of VSR[XT] are set to the contents of bits 1:63 of VSR[XB].
The contents of doubleword element 1 of VSR[XT] are undefined.

There is no mention of normalization.

[inouehrs]

Does the comment about normalization only pertain to ISA 2.07?

As I browse the document, neither ISA 2.07 nor 3.0 mention about normalization by xscpsgndp.
P8 UM says xscpsgndp, xvcpsgndp and fmr are normalizing instruction. P9 UM say nothing.
Since fmr is also a normalizing instruction, I feel it is acceptable to use xscpsgndp for coping register.

[jedilyn]

In D50004#1185697, @nemanjai wrote:

+1, even for Power9 XSCPSGNDP makes pipeline busy longer than XXLOR, XXLOR is still better.

Can you clarify this please? Where is this information coming from? According to the UM, XXLOR takes up a whole superslice whereas XSCPSGNDP takes up a single slice so we can dispatch 2 of the former per cycle and 4 of the latter. And the "Pipe Busy Cycles" field for both is 1.

My fault, sorry, I saw the data from the wrong column "max ops per cycle". You are right, both are 1 cycle for busy pipe, XSCPSGNDP should outperform on Power9 then.

[amyk]

This revision primarily addresses enabling xscpsgndp for P9 only, as xxlor is still preferable to use for copying floating point scalars pre-P9.

[jsji]

In D50004#1185846, @inouehrs wrote:

Does the comment about normalization only pertain to ISA 2.07?

As I browse the document, neither ISA 2.07 nor 3.0 mention about normalization by xscpsgndp.
P8 UM says xscpsgndp, xvcpsgndp and fmr are normalizing instruction. P9 UM say nothing.
Since fmr is also a normalizing instruction, I feel it is acceptable to use xscpsgndp for coping register.

P9 UM does clarify the difference:

4.3.6 Handling of Denormal Single-Precision Values in Double-Precision Format
Unlike previous generation processors, such as the POWER8 processor, the POWER9 processor is capable of handling denormal single-precision values as inputs for all subsequent instructions. Whereas, in some cases, the POWER8 processor takes a soft-patch interrupt to allow the interrupt handler to reformat the input operands to a double-precision format and then re-execute the instruction, the POWER9 processor simply executes normally regardless of how that number was produced.

[jsji]

In D50004#1187230, @amyk wrote:

This revision primarily addresses enabling xscpsgndp for P9 only, as xxlor is still preferable to use for copying floating point scalars pre-P9.

No sure how much this will have impact, but maybe we need to consider still using xxlor for destructive instructions?

eg:
In Power ISA 3.0 B, 2.1.5 Destructive Operation Operand Preservation
"The set of instructions listed below, when immediately preceded by the xxlor XT,XC,XC instruction in a sequence similar to the above example, will provide optimal performance."

[nemanjai]

In D50004#1187625, @jsji wrote:

<snip>

No sure how much this will have impact, but maybe we need to consider still using xxlor for destructive instructions?

eg:
In Power ISA 3.0 B, 2.1.5 Destructive Operation Operand Preservation
"The set of instructions listed below, when immediately preceded by the xxlor XT,XC,XC instruction in a sequence similar to the above example, will provide optimal performance."

I don't think there are any conditions under which we will emit an xxlor that will be eligible for this. That may be a good candidate to peephole and/or fuse together.
Example:

vector double test(double a, vector double b, vector double c, vector double *s) {
  vector double n = (vector double)a;
  *s = n + c * b;
  return n;
}

Is about as close as you can get, but will produce the following on Power9:

xxspltd vs0, vs1, 0
xxlor vs1, vs0, vs0
xvmaddadp vs1, vs35, vs34
xxlor vs34, vs0, vs0
stxv vs1, 0(r9)

Ultimately, the target of the copy will always be used as an input to the destructive operation. If we want to exploit this optimization in the HW, we'd have to forward the source of the copy (and eliminate the second copy in this case as well). But if we're consciously transforming the code to exploit this, the instruction we use for the COPY is immaterial (we can always transform it to XXLOR at the time).

[jsji]

In D50004#1192390, @nemanjai wrote:

In D50004#1187625, @jsji wrote:

<snip>

No sure how much this will have impact, but maybe we need to consider still using xxlor for destructive instructions?

eg:
In Power ISA 3.0 B, 2.1.5 Destructive Operation Operand Preservation
"The set of instructions listed below, when immediately preceded by the xxlor XT,XC,XC instruction in a sequence similar to the above example, will provide optimal performance."

I don't think there are any conditions under which we will emit an xxlor that will be eligible for this. That may be a good candidate to peephole and/or fuse together.
Example:

vector double test(double a, vector double b, vector double c, vector double *s) {
  vector double n = (vector double)a;
  *s = n + c * b;
  return n;
}

Is about as close as you can get, but will produce the following on Power9:

xxspltd vs0, vs1, 0
xxlor vs1, vs0, vs0
xvmaddadp vs1, vs35, vs34
xxlor vs34, vs0, vs0
stxv vs1, 0(r9)

Ultimately, the target of the copy will always be used as an input to the destructive operation. If we want to exploit this optimization in the HW, we'd have to forward the source of the copy (and eliminate the second copy in this case as well). But if we're consciously transforming the code to exploit this, the instruction we use for the COPY is immaterial (we can always transform it to XXLOR at the time).

FYI.

An ugly example to show that the there are situations that this change will have impact to destructive operations.

$ cat t1.c

double test(double n0, double n1, double n2, double n3, double n4, double n5, double n6, double n7, double n8, double n9,
double n10, double n11, double n12, double n13, double n14, double n15, double n16, double n17, double n18, double n19,
double n20, double n21, double n22, double n23, double n24, double n25, double n26, double n27, double n28, double n29,
double n30, double n31, double n32, double n33,
 double c, double b, double *s) {
  *s = n0 + c * b;
  *s += n1 + *s * b;
  *s += n2 + *s * b;
  *s += n3 + *s * b;
  *s += n4 + *s * b;
  *s += n5+ *s * b;
  *s += n6+ *s * b;
  *s += n7+ *s * b;
  *s += n8+ *s * b;
  *s += n9+ *s * b;
  *s += n10 + *s * b;
  *s += n11 + *s * b;
  *s += n12 + *s * b;
  *s += n13 + *s * b;
  *s += n14 + *s * b;
  *s += n15+ *s * b;
  *s += n16+ *s * b;
  *s += n17+ *s * b;
  *s += n18+ *s * b;
  *s += n19+ *s * b;
  *s += n20 + *s * b;
  *s += n21 + *s * b;
  *s += n22 + *s * b;
  *s += n23 + *s * b;
  *s += n24 + *s * b;
  *s += n25+ *s * b;
  *s += n26+ *s * b;
  *s += n27+ *s * b;
  *s += n28+ *s * b;
  *s += n29+ *s * b;
  *s += n30 + *s * b;
  *s += n31 + *s * b;
  *s += n32 + *s * b;
  *s += n33 + *s * b;
  return n0;
}

clang -S -mcpu=pwr9 -O2 -ffast-math t1.c -mllvm -ppc-vsr-nums-as-vr -mllvm -ppc-asm-full-reg-names -mllvm -enable-post-misched=false

diff of assembly before change and after change:

$ diff -Naur before.s after.s 
--- before.s    2018-08-09 13:52:24.785246846 -0400
+++ after.s     2018-08-09 13:59:38.815493708 -0400
@@ -9,7 +9,7 @@
 # %bb.0:                                # %entry
        lfd f0, 304(r1)
        lxsd v2, 312(r1)
-       xxlor v3, f1, f1
+      xscpsgndp v3, f1, f1
        xsmaddadp v3, v2, f0
        xsadddp f0, v3, f2
        xsmaddadp f0, v3, v2

[nemanjai]

In D50004#1194086, @jsji wrote:

<snip>

diff of assembly before change and after change:

$ diff -Naur before.s after.s 
--- before.s    2018-08-09 13:52:24.785246846 -0400
+++ after.s     2018-08-09 13:59:38.815493708 -0400
@@ -9,7 +9,7 @@
 # %bb.0:                                # %entry
        lfd f0, 304(r1)
        lxsd v2, 312(r1)
-       xxlor v3, f1, f1
+      xscpsgndp v3, f1, f1
        xsmaddadp v3, v2, f0
        xsadddp f0, v3, f2
        xsmaddadp f0, v3, v2

This is exactly what I was referring to... The situation you describe is not analogous to the situation described in the ISA. According to the ISA, the sequence that will be optimized is:

xxlor XC, XT, XT
xxperm XT, XA, XB

So in this case, the only way we would get the optimized behaviour would be if the "pre-patch" code sequence was:

xxlor v3, f1, f1
xsmaddadp f1, v2, f0

And I'm fairly certain that without source forwarding of the copy, we can never produce such code (but of course, I could be wrong).

[jsji]

In D50004#1195184, @nemanjai wrote:

In D50004#1194086, @jsji wrote:

<snip>

This is exactly what I was referring to... The situation you describe is not analogous to the situation described in the ISA. According to the ISA, the sequence that will be optimized is:

xxlor XC, XT, XT
xxperm XT, XA, XB

So in this case, the only way we would get the optimized behaviour would be if the "pre-patch" code sequence was:

xxlor v3, f1, f1
xsmaddadp f1, v2, f0

And I'm fairly certain that without source forwarding of the copy, we can never produce such code (but of course, I could be wrong).

??? Can you please double check what ISA are you referring to?

The description in PowerISA_public.v3.0B https://ibm.ent.box.com/s/1hzcwkwf8rbju5h9iyf44wm94amnlcrv is:

As an example, to preserve the XT source register in the xxperm instruction, the following sequence will optimize performance.

xxlor XT,XC,XC /* Copy (XC) to XT
xxperm XT,XA,XB /* Permute, overwriting XT

The set of instructions listed below, when immediately preceded by the xxlor XT,XC,XC instruction in a sequence similar to the above example, will provide optimal performance.

This should be exact the same pattern as in my example: xxlor XT,XC,XC to Copy (XC) to XT, not xxlor XC,XT,XT in your description.

[nemanjai]

In D50004#1195212, @jsji wrote:

??? Can you please double check what ISA are you referring to?

ISA 3.0

The description in PowerISA_public.v3.0B https://ibm.ent.box.com/s/1hzcwkwf8rbju5h9iyf44wm94amnlcrv is:

As an example, to preserve the XT source register in the xxperm instruction, the following sequence will optimize performance.

xxlor XT,XC,XC /* Copy (XC) to XT
xxperm XT,XA,XB /* Permute, overwriting XT

The set of instructions listed below, when immediately preceded by the xxlor XT,XC,XC instruction in a sequence similar to the above example, will provide optimal performance.

This should be exact the same pattern as in my example: xxlor XT,XC,XC to Copy (XC) to XT, not xxlor XC,XT,XT in your description.

It would appear that the version of the document I have has a bug in it (I had ISA 3.0 - without the B). Yes, I agree that the description in the corrected ISA document matches both of the provided examples.
However, I don't think this should preclude this patch. Register/register copies are far more common than destructive operations so we should emit the best instruction for the copy. As a follow-up, we should detect copies that are inputs to destructive operations and emit the XXLOR for those.

[jsji]

In D50004#1196993, @nemanjai wrote:

It would appear that the version of the document I have has a bug in it (I had ISA 3.0 - without the B). Yes, I agree that the description in the corrected ISA document matches both of the provided examples.
However, I don't think this should preclude this patch. Register/register copies are far more common than destructive operations so we should emit the best instruction for the copy. As a follow-up, we should detect copies that are inputs to destructive operations and emit the XXLOR for those.

Yes, agree. It is OK as long as we will follow up for destructive operations. Thanks!

[nemanjai]

LGTM. Since we're all in agreement that we want to make this change for Power9, I think this is fine to go in.

[amyk]

Updated the diff to since a specific test on line 528 in vsx.ll now using the v4 register instead of vs0.

[jsji]

In D50004#1204121, @amyk wrote:

Updated the diff to since a specific test on line 528 in vsx.ll now using the v4 register instead of vs0.

Can we split the part of "An update to test cases to include the -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names llc options" into a separate patch and commit it first,
so that it would be clearer to see what is the intended change from xxlor-> xscpsgndp in all the testcases?

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
     //   2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
     //      can go to either pipeline.
     // We'll always use xxlor here, because in practically all cases where
     // copies are generated, they are close enough to some use that the
     // lower-latency form is preferable.
     Opc = PPC::XXLOR;
   else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
            PPC::VSSRCRegClass.contains(DestReg, SrcReg))
-    Opc = PPC::XXLORf;
+    Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
   else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
     Opc = PPC::QVFMR;
   else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
     Opc = PPC::QVFMRs;
   else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
     Opc = PPC::QVFMRb;
   else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
     Opc = PPC::CROR;

llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll

 declare fp128 @llvm.ppc.divf128.round.to.odd(fp128, fp128)
 
 define double @testTruncOdd(fp128 %a) {
 entry:
   %0 = call double @llvm.ppc.truncf128.round.to.odd(fp128 %a)
   ret double %0
 ; CHECK-LABEL: testTruncOdd
 ; CHECK: xscvqpdpo v2, v2
-; CHECK: xxlor f1, v2, v2
+; CHECK: xscpsgndp f1, v2, v2
 ; CHECK: blr
 }
 
 declare double @llvm.ppc.truncf128.round.to.odd(fp128)

llvm/test/CodeGen/PowerPC/f128-conv.ll

 ; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG]]
 ; CHECK-NEXT: stxv v[[CONV]], 0(r3)
 ; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @sdwConv2qp_02(fp128* nocapture %a) {
 entry:
-  %0 = load i64, i64* getelementptr inbounds 
+  %0 = load i64, i64* getelementptr inbounds
                         ([5 x i64], [5 x i64]* @mem, i64 0, i64 2), align 8
   %conv = sitofp i64 %0 to fp128
   store fp128 %conv, fp128* %a, align 16
   ret void
 
 ; CHECK-LABEL: sdwConv2qp_02
 ; CHECK: addis r[[REG:[0-9]+]], r2, .LC0@toc@ha
 ; CHECK: ld r[[REG]], .LC0@toc@l(r[[REG]])

 ; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
 ; CHECK-NEXT: stxv v[[CONV]], 0(r3)
 ; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @ubConv2qp_03(fp128* nocapture %a) {
 entry:
-  %0 = load i8, i8* getelementptr inbounds 
+  %0 = load i8, i8* getelementptr inbounds
                       ([5 x i8], [5 x i8]* @ubMem, i64 0, i64 2), align 1
   %conv = uitofp i8 %0 to fp128
   store fp128 %conv, fp128* %a, align 16
   ret void
 
 ; CHECK-LABEL: ubConv2qp_03
 ; CHECK: addis r[[REG0:[0-9]+]], r2, .LC5@toc@ha
 ; CHECK: ld r[[REG0]], .LC5@toc@l(r[[REG0]])

 @f128global = global fp128 0xL300000000000000040089CA8F5C28F5C, align 16
 
 ; Function Attrs: norecurse nounwind readonly
 define double @qpConv2dp(fp128* nocapture readonly %a) {
 ; CHECK-LABEL: qpConv2dp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
 ; CHECK-NEXT:    xscvqpdp v2, v2
-; CHECK-NEXT:    xxlor f1, v2, v2
+; CHECK-NEXT:    xscpsgndp f1, v2, v2
 ; CHECK-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %conv = fptrunc fp128 %0 to double
   ret double %conv
 }
 
 ; Function Attrs: norecurse nounwind

 }
 
 @f128Glob = common global fp128 0xL00000000000000000000000000000000, align 16
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @dpConv2qp(double %a) {
 ; CHECK-LABEL: dpConv2qp:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor v2, f1, f1
+; CHECK-NEXT:    xscpsgndp v2, f1, f1
 ; CHECK-NEXT:    xscvdpqp v2, v2
 ; CHECK-NEXT:    blr
 entry:
   %conv = fpext double %a to fp128
   ret fp128 %conv
 }
 
 ; Function Attrs: norecurse nounwind
entry:
   store fp128 %conv, fp128* @f128Glob, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind
 define void @dpConv2qp_03(fp128* nocapture %res, i32 signext %idx, double %a) {
 ; CHECK-LABEL: dpConv2qp_03:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor v2, f1, f1
+; CHECK-NEXT:    xscpsgndp v2, f1, f1
 ; CHECK-NEXT:    sldi r4, r4, 4
 ; CHECK-NEXT:    xscvdpqp v2, v2
 ; CHECK-NEXT:    stxvx v2, r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %conv = fpext double %a to fp128
   %idxprom = sext i32 %idx to i64
   %arrayidx = getelementptr inbounds fp128, fp128* %res, i64 %idxprom
   store fp128 %conv, fp128* %arrayidx, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind
 define void @dpConv2qp_04(double %a, fp128* nocapture %res) {
 ; CHECK-LABEL: dpConv2qp_04:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor v2, f1, f1
+; CHECK-NEXT:    xscpsgndp v2, f1, f1
 ; CHECK-NEXT:    xscvdpqp v2, v2
 ; CHECK-NEXT:    stxv v2, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %conv = fpext double %a to fp128
   store fp128 %conv, fp128* %res, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @spConv2qp(float %a) {
 ; CHECK-LABEL: spConv2qp:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor v2, f1, f1
+; CHECK-NEXT:    xscpsgndp v2, f1, f1
 ; CHECK-NEXT:    xscvdpqp v2, v2
 ; CHECK-NEXT:    blr
 entry:
   %conv = fpext float %a to fp128
   ret fp128 %conv
 }
 
 ; Function Attrs: norecurse nounwind
entry:
   store fp128 %conv, fp128* @f128Glob, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind
 define void @spConv2qp_03(fp128* nocapture %res, i32 signext %idx, float %a) {
 ; CHECK-LABEL: spConv2qp_03:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor v2, f1, f1
+; CHECK-NEXT:    xscpsgndp v2, f1, f1
 ; CHECK-NEXT:    sldi r4, r4, 4
 ; CHECK-NEXT:    xscvdpqp v2, v2
 ; CHECK-NEXT:    stxvx v2, r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %conv = fpext float %a to fp128
   %idxprom = sext i32 %idx to i64
   %arrayidx = getelementptr inbounds fp128, fp128* %res, i64 %idxprom
   store fp128 %conv, fp128* %arrayidx, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind
 define void @spConv2qp_04(float %a, fp128* nocapture %res) {
 ; CHECK-LABEL: spConv2qp_04:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor v2, f1, f1
+; CHECK-NEXT:    xscpsgndp v2, f1, f1
 ; CHECK-NEXT:    xscvdpqp v2, v2
 ; CHECK-NEXT:    stxv v2, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %conv = fpext float %a to fp128
   store fp128 %conv, fp128* %res, align 16
   ret void
 }

llvm/test/CodeGen/PowerPC/f128-passByValue.ll

 }
 
 ; Function Attrs: norecurse nounwind
 define fp128 @mixParam_02(fp128 %p1, double %p2, i64* nocapture %p3,
 ; CHECK-LABEL: mixParam_02:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-DAG:     lwz r3, 96(r1)
 ; CHECK:         add r4, r7, r9
-; CHECK-NEXT:    xxlor v[[REG0:[0-9]+]], f1, f1
+; CHECK-NEXT:    xscpsgndp v[[REG0:[0-9]+]], f1, f1
 ; CHECK-DAG:     add r4, r4, r10
 ; CHECK:         xscvdpqp v[[REG0]], v[[REG0]]
 ; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    std r3, 0(r6)
 ; CHECK-NEXT:    lxv v[[REG1:[0-9]+]], 0(r8)
 ; CHECK-NEXT:    xsaddqp v2, v[[REG1]], v2
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
entry:
   ret fp128 %add7
 }
 
 ; Function Attrs: norecurse nounwind
 define fastcc fp128 @mixParam_02f(fp128 %p1, double %p2, i64* nocapture %p3,
 ; CHECK-LABEL: mixParam_02f:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    add r4, r4, r6
-; CHECK-NEXT:    xxlor v[[REG0:[0-9]+]], f1, f1
+; CHECK-NEXT:    xscpsgndp v[[REG0:[0-9]+]], f1, f1
 ; CHECK-NEXT:    add r4, r4, r7
 ; CHECK-NEXT:    xscvdpqp v[[REG0]], v[[REG0]]
 ; CHECK-NEXT:    add r4, r4, r8
 ; CHECK-NEXT:    clrldi r4, r4, 32
 ; CHECK-NEXT:    std r4, 0(r3)
 ; CHECK-NEXT:    lxv v[[REG1:[0-9]+]], 0(r5)
 ; CHECK-NEXT:    xsaddqp v2, v[[REG1]], v2
 ; CHECK-NEXT:    xsaddqp v2, v2, v[[REG0]] 

llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll

-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-LE
+; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:       -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 \
+; RUN:       | FileCheck %s
+; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:       -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 \
+; RUN:       | FileCheck %s -check-prefix=CHECK-LE
 
 ; The build[csilf] functions simply test the scalar_to_vector handling with
 ; direct moves. This corresponds to the "insertelement" instruction. Subsequent
 ; to this, there will be a splat corresponding to the shufflevector.
 
 @d = common global double 0.000000e+00, align 8
 
 ; Function Attrs: norecurse nounwind readnone
 define <16 x i8> @buildc(i8 zeroext %a) {
 entry:
   %splat.splatinsert = insertelement <16 x i8> undef, i8 %a, i32 0
   %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
   ret <16 x i8> %splat.splat
-; CHECK: sldi [[REG1:[0-9]+]], 3, 56
-; CHECK: mtvsrd {{[0-9]+}}, [[REG1]]
-; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3
-; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]]
+; CHECK-LABEL: buildc
+; CHECK: sldi r3, r3, 56
+; CHECK: mtvsrd v2, r3
+; CHECK-LE-LABEL: buildc
+; CHECK-LE: mtvsrd f0, r3
+; CHECK-LE: xxswapd v2, vs0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define <8 x i16> @builds(i16 zeroext %a) {
 entry:
   %splat.splatinsert = insertelement <8 x i16> undef, i16 %a, i32 0
   %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
   ret <8 x i16> %splat.splat
-; CHECK: sldi [[REG1:[0-9]+]], 3, 48
-; CHECK: mtvsrd {{[0-9]+}}, [[REG1]]
-; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3
-; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]]
+; CHECK-LABEL: builds
+; CHECK: sldi r3, r3, 48
+; CHECK: mtvsrd v2, r3
+; CHECK-LE-LABEL: builds
+; CHECK-LE: mtvsrd f0, r3
+; CHECK-LE: xxswapd v2, vs0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define <4 x i32> @buildi(i32 zeroext %a) {
 entry:
   %splat.splatinsert = insertelement <4 x i32> undef, i32 %a, i32 0
   %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
   ret <4 x i32> %splat.splat
-; CHECK: mtvsrwz [[REG1:[0-9]+]], 3
-; CHECK: xxspltw 34, [[REG1]]
-; CHECK-LE: mtvsrwz [[REG1:[0-9]+]], 3
-; CHECK-LE: xxspltw 34, [[REG1]]
+; CHECK-LABEL: buildi
+; CHECK: mtvsrwz f0, r3
+; CHECK: xxspltw v2, vs0, 1
+; CHECK-LE-LABEL: buildi
+; CHECK-LE: mtvsrwz f0, r3
+; CHECK-LE: xxspltw v2, vs0, 1
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define <2 x i64> @buildl(i64 %a) {
 entry:
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %a, i32 0
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat.splat
-; CHECK: mtvsrd {{[0-9]+}}, 3
-; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3
-; CHECK-LE: xxspltd 34, [[REG1]], 0
+; CHECK-LABEL: buildl
+; CHECK: mtvsrd f0, r3
+; CHECK-LE-LABEL: buildl
+; CHECK-LE: mtvsrd f0, r3
+; CHECK-LE: xxspltd v2, vs0, 0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define <4 x float> @buildf(float %a) {
 entry:
   %splat.splatinsert = insertelement <4 x float> undef, float %a, i32 0
   %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
   ret <4 x float> %splat.splat
-; CHECK: xscvdpspn [[REG1:[0-9]+]], 1
-; CHECK: xxspltw 34, [[REG1]]
-; CHECK-LE: xscvdpspn [[REG1:[0-9]+]], 1
-; CHECK-LE: xxspltw 34, [[REG1]]
+; CHECK-LABEL: buildf
+; CHECK: xscvdpspn vs0, f1
+; CHECK: xxspltw v2, vs0, 0
+; CHECK-LE-LABEL: buildf
+; CHECK-LE: xscvdpspn vs0, f1
+; CHECK-LE: xxspltw v2, vs0, 0
 }
 
 ; The optimization to remove stack operations from PPCDAGToDAGISel::Select
 ; should still trigger for v2f64, producing an lxvdsx.
 ; Function Attrs: norecurse nounwind readonly
 define <2 x double> @buildd() {
 entry:
   %0 = load double, double* @d, align 8
   %splat.splatinsert = insertelement <2 x double> undef, double %0, i32 0
   %splat.splat = shufflevector <2 x double> %splat.splatinsert, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %splat.splat
-; CHECK: ld [[REG1:[0-9]+]], .LC0@toc@l
-; CHECK: lxvdsx 34, 0, [[REG1]]
-; CHECK-LE: ld [[REG1:[0-9]+]], .LC0@toc@l
-; CHECK-LE: lxvdsx 34, 0, [[REG1]]
+; CHECK-LABEL: buildd
+; CHECK: ld r3, .LC0@toc@l(r3)
+; CHECK: lxvdsx v2, 0, r3
+; CHECK-LE-LABEL: buildd
+; CHECK-LE: ld r3, .LC0@toc@l(r3)
+; CHECK-LE: lxvdsx v2, 0, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc0(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 0
   ret i8 %vecext
 ; CHECK-LABEL: @getsc0
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 8, 56
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 8, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc0
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: clrldi 3, 3, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: clrldi r3, r3, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc1(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 1
   ret i8 %vecext
 ; CHECK-LABEL: @getsc1
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 16, 56
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 16, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc1
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 56, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 56, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc2(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 2
   ret i8 %vecext
 ; CHECK-LABEL: @getsc2
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 24, 56
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 24, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc2
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 48, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 48, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc3(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 3
   ret i8 %vecext
 ; CHECK-LABEL: @getsc3
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 32, 56
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 32, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc3
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 40, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 40, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc4(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 4
   ret i8 %vecext
 ; CHECK-LABEL: @getsc4
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 40, 56
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 40, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc4
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 32, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 32, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc5(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 5
   ret i8 %vecext
 ; CHECK-LABEL: @getsc5
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 48, 56
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 48, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc5
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 24, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 24, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc6(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 6
   ret i8 %vecext
 ; CHECK-LABEL: @getsc6
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 56, 56
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 56, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc6
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 16, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 16, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc7(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 7
   ret i8 %vecext
 ; CHECK-LABEL: @getsc7
-; CHECK: mfvsrd 3, 34
-; CHECK: clrldi 3, 3, 56
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, v2
+; CHECK: clrldi r3, r3, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc7
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 8, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 8, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc8(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 8
   ret i8 %vecext
 ; CHECK-LABEL: @getsc8
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 8, 56
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 8, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc8
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: clrldi 3, 3, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: clrldi r3, r3, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc9(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 9
   ret i8 %vecext
 ; CHECK-LABEL: @getsc9
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 16, 56
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 16, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc9
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 56, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 56, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc10(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 10
   ret i8 %vecext
 ; CHECK-LABEL: @getsc10
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 24, 56
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 24, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc10
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 48, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 48, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc11(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 11
   ret i8 %vecext
 ; CHECK-LABEL: @getsc11
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 32, 56
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 32, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc11
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 40, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 40, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc12(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 12
   ret i8 %vecext
 ; CHECK-LABEL: @getsc12
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 40, 56
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 40, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc12
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 32, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 32, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc13(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 13
   ret i8 %vecext
 ; CHECK-LABEL: @getsc13
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 48, 56
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 48, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc13
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 24, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 24, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc14(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 14
   ret i8 %vecext
 ; CHECK-LABEL: @getsc14
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 56, 56
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 56, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc14
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 16, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 16, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc15(<16 x i8> %vsc) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 15
   ret i8 %vecext
 ; CHECK-LABEL: @getsc15
-; CHECK: mfvsrd 3,
-; CHECK: extsb 3, 3
+; CHECK: mfvsrd r3, f0
+; CHECK: clrldi  r3, r3, 56
+; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc15
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 8, 56
-; CHECK-LE: extsb 3, 3
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 8, 56
+; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc0(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 0
   ret i8 %vecext
 ; CHECK-LABEL: @getuc0
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 8, 56
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 8, 56
 ; CHECK-LE-LABEL: @getuc0
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: clrldi   3, 3, 56
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: clrldi r3, r3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc1(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 1
   ret i8 %vecext
 ; CHECK-LABEL: @getuc1
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 16, 56
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 16, 56
 ; CHECK-LE-LABEL: @getuc1
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 56, 56
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 56, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc2(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 2
   ret i8 %vecext
 ; CHECK-LABEL: @getuc2
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 24, 56
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 24, 56
 ; CHECK-LE-LABEL: @getuc2
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 48, 56
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 48, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc3(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 3
   ret i8 %vecext
 ; CHECK-LABEL: @getuc3
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 32, 56
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 32, 56
 ; CHECK-LE-LABEL: @getuc3
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 40, 56
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 40, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc4(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 4
   ret i8 %vecext
 ; CHECK-LABEL: @getuc4
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 40, 56
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 40, 56
 ; CHECK-LE-LABEL: @getuc4
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 32, 56
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 32, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc5(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 5
   ret i8 %vecext
 ; CHECK-LABEL: @getuc5
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 48, 56
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 48, 56
 ; CHECK-LE-LABEL: @getuc5
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 24, 56
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 24, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc6(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 6
   ret i8 %vecext
 ; CHECK-LABEL: @getuc6
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 56, 56
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 56, 56
 ; CHECK-LE-LABEL: @getuc6
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 16, 56
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 16, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc7(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 7
   ret i8 %vecext
 ; CHECK-LABEL: @getuc7
-; CHECK: mfvsrd 3, 34
-; CHECK: clrldi   3, 3, 56
+; CHECK: mfvsrd r3, v2
+; CHECK: clrldi   r3, r3, 56
 ; CHECK-LE-LABEL: @getuc7
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 8, 56
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 8, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc8(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 8
   ret i8 %vecext
 ; CHECK-LABEL: @getuc8
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 8, 56
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 8, 56
 ; CHECK-LE-LABEL: @getuc8
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: clrldi   3, 3, 56
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: clrldi r3, r3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc9(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 9
   ret i8 %vecext
 ; CHECK-LABEL: @getuc9
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 16, 56
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 16, 56
 ; CHECK-LE-LABEL: @getuc9
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 56, 56
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 56, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc10(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 10
   ret i8 %vecext
 ; CHECK-LABEL: @getuc10
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 24, 56
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 24, 56
 ; CHECK-LE-LABEL: @getuc10
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 48, 56
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 48, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc11(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 11
   ret i8 %vecext
 ; CHECK-LABEL: @getuc11
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 32, 56
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 32, 56
 ; CHECK-LE-LABEL: @getuc11
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 40, 56
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 40, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc12(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 12
   ret i8 %vecext
 ; CHECK-LABEL: @getuc12
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 40, 56
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 40, 56
 ; CHECK-LE-LABEL: @getuc12
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 32, 56
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 32, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc13(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 13
   ret i8 %vecext
 ; CHECK-LABEL: @getuc13
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 48, 56
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 48, 56
 ; CHECK-LE-LABEL: @getuc13
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 24, 56
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 24, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc14(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 14
   ret i8 %vecext
 ; CHECK-LABEL: @getuc14
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 56, 56
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 56, 56
 ; CHECK-LE-LABEL: @getuc14
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 16, 56
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 16, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc15(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 15
   ret i8 %vecext
 ; CHECK-LABEL: @getuc15
-; CHECK: mfvsrd 3,
-; CHECK: clrldi   3, 3, 56
+; CHECK: mfvsrd r3, f0
+; CHECK: clrldi   r3, r3, 56
 ; CHECK-LE-LABEL: @getuc15
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 8, 56
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 8, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) {
+; CHECK-LABEL: @getvelsc
+; CHECK: andi. r4, r5, 8
+; CHECK: li r3, 7
+; CHECK: lvsl v3, 0, r4
+; CHECK: andc r3, r3, r5
+; CHECK: sldi r3, r3, 3
+; CHECK: vperm v2, v2, v2, v3
+; CHECK: mfvsrd r4, v2
+; CHECK: srd r3, r4, r3
+; CHECK: extsb r3, r3
+; CHECK-LE-LABEL: @getvelsc
+; CHECK-LE: li r3, 8
+; CHECK-LE: andc r3, r3, r5
+; CHECK-LE: lvsl v3, 0, r3
+; CHECK-LE: li r3, 7
+; CHECK-LE: and r3, r3, r5
+; CHECK-LE: vperm v2, v2, v2, v3
+; CHECK-LE: sldi r3, r3, 3
+; CHECK-LE: mfvsrd r4, v2
+; CHECK-LE: srd r3, r4, r3
+; CHECK-LE: extsb r3, r3
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 %i
   ret i8 %vecext
-; CHECK-LABEL: @getvelsc
-; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8
-; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]]
-; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]]
-; CHECK-DAG: mfvsrd [[MOV:[0-9]+]],
-; CHECK-DAG: li [[IMM7:[0-9]+]], 7
-; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]]
-; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3
-; CHECK-DAG: srd 3, [[MOV]], [[SHL]]
-; CHECK-DAG: extsb 3, 3
-; CHECK-LE-LABEL: @getvelsc
-; CHECK-DAG-LE: li [[IMM8:[0-9]+]], 8
-; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]]
-; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[ANDC]]
-; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]]
-; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]],
-; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7
-; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]]
-; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3
-; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]]
-; CHECK-DAG-LE: extsb 3, 3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getveluc(<16 x i8> %vuc, i32 signext %i) {
+; CHECK-LABEL: @getveluc
+; CHECK: andi. r4, r5, 8
+; CHECK: li r3, 7
+; CHECK: lvsl v3, 0, r4
+; CHECK: andc r3, r3, r5
+; CHECK: sldi r3, r3, 3
+; CHECK: vperm v2, v2, v2, v3
+; CHECK: mfvsrd r4, v2
+; CHECK: srd r3, r4, r3
+; CHECK: clrldi  r3, r3, 5
+; CHECK-LE-LABEL: @getveluc
+; CHECK-LE: li r3, 8
+; CHECK-LE: andc r3, r3, r5
+; CHECK-LE: lvsl v3, 0, r3
+; CHECK-LE: li r3, 7
+; CHECK-LE: and r3, r3, r5
+; CHECK-LE: vperm v2, v2, v2, v3
+; CHECK-LE: sldi r3, r3, 3
+; CHECK-LE: mfvsrd r4, v2
+; CHECK-LE: srd r3, r4, r3
+; CHECK-LE: clrldi r3, r3, 56
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 %i
   ret i8 %vecext
-; CHECK-LABEL: @getveluc
-; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8
-; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]]
-; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]]
-; CHECK-DAG: mfvsrd [[MOV:[0-9]+]],
-; CHECK-DAG: li [[IMM7:[0-9]+]], 7
-; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]]
-; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3
-; CHECK-DAG: srd 3, [[MOV]], [[SHL]]
-; CHECK-DAG: clrldi   3, 3, 56
-; CHECK-LE-LABEL: @getveluc
-; CHECK-DAG-LE: li [[IMM8:[0-9]+]], 8
-; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]]
-; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[ANDC]]
-; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]]
-; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]],
-; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7
-; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]]
-; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3
-; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]]
-; CHECK-DAG-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss0(<8 x i16> %vss) {
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 0
   ret i16 %vecext
 ; CHECK-LABEL: @getss0
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 16, 48
-; CHECK: extsh 3, 3
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 16, 48
+; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss0
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: clrldi 3, 3, 48
-; CHECK-LE: extsh 3, 3
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: clrldi r3, r3, 48
+; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss1(<8 x i16> %vss) {
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 1
   ret i16 %vecext
 ; CHECK-LABEL: @getss1
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 32, 48
-; CHECK: extsh 3, 3
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 32, 48
+; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss1
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 48, 48
-; CHECK-LE: extsh 3, 3
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 48, 48
+; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss2(<8 x i16> %vss) {
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 2
   ret i16 %vecext
 ; CHECK-LABEL: @getss2
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 48, 48
-; CHECK: extsh 3, 3
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 48, 48
+; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss2
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 32, 48
-; CHECK-LE: extsh 3, 3
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 32, 48
+; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss3(<8 x i16> %vss) {
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 3
   ret i16 %vecext
 ; CHECK-LABEL: @getss3
-; CHECK: mfvsrd 3, 34
-; CHECK: clrldi 3, 3, 48
-; CHECK: extsh 3, 3
+; CHECK: mfvsrd r3, v2
+; CHECK: clrldi r3, r3, 48
+; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss3
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 16, 48
-; CHECK-LE: extsh 3, 3
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 16, 48
+; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss4(<8 x i16> %vss) {
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 4
   ret i16 %vecext
 ; CHECK-LABEL: @getss4
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 16, 48
-; CHECK: extsh 3, 3
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 16, 48
+; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss4
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: clrldi 3, 3, 48
-; CHECK-LE: extsh 3, 3
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: clrldi r3, r3, 48
+; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss5(<8 x i16> %vss) {
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 5
   ret i16 %vecext
 ; CHECK-LABEL: @getss5
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 32, 48
-; CHECK: extsh 3, 3
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 32, 48
+; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss5
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 48, 48
-; CHECK-LE: extsh 3, 3
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 48, 48
+; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss6(<8 x i16> %vss) {
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 6
   ret i16 %vecext
 ; CHECK-LABEL: @getss6
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 48, 48
-; CHECK: extsh 3, 3
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 48, 48
+; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss6
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 32, 48
-; CHECK-LE: extsh 3, 3
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 32, 48
+; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss7(<8 x i16> %vss) {
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 7
   ret i16 %vecext
 ; CHECK-LABEL: @getss7
-; CHECK: mfvsrd 3,
-; CHECK: extsh 3, 3
+; CHECK: mfvsrd r3, f0
+; CHECK: clrldi  r3, r3, 48
+; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss7
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 16, 48
-; CHECK-LE: extsh 3, 3
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 16, 48
+; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus0(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 0
   ret i16 %vecext
 ; CHECK-LABEL: @getus0
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 16, 48
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 16, 48
 ; CHECK-LE-LABEL: @getus0
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: clrldi   3, 3, 48
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: clrldi r3, r3, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus1(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 1
   ret i16 %vecext
 ; CHECK-LABEL: @getus1
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 32, 48
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 32, 48
 ; CHECK-LE-LABEL: @getus1
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 48, 48
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 48, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus2(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 2
   ret i16 %vecext
 ; CHECK-LABEL: @getus2
-; CHECK: mfvsrd 3, 34
-; CHECK: rldicl 3, 3, 48, 48
+; CHECK: mfvsrd r3, v2
+; CHECK: rldicl r3, r3, 48, 48
 ; CHECK-LE-LABEL: @getus2
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 32, 48
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 32, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus3(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 3
   ret i16 %vecext
 ; CHECK-LABEL: @getus3
-; CHECK: mfvsrd 3, 34
-; CHECK: clrldi   3, 3, 48
+; CHECK: mfvsrd r3, v2
+; CHECK: clrldi   r3, r3, 48
 ; CHECK-LE-LABEL: @getus3
-; CHECK-LE: mfvsrd 3,
-; CHECK-LE: rldicl 3, 3, 16, 48
+; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: rldicl r3, r3, 16, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus4(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 4
   ret i16 %vecext
 ; CHECK-LABEL: @getus4
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 16, 48
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 16, 48
 ; CHECK-LE-LABEL: @getus4
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: clrldi   3, 3, 48
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: clrldi r3, r3, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus5(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 5
   ret i16 %vecext
 ; CHECK-LABEL: @getus5
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 32, 48
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 32, 48
 ; CHECK-LE-LABEL: @getus5
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 48, 48
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 48, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus6(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 6
   ret i16 %vecext
 ; CHECK-LABEL: @getus6
-; CHECK: mfvsrd 3,
-; CHECK: rldicl 3, 3, 48, 48
+; CHECK: mfvsrd r3, f0
+; CHECK: rldicl r3, r3, 48, 48
 ; CHECK-LE-LABEL: @getus6
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 32, 48
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 32, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus7(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 7
   ret i16 %vecext
 ; CHECK-LABEL: @getus7
-; CHECK: mfvsrd 3,
-; CHECK: clrldi   3, 3, 48
+; CHECK: mfvsrd r3, f0
+; CHECK: clrldi   r3, r3, 48
 ; CHECK-LE-LABEL: @getus7
-; CHECK-LE: mfvsrd 3, 34
-; CHECK-LE: rldicl 3, 3, 16, 48
+; CHECK-LE: mfvsrd r3, v2
+; CHECK-LE: rldicl r3, r3, 16, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) {
+; CHECK-LABEL: @getvelss
+; CHECK: andi. r4, r5, 4
+; CHECK: li r3, 3
+; CHECK: sldi r4, r4, 1
+; CHECK: andc r3, r3, r5
+; CHECK: lvsl v3, 0, r4
+; CHECK: sldi r3, r3, 4
+; CHECK: vperm v2, v2, v2, v3
+; CHECK: mfvsrd r4, v2
+; CHECK: srd r3, r4, r3
+; CHECK: extsh r3, r3
+; CHECK-LE-LABEL: @getvelss
+; CHECK-LE: li r3, 4
+; CHECK-LE: andc r3, r3, r5
+; CHECK-LE: sldi r3, r3, 1
+; CHECK-LE: lvsl v3, 0, r3
+; CHECK-LE: li r3, 3
+; CHECK-LE: and r3, r3, r5
+; CHECK-LE: vperm v2, v2, v2, v3
+; CHECK-LE: sldi r3, r3, 4
+; CHECK-LE: mfvsrd r4, v2
+; CHECK-LE: srd r3, r4, r3
+; CHECK-LE: extsh r3, r3
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 %i
   ret i16 %vecext
-; CHECK-LABEL: @getvelss
-; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4
-; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1
-; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]]
-; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]]
-; CHECK-DAG: mfvsrd [[MOV:[0-9]+]],
-; CHECK-DAG: li [[IMM3:[0-9]+]], 3
-; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM3]]
-; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 4
-; CHECK-DAG: srd 3, [[MOV]], [[SHL]]
-; CHECK-DAG: extsh 3, 3
-; CHECK-LE-LABEL: @getvelss
-; CHECK-DAG-LE: li [[IMM4:[0-9]+]], 4
-; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM4]]
-; CHECK-DAG-LE: sldi [[MUL2:[0-9]+]], [[ANDC]], 1
-; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]]
-; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]]
-; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]],
-; CHECK-DAG-LE: li [[IMM3:[0-9]+]], 3
-; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM3]]
-; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 4
-; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]]
-; CHECK-DAG-LE: extsh 3, 3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getvelus(<8 x i16> %vus, i32 signext %i) {
+; CHECK-LABEL: @getvelus
+; CHECK: andi. r4, r5, 4
+; CHECK: li r3, 3
+; CHECK: sldi r4, r4, 1
+; CHECK: andc r3, r3, r5
+; CHECK: lvsl v3, 0, r4
+; CHECK: sldi r3, r3, 4
+; CHECK: vperm v2, v2, v2, v3
+; CHECK: mfvsrd r4, v2
+; CHECK: srd r3, r4, r3
+; CHECK: clrldi  r3, r3, 48
+; CHECK-LE-LABEL: @getvelus
+; CHECK-LE: li r3, 4
+; CHECK-LE: andc r3, r3, r5
+; CHECK-LE: sldi r3, r3, 1
+; CHECK-LE: lvsl v3, 0, r3
+; CHECK-LE: li r3, 3
+; CHECK-LE: and r3, r3, r5
+; CHECK-LE: vperm v2, v2, v2, v3
+; CHECK-LE: sldi r3, r3, 4
+; CHECK-LE: mfvsrd r4, v2
+; CHECK-LE: srd r3, r4, r3
+; CHECK-LE: clrldi r3, r3, 48
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 %i
   ret i16 %vecext
-; CHECK-LABEL: @getvelus
-; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4
-; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1
-; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]]
-; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]]
-; CHECK-DAG: mfvsrd [[MOV:[0-9]+]],
-; CHECK-DAG: li [[IMM3:[0-9]+]], 3
-; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM3]]
-; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 4
-; CHECK-DAG: srd 3, [[MOV]], [[SHL]]
-; CHECK-DAG: clrldi   3, 3, 48
-; CHECK-LE-LABEL: @getvelus
-; CHECK-DAG-LE: li [[IMM4:[0-9]+]], 4
-; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM4]]
-; CHECK-DAG-LE: sldi [[MUL2:[0-9]+]], [[ANDC]], 1
-; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]]
-; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]]
-; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]],
-; CHECK-DAG-LE: li [[IMM3:[0-9]+]], 3
-; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM3]]
-; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 4
-; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]]
-; CHECK-DAG-LE: clrldi   3, 3, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @getsi0(<4 x i32> %vsi) {
 entry:
   %vecext = extractelement <4 x i32> %vsi, i32 0
   ret i32 %vecext
 ; CHECK-LABEL: @getsi0
-; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
-; CHECK: mfvsrwz 3, [[SHL]]
-; CHECK: extsw 3, 3
+; CHECK: xxsldwi vs0, v2, v2, 3
+; CHECK: mfvsrwz r3, f0
+; CHECK: extsw r3, r3
 ; CHECK-LE-LABEL: @getsi0
-; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34
-; CHECK-LE: mfvsrwz 3, [[SHL]]
-; CHECK-LE: extsw 3, 3
+; CHECK-LE: xxswapd vs0, v2
+; CHECK-LE: mfvsrwz r3, f0
+; CHECK-LE: extsw r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @getsi1(<4 x i32> %vsi) {
 entry:
   %vecext = extractelement <4 x i32> %vsi, i32 1
   ret i32 %vecext
 ; CHECK-LABEL: @getsi1
-; CHECK: mfvsrwz 3, 34
-; CHECK: extsw 3, 3
+; CHECK: mfvsrwz r3, v2
+; CHECK: extsw r3, r3
 ; CHECK-LE-LABEL: @getsi1
-; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
-; CHECK-LE: mfvsrwz 3, [[SHL]]
-; CHECK-LE: extsw 3, 3
+; CHECK-LE: xxsldwi vs0, v2, v2, 1
+; CHECK-LE: mfvsrwz r3, f0
+; CHECK-LE: extsw r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @getsi2(<4 x i32> %vsi) {
 entry:
   %vecext = extractelement <4 x i32> %vsi, i32 2
   ret i32 %vecext
 ; CHECK-LABEL: @getsi2
-; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
-; CHECK: mfvsrwz 3, [[SHL]]
-; CHECK: extsw 3, 3
+; CHECK: xxsldwi vs0, v2, v2, 1
+; CHECK: mfvsrwz r3, f0
+; CHECK: extsw r3, r3
 ; CHECK-LE-LABEL: @getsi2
-; CHECK-LE: mfvsrwz 3, 34
-; CHECK-LE: extsw 3, 3
+; CHECK-LE: mfvsrwz r3, v2
+; CHECK-LE: extsw r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @getsi3(<4 x i32> %vsi) {
 entry:
   %vecext = extractelement <4 x i32> %vsi, i32 3
   ret i32 %vecext
 ; CHECK-LABEL: @getsi3
-; CHECK: xxswapd [[SHL:[0-9]+]], 34
-; CHECK: mfvsrwz 3, [[SHL]]
-; CHECK: extsw 3, 3
+; CHECK: xxswapd vs0, v2
+; CHECK: mfvsrwz r3, f0
+; CHECK: extsw r3, r3
 ; CHECK-LE-LABEL: @getsi3
-; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
-; CHECK-LE: mfvsrwz 3, [[SHL]]
-; CHECK-LE: extsw 3, 3
+; CHECK-LE: xxsldwi vs0, v2, v2, 3
+; CHECK-LE: mfvsrwz r3, f0
+; CHECK-LE: extsw r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui0(<4 x i32> %vui) {
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 0
   ret i32 %vecext
 ; CHECK-LABEL: @getui0
-; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
-; CHECK: mfvsrwz 3, [[SHL]]
+; CHECK: xxsldwi vs0, v2, v2, 3
+; CHECK: mfvsrwz r3, f0
 ; CHECK-LE-LABEL: @getui0
-; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34
-; CHECK-LE: mfvsrwz 3, [[SHL]]
+; CHECK-LE: xxswapd vs0, v2
+; CHECK-LE: mfvsrwz r3, f0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui1(<4 x i32> %vui) {
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 1
   ret i32 %vecext
 ; CHECK-LABEL: @getui1
-; CHECK: mfvsrwz 3, 34
+; CHECK: mfvsrwz r3, v2
 ; CHECK-LE-LABEL: @getui1
-; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
-; CHECK-LE: mfvsrwz 3, [[SHL]]
+; CHECK-LE: xxsldwi vs0, v2, v2, 1
+; CHECK-LE: mfvsrwz r3, f0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui2(<4 x i32> %vui) {
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 2
   ret i32 %vecext
 ; CHECK-LABEL: @getui2
-; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
-; CHECK: mfvsrwz 3, [[SHL]]
+; CHECK: xxsldwi vs0, v2, v2, 1
+; CHECK: mfvsrwz r3, f0
 ; CHECK-LE-LABEL: @getui2
-; CHECK-LE: mfvsrwz 3, 34
+; CHECK-LE: mfvsrwz r3, v2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui3(<4 x i32> %vui) {
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 3
   ret i32 %vecext
 ; CHECK-LABEL: @getui3
-; CHECK: xxswapd [[SHL:[0-9]+]], 34
-; CHECK: mfvsrwz 3, [[SHL]]
+; CHECK: xxswapd vs0, v2
+; CHECK: mfvsrwz r3, f0
 ; CHECK-LE-LABEL: @getui3
-; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
-; CHECK-LE: mfvsrwz 3, [[SHL]]
+; CHECK-LE: xxsldwi vs0, v2, v2, 3
+; CHECK-LE: mfvsrwz r3, f0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @getvelsi(<4 x i32> %vsi, i32 signext %i) {
 entry:
   %vecext = extractelement <4 x i32> %vsi, i32 %i
   ret i32 %vecext
 ; CHECK-LABEL: @getvelsi

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getsl0(<2 x i64> %vsl) {
 entry:
   %vecext = extractelement <2 x i64> %vsl, i32 0
   ret i64 %vecext
 ; CHECK-LABEL: @getsl0
-; CHECK: mfvsrd 3, 34
+; CHECK: mfvsrd r3, v2
 ; CHECK-LE-LABEL: @getsl0
-; CHECK-LE: xxswapd  [[SWP:[0-9]+]], 34
-; CHECK-LE: mfvsrd 3, [[SWP]]
+; CHECK-LE: xxswapd vs0, v2
+; CHECK-LE: mfvsrd r3, f0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getsl1(<2 x i64> %vsl) {
 entry:
   %vecext = extractelement <2 x i64> %vsl, i32 1
   ret i64 %vecext
 ; CHECK-LABEL: @getsl1
-; CHECK: xxswapd  [[SWP:[0-9]+]], 34
-; CHECK: mfvsrd 3, [[SWP]]
+; CHECK: xxswapd vs0, v2
+; CHECK: mfvsrd r3, f0
 ; CHECK-LE-LABEL: @getsl1
-; CHECK-LE: mfvsrd 3, 34
+; CHECK-LE: mfvsrd r3, v2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getul0(<2 x i64> %vul) {
 entry:
   %vecext = extractelement <2 x i64> %vul, i32 0
   ret i64 %vecext
 ; CHECK-LABEL: @getul0
-; CHECK: mfvsrd 3, 34
+; CHECK: mfvsrd r3, v2
 ; CHECK-LE-LABEL: @getul0
-; CHECK-LE: xxswapd  [[SWP:[0-9]+]], 34
-; CHECK-LE: mfvsrd 3, [[SWP]]
+; CHECK-LE: xxswapd  vs0, v2
+; CHECK-LE: mfvsrd r3, f0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getul1(<2 x i64> %vul) {
 entry:
   %vecext = extractelement <2 x i64> %vul, i32 1
   ret i64 %vecext
 ; CHECK-LABEL: @getul1
-; CHECK: xxswapd  [[SWP:[0-9]+]], 34
-; CHECK: mfvsrd 3, [[SWP]]
+; CHECK: xxswapd vs0, v2
+; CHECK: mfvsrd r3, f0
 ; CHECK-LE-LABEL: @getul1
-; CHECK-LE: mfvsrd 3, 34
+; CHECK-LE: mfvsrd r3, v2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) {
 entry:
   %vecext = extractelement <2 x i64> %vsl, i32 %i
   ret i64 %vecext
 ; CHECK-LABEL: @getvelsl

 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @getf0(<4 x float> %vf) {
 entry:
   %vecext = extractelement <4 x float> %vf, i32 0
   ret float %vecext
 ; CHECK-LABEL: @getf0
-; CHECK: xscvspdpn 1, 34
+; CHECK: xscvspdpn f1, v2
 ; CHECK-LE-LABEL: @getf0
-; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
-; CHECK-LE: xscvspdpn 1, [[SHL]]
+; CHECK-LE: xxsldwi vs0, v2, v2, 3
+; CHECK-LE: xscvspdpn f1, vs0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @getf1(<4 x float> %vf) {
 entry:
   %vecext = extractelement <4 x float> %vf, i32 1
   ret float %vecext
 ; CHECK-LABEL: @getf1
-; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
-; CHECK: xscvspdpn 1, [[SHL]]
+; CHECK: xxsldwi vs0, v2, v2, 1
+; CHECK: xscvspdpn f1, vs0
 ; CHECK-LE-LABEL: @getf1
-; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34
-; CHECK-LE: xscvspdpn 1, [[SHL]]
+; CHECK-LE: xxswapd vs0, v2
+; CHECK-LE: xscvspdpn f1, vs0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @getf2(<4 x float> %vf) {
 entry:
   %vecext = extractelement <4 x float> %vf, i32 2
   ret float %vecext
 ; CHECK-LABEL: @getf2
-; CHECK: xxswapd [[SHL:[0-9]+]], 34
-; CHECK: xscvspdpn 1, [[SHL]]
+; CHECK: xxswapd vs0, v2
+; CHECK: xscvspdpn f1, vs0
 ; CHECK-LE-LABEL: @getf2
-; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
-; CHECK-LE: xscvspdpn 1, [[SHL]]
+; CHECK-LE: xxsldwi vs0, v2, v2, 1
+; CHECK-LE: xscvspdpn f1, vs0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @getf3(<4 x float> %vf) {
 entry:
   %vecext = extractelement <4 x float> %vf, i32 3
   ret float %vecext
 ; CHECK-LABEL: @getf3
-; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
-; CHECK: xscvspdpn 1, [[SHL]]
+; CHECK: xxsldwi vs0, v2, v2, 3
+; CHECK: xscvspdpn f1, vs0
 ; CHECK-LE-LABEL: @getf3
-; CHECK-LE: xscvspdpn 1, 34
+; CHECK-LE: xscvspdpn f1, v2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @getvelf(<4 x float> %vf, i32 signext %i) {
 entry:
   %vecext = extractelement <4 x float> %vf, i32 %i
   ret float %vecext
 ; CHECK-LABEL: @getvelf
 ; CHECK-LE-LABEL: @getvelf
 ; FIXME: add check patterns when variable element extraction is implemented
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @getd0(<2 x double> %vd) {
 entry:
   %vecext = extractelement <2 x double> %vd, i32 0
   ret double %vecext
 ; CHECK-LABEL: @getd0
-; CHECK: xxlor 1, 34, 34
+; CHECK: xxlor f1, v2, v2
 ; CHECK-LE-LABEL: @getd0
-; CHECK-LE: xxswapd  1, 34
+; CHECK-LE: xxswapd vs1, v2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @getd1(<2 x double> %vd) {
 entry:
   %vecext = extractelement <2 x double> %vd, i32 1
   ret double %vecext
 ; CHECK-LABEL: @getd1
-; CHECK: xxswapd  1, 34
+; CHECK: xxswapd vs1, v2
 ; CHECK-LE-LABEL: @getd1
-; CHECK-LE: xxlor 1, 34, 34
+; CHECK-LE: xxlor f1, v2, v2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @getveld(<2 x double> %vd, i32 signext %i) {
 entry:
   %vecext = extractelement <2 x double> %vd, i32 %i
   ret double %vecext
 ; CHECK-LABEL: @getveld
 ; CHECK-LE-LABEL: @getveld
 ; FIXME: add check patterns when variable element extraction is implemented
 }

llvm/test/CodeGen/PowerPC/p9_copy_fp.ll

+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=+vsx -ppc-vsr-nums-as-vr \
+; RUN:     -mtriple=powerpc64le-unknown-linux-gnu -ppc-asm-full-reg-names < %s \
+; RUN:     | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=+vsx -ppc-vsr-nums-as-vr \
+; RUN:     -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names < %s \
+; RUN:     | FileCheck -check-prefix=CHECK-BE %s
+
+; Function Attrs: norecurse nounwind readnone
+define double @cp_fp1(<2 x double> %v) {
+; CHECK-LABEL: cp_fp1:
+; CHECK: xscpsgndp f1, v2, v2
+; CHECK: blr
+
+; CHECK-BE-LABEL: cp_fp1:
+; CHECK-BE: xxswapd vs1, v2
+; CHECK-BE: blr
+entry:
+  %vecext = extractelement <2 x double> %v, i32 1
+  ret double %vecext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define double @cp_fp2(<2 x double> %v) {
+; CHECK-LABEL: cp_fp2:
+; CHECK:    xxswapd vs1, v2
+; CHECK:    blr
+
+; CHECK-BE-LABEL: cp_fp2:
+; CHECK-BE: xscpsgndp f1, v2, v2
+; CHECK-BE: blr
+entry:
+  %vecext = extractelement <2 x double> %v, i32 0
+  ret double %vecext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define <2 x double> @cp_fp3(double %v) {
+; CHECK-LABEL: cp_fp3:
+; CHECK:    xxspltd v2, vs1, 0
+; CHECK:    blr
+
+; CHECK-BE-LABEL: cp_fp3:
+; CHECK-BE: xscpsgndp v2, f1, f1
+; CHECK-BE: blr
+entry:
+  %vecins = insertelement <2 x double> undef, double %v, i32 0
+  ret <2 x double> %vecins
+}
+

llvm/test/CodeGen/PowerPC/vsx-spill.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx < %s | FileCheck \
-; RUN:   -check-prefix=CHECK-REG %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | \
-; RUN:   FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | \
-; RUN:   FileCheck -check-prefix=CHECK-FISL %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck \
-; RUN:   -check-prefix=CHECK-P9-REG %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr9 -fast-isel -O0 < %s | FileCheck \
-; RUN:   -check-prefix=CHECK-P9-FISL %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx \
+; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx \
+; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
+; RUN:     -check-prefix=CHECK-REG %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 \
+; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 \
+; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | \
+; RUN:     FileCheck -check-prefix=CHECK-FISL %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
+; RUN:     -ppc-asm-full-reg-names < %s | FileCheck -check-prefix=CHECK-P9-REG %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -fast-isel -O0 \
+; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
+; RUN:     -check-prefix=CHECK-P9-FISL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @foo1(double %a) nounwind {
 entry:
   call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
   br label %return
 
 ; CHECK-REG: @foo1
-; CHECK-REG: xxlor [[R1:[0-9]+]], 1, 1
-; CHECK-REG: xxlor 1, [[R1]], [[R1]]
+; CHECK-REG: xxlor v2, f1, f1
+; CHECK-REG: xxlor f1, v2, v2
 ; CHECK-REG: blr
 
 ; CHECK-FISL: @foo1
 ; CHECK-FISL-NOT: lis
 ; CHECK-FISL-NOT: ori
-; CHECK-FISL: li 3, -152
+; CHECK-FISL: li r3, -152
 ; CHECK-FISL-NOT: lis
 ; CHECK-FISL-NOT: ori
-; CHECK-FISL: stxsdx 1, 1, 3
+; CHECK-FISL: stxsdx f1, r1, r3
 ; CHECK-FISL: blr
 
 ; CHECK-P9-REG: @foo1
-; CHECK-P9-REG: xxlor [[R1:[0-9]+]], 1, 1
-; CHECK-P9-REG: xxlor 1, [[R1]], [[R1]]
+; CHECK-P9-REG: xscpsgndp v2, f1, f1
+; CHECK-P9-REG: xscpsgndp f1, v2, v2
 ; CHECK-P9-REG: blr
 
 ; CHECK-P9-FISL: @foo1
-; CHECK-P9-FISL: stfd 31, -8(1)
+; CHECK-P9-FISL: stfd f31, -8(r1)
 ; CHECK-P9-FISL: blr
 
 return:                                           ; preds = %entry
   ret double %a
 }
 
 define double @foo2(double %a) nounwind {
 entry:
   %b = fadd double %a, %a
   call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
   br label %return
 
 ; CHECK-REG: @foo2
-; CHECK-REG: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1
-; CHECK-REG: {{xxlor|xsadddp}} 1, [[R1]], [[R1]]
+; CHECK-REG: {{xxlor|xsadddp}} v2, f1, f1
+; CHECK-REG: {{xxlor|xsadddp}} f1, f0, f0
 ; CHECK-REG: blr
 
 ; CHECK-FISL: @foo2
-; CHECK-FISL: xsadddp [[R1:[0-9]+]], 1, 1
-; CHECK-FISL: stxsdx [[R1]], [[R1]], 3
-; CHECK-FISL: lxsdx [[R1]], [[R1]], 3
+; CHECK-FISL: xsadddp f1, f1, f1
+; CHECK-FISL: stxsdx f1, r1, r3
+; CHECK-FISL: lxsdx f1, r1, r3
 ; CHECK-FISL: blr
 
 ; CHECK-P9-REG: @foo2
-; CHECK-P9-REG: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1
-; CHECK-P9-REG: {{xxlor|xsadddp}} 1, [[R1]], [[R1]]
+; CHECK-P9-REG: {{xscpsgndp|xsadddp}} v2, f1, f1
+; CHECK-P9-REG: {{xscpsgndp|xsadddp}} f1, v2, v2
 ; CHECK-P9-REG: blr
 
 ; CHECK-P9-FISL: @foo2
-; CHECK-P9-FISL: xsadddp [[R1:[0-9]+]], 1, 1
-; CHECK-P9-FISL: stfd [[R1]], [[OFF:[0-9\-]+]](1)
-; CHECK-P9-FISL: lfd [[R1]], [[OFF]](1)
+; CHECK-P9-FISL: xsadddp f1, f1, f1
+; CHECK-P9-FISL: stfd f1, -152(r1)
+; CHECK-P9-FISL: lfd f1, -152(r1)
 ; CHECK-P9-FISL: blr
 
 return:                                           ; preds = %entry
   ret double %b
 }
 
 define double @foo3(double %a) nounwind {
 entry:
   call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() nounwind
   br label %return
 
 ; CHECK: @foo3
-; CHECK: stxsdx 1,
-; CHECK: lxsdx [[R1:[0-9]+]],
-; CHECK: xsadddp 1, [[R1]], [[R1]]
+; CHECK: stxsdx f1, r1, r3
+; CHECK: lxsdx f0, r1, r3
+; CHECK: xsadddp f1, f0, f0
 ; CHECK: blr
 
 ; CHECK-P9-REG-LABEL: foo3
-; CHECK-P9-REG: stfd 1, [[OFF:[0-9\-]+]](1)
-; CHECK-P9-REG: lfd [[FPR:[0-9]+]], [[OFF]](1)
-; CHECK-P9-REG: xsadddp 1, [[FPR]], [[FPR]]
+; CHECK-P9-REG: stdu r1, -400(r1)
+; CHECK-P9-REG: lfd f30, 384(r1)
+; CHECK-P9-REG: xsadddp f1, f0, f0
 
 ; CHECK-P9-FISL-LABEL: foo3
-; CHECK-P9-FISL: stfd 1, [[OFF:[0-9\-]+]](1)
-; CHECK-P9-FISL: lfd [[FPR:[0-9]+]], [[OFF]](1)
-; CHECK-P9-FISL: xsadddp 1, [[FPR]], [[FPR]]
+; CHECK-P9-FISL: stdu r1, -400(r1)
+; CHECK-P9-FISL: lfd f0, 56(r1)
+; CHECK-P9-FISL: xsadddp f1, f0, f0
 return:                                           ; preds = %entry
   %b = fadd double %a, %a
   ret double %b
 }
 

llvm/test/CodeGen/PowerPC/vsx.ll

-; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s
-; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s
-; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s
-; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
-; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-LE %s
+; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \
+; RUN:     -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx \
+; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \
+; RUN:     -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx \
+; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
+; RUN:     -check-prefix=CHECK-REG %s
+; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \
+; RUN:     -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 \
+; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
+; RUN:     -check-prefix=CHECK-FISL %s
+; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 \
+; RUN:     -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx \
+; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
+; RUN:     -check-prefix=CHECK-LE %s
 
 define double @test1(double %a, double %b) {
 entry:
   %v = fmul double %a, %b
   ret double %v
 
 ; CHECK-LABEL: @test1
-; CHECK: xsmuldp 1, 1, 2
+; CHECK: xsmuldp f1, f1, f2
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test1
-; CHECK-LE: xsmuldp 1, 1, 2
+; CHECK-LE: xsmuldp f1, f1, f2
 ; CHECK-LE: blr
 }
 
 define double @test2(double %a, double %b) {
 entry:
   %v = fdiv double %a, %b
   ret double %v
 
 ; CHECK-LABEL: @test2
-; CHECK: xsdivdp 1, 1, 2
+; CHECK: xsdivdp f1, f1, f2
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test2
-; CHECK-LE: xsdivdp 1, 1, 2
+; CHECK-LE: xsdivdp f1, f1, f2
 ; CHECK-LE: blr
 }
 
 define double @test3(double %a, double %b) {
 entry:
   %v = fadd double %a, %b
   ret double %v
 
 ; CHECK-LABEL: @test3
-; CHECK: xsadddp 1, 1, 2
+; CHECK: xsadddp f1, f1, f2
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test3
-; CHECK-LE: xsadddp 1, 1, 2
+; CHECK-LE: xsadddp f1, f1, f2
 ; CHECK-LE: blr
 }
 
 define <2 x double> @test4(<2 x double> %a, <2 x double> %b) {
 entry:
   %v = fadd <2 x double> %a, %b
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test4
-; CHECK: xvadddp 34, 34, 35
+; CHECK: xvadddp v2, v2, v3
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test4
-; CHECK-LE: xvadddp 34, 34, 35
+; CHECK-LE: xvadddp v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
 entry:
   %v = xor <4 x i32> %a, %b
   ret <4 x i32> %v
 
 ; CHECK-REG-LABEL: @test5
-; CHECK-REG: xxlxor 34, 34, 35
+; CHECK-REG: xxlxor v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test5
-; CHECK-FISL: xxlxor 34, 34, 35
+; CHECK-FISL: xxlxor v2, v2, v3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test5
-; CHECK-LE: xxlxor 34, 34, 35
+; CHECK-LE: xxlxor v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
 entry:
   %v = xor <8 x i16> %a, %b
   ret <8 x i16> %v
 
 ; CHECK-REG-LABEL: @test6
-; CHECK-REG: xxlxor 34, 34, 35
+; CHECK-REG: xxlxor v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test6
-; CHECK-FISL: xxlxor 34, 34, 35
+; CHECK-FISL: xxlxor v2, v2, v3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test6
-; CHECK-LE: xxlxor 34, 34, 35
+; CHECK-LE: xxlxor v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {
 entry:
   %v = xor <16 x i8> %a, %b
   ret <16 x i8> %v
 
 ; CHECK-REG-LABEL: @test7
-; CHECK-REG: xxlxor 34, 34, 35
+; CHECK-REG: xxlxor v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test7
-; CHECK-FISL: xxlxor 34, 34, 35
+; CHECK-FISL: xxlxor v2, v2, v3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test7
-; CHECK-LE: xxlxor 34, 34, 35
+; CHECK-LE: xxlxor v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {
 entry:
   %v = or <4 x i32> %a, %b
   ret <4 x i32> %v
 
 ; CHECK-REG-LABEL: @test8
-; CHECK-REG: xxlor 34, 34, 35
+; CHECK-REG: xxlor v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test8
-; CHECK-FISL: xxlor 34, 34, 35
+; CHECK-FISL: xxlor v2, v2, v3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test8
-; CHECK-LE: xxlor 34, 34, 35
+; CHECK-LE: xxlor v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
 entry:
   %v = or <8 x i16> %a, %b
   ret <8 x i16> %v
 
 ; CHECK-REG-LABEL: @test9
-; CHECK-REG: xxlor 34, 34, 35
+; CHECK-REG: xxlor v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test9
-; CHECK-FISL: xxlor 34, 34, 35
+; CHECK-FISL: xxlor v2, v2, v3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test9
-; CHECK-LE: xxlor 34, 34, 35
+; CHECK-LE: xxlor v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {
 entry:
   %v = or <16 x i8> %a, %b
   ret <16 x i8> %v
 
 ; CHECK-REG-LABEL: @test10
-; CHECK-REG: xxlor 34, 34, 35
+; CHECK-REG: xxlor v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test10
-; CHECK-FISL: xxlor 34, 34, 35
+; CHECK-FISL: xxlor v2, v2, v3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test10
-; CHECK-LE: xxlor 34, 34, 35
+; CHECK-LE: xxlor v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
 entry:
   %v = and <4 x i32> %a, %b
   ret <4 x i32> %v
 
 ; CHECK-REG-LABEL: @test11
-; CHECK-REG: xxland 34, 34, 35
+; CHECK-REG: xxland v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test11
-; CHECK-FISL: xxland 34, 34, 35
+; CHECK-FISL: xxland v2, v2, v3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test11
-; CHECK-LE: xxland 34, 34, 35
+; CHECK-LE: xxland v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
 entry:
   %v = and <8 x i16> %a, %b
   ret <8 x i16> %v
 
 ; CHECK-REG-LABEL: @test12
-; CHECK-REG: xxland 34, 34, 35
+; CHECK-REG: xxland v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test12
-; CHECK-FISL: xxland 34, 34, 35
+; CHECK-FISL: xxland v2, v2, v3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test12
-; CHECK-LE: xxland 34, 34, 35
+; CHECK-LE: xxland v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {
 entry:
   %v = and <16 x i8> %a, %b
   ret <16 x i8> %v
 
 ; CHECK-REG-LABEL: @test13
-; CHECK-REG: xxland 34, 34, 35
+; CHECK-REG: xxland v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test13
-; CHECK-FISL: xxland 34, 34, 35
+; CHECK-FISL: xxland v2, v2, v3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test13
-; CHECK-LE: xxland 34, 34, 35
+; CHECK-LE: xxland v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {
 entry:
   %v = or <4 x i32> %a, %b
   %w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1>
   ret <4 x i32> %w
 
 ; CHECK-REG-LABEL: @test14
-; CHECK-REG: xxlnor 34, 34, 35
+; CHECK-REG: xxlnor v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test14
-; CHECK-FISL: xxlor 0, 34, 35
-; CHECK-FISL: xxlnor 34, 34, 35
+; CHECK-FISL: xxlor vs0, v2, v3
+; CHECK-FISL: xxlnor v2, v2, v3
 ; CHECK-FISL-NOT: lis
 ; CHECK-FISL-NOT: ori
-; CHECK-FISL: li 3, -16
+; CHECK-FISL: li r3, -16
 ; CHECK-FISL-NOT: lis
 ; CHECK-FISL-NOT: ori
-; CHECK-FISL: stxvd2x 0, 1, 3
+; CHECK-FISL: stxvd2x vs0, r1, r3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test14
-; CHECK-LE: xxlnor 34, 34, 35
+; CHECK-LE: xxlnor v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
 entry:
   %v = or <8 x i16> %a, %b
   %w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
   ret <8 x i16> %w
 
 ; CHECK-REG-LABEL: @test15
-; CHECK-REG: xxlnor 34, 34, 35
+; CHECK-REG: xxlnor v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test15
-; CHECK-FISL: xxlor 0, 34, 35
-; CHECK-FISL: xxlor 36, 0, 0
-; CHECK-FISL: xxlnor 0, 34, 35
-; CHECK-FISL: xxlor 34, 0, 0
+; CHECK-FISL: xxlor vs0, v2, v3
+; CHECK-FISL: xxlor v4, vs0, vs0
+; CHECK-FISL: xxlnor vs0, v2, v3
+; CHECK-FISL: xxlor v2, vs0, vs0
 ; CHECK-FISL-NOT: lis
 ; CHECK-FISL-NOT: ori
-; CHECK-FISL: li 3, -16
+; CHECK-FISL: li r3, -16
 ; CHECK-FISL-NOT: lis
 ; CHECK-FISL-NOT: ori
-; CHECK-FISL: stxvd2x 36, 1, 3
+; CHECK-FISL: stxvd2x v4, r1, r3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test15
-; CHECK-LE: xxlnor 34, 34, 35
+; CHECK-LE: xxlnor v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
 entry:
   %v = or <16 x i8> %a, %b
   %w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   ret <16 x i8> %w
 
 ; CHECK-REG-LABEL: @test16
-; CHECK-REG: xxlnor 34, 34, 35
+; CHECK-REG: xxlnor v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test16
-; CHECK-FISL: xxlor 0, 34, 35
-; CHECK-FISL: xxlor 36, 0, 0
-; CHECK-FISL: xxlnor 0, 34, 35
-; CHECK-FISL: xxlor 34, 0, 0
+; CHECK-FISL: xxlor vs0, v2, v3
+; CHECK-FISL: xxlor v4, vs0, vs0
+; CHECK-FISL: xxlnor vs0, v2, v3
+; CHECK-FISL: xxlor v2, vs0, vs0
 ; CHECK-FISL-NOT: lis
 ; CHECK-FISL-NOT: ori
-; CHECK-FISL: li 3, -16
+; CHECK-FISL: li r3, -16
 ; CHECK-FISL-NOT: lis
 ; CHECK-FISL-NOT: ori
-; CHECK-FISL: stxvd2x 36, 1, 3
+; CHECK-FISL: stxvd2x v4, r1, r3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test16
-; CHECK-LE: xxlnor 34, 34, 35
+; CHECK-LE: xxlnor v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
 entry:
   %w = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
   %v = and <4 x i32> %a, %w
   ret <4 x i32> %v
 
 ; CHECK-REG-LABEL: @test17
-; CHECK-REG: xxlandc 34, 34, 35
+; CHECK-REG: xxlandc v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test17
-; CHECK-FISL: xxlnor 35, 35, 35
-; CHECK-FISL: xxland 34, 34, 35
+; CHECK-FISL: xxlnor v3, v3, v3
+; CHECK-FISL: xxland v2, v2, v3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test17
-; CHECK-LE: xxlandc 34, 34, 35
+; CHECK-LE: xxlandc v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
 entry:
   %w = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
   %v = and <8 x i16> %a, %w
   ret <8 x i16> %v
 
 ; CHECK-REG-LABEL: @test18
-; CHECK-REG: xxlandc 34, 34, 35
+; CHECK-REG: xxlandc v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test18
-; CHECK-FISL: xxlnor 0, 35, 35
-; CHECK-FISL: xxlor 36, 0, 0
-; CHECK-FISL: xxlandc 0, 34, 35
-; CHECK-FISL: xxlor 34, 0, 0
+; CHECK-FISL: xxlnor vs0, v3, v3
+; CHECK-FISL: xxlor v4, vs0, vs0
+; CHECK-FISL: xxlandc vs0, v2, v3
+; CHECK-FISL: xxlor v2, vs0, vs0
 ; CHECK-FISL-NOT: lis
 ; CHECK-FISL-NOT: ori
-; CHECK-FISL: li 3, -16
+; CHECK-FISL: li r3, -16
 ; CHECK-FISL-NOT: lis
 ; CHECK-FISL-NOT: ori
-; CHECK-FISL: stxvd2x 36, 1, 3
+; CHECK-FISL: stxvd2x v4, r1, r3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test18
-; CHECK-LE: xxlandc 34, 34, 35
+; CHECK-LE: xxlandc v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
 entry:
   %w = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   %v = and <16 x i8> %a, %w
   ret <16 x i8> %v
 
 ; CHECK-REG-LABEL: @test19
-; CHECK-REG: xxlandc 34, 34, 35
+; CHECK-REG: xxlandc v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test19
-; CHECK-FISL: xxlnor 0, 35, 35
-; CHECK-FISL: xxlor 36, 0, 0
-; CHECK-FISL: xxlandc 0, 34, 35
-; CHECK-FISL: xxlor 34, 0, 0
+; CHECK-FISL: xxlnor vs0, v3, v3
+; CHECK-FISL: xxlor v4, vs0, vs0
+; CHECK-FISL: xxlandc vs0, v2, v3
+; CHECK-FISL: xxlor v2, vs0, vs0
 ; CHECK-FISL-NOT: lis
 ; CHECK-FISL-NOT: ori
-; CHECK-FISL: li 3, -16
+; CHECK-FISL: li r3, -16
 ; CHECK-FISL-NOT: lis
 ; CHECK-FISL-NOT: ori
-; CHECK-FISL: stxvd2x 36, 1, 3
+; CHECK-FISL: stxvd2x v4, r1, r3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test19
-; CHECK-LE: xxlandc 34, 34, 35
+; CHECK-LE: xxlandc v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
 entry:
   %m = icmp eq <4 x i32> %c, %d
   %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
   ret <4 x i32> %v
 
 ; CHECK-REG-LABEL: @test20
-; CHECK-REG: vcmpequw {{[0-9]+}}, 4, 5
-; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-REG: vcmpequw v4, v4, v5
+; CHECK-REG: xxsel v2, v3, v2, v4
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test20
-; CHECK-FISL: vcmpequw {{[0-9]+}}, 4, 5
-; CHECK-FISL: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-FISL: vcmpequw v4, v4, v5
+; CHECK-FISL: xxsel v2, v3, v2, v4
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test20
-; CHECK-LE: vcmpequw {{[0-9]+}}, 4, 5
-; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-LE: vcmpequw v4, v4, v5
+; CHECK-LE: xxsel v2, v3, v2, v4
 ; CHECK-LE: blr
 }
 
 define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
 entry:
   %m = fcmp oeq <4 x float> %c, %d
   %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
   ret <4 x float> %v
 
 ; CHECK-REG-LABEL: @test21
-; CHECK-REG: xvcmpeqsp [[V1:[0-9]+]], 36, 37
-; CHECK-REG: xxsel 34, 35, 34, [[V1]]
+; CHECK-REG: xvcmpeqsp vs0, v4, v5
+; CHECK-REG: xxsel v2, v3, v2, vs0
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test21
-; CHECK-FISL: xvcmpeqsp [[V1:[0-9]+]], 36, 37
-; CHECK-FISL: xxsel 34, 35, 34, [[V1]]
+; CHECK-FISL: xvcmpeqsp v4, v4, v5
+; CHECK-FISL: xxsel v2, v3, v2, v4
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test21
-; CHECK-LE: xvcmpeqsp [[V1:[0-9]+]], 36, 37
-; CHECK-LE: xxsel 34, 35, 34, [[V1]]
+; CHECK-LE: xvcmpeqsp vs0, v4, v5
+; CHECK-LE: xxsel v2, v3, v2, vs0
 ; CHECK-LE: blr
 }
 
 define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
 entry:
   %m = fcmp ueq <4 x float> %c, %d
   %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
   ret <4 x float> %v
 
 ; CHECK-REG-LABEL: @test22
-; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
-; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
-; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
-; CHECK-REG-DAG: xxlnor
-; CHECK-REG-DAG: xxlnor
-; CHECK-REG-DAG: xxlor
-; CHECK-REG-DAG: xxlor
-; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-REG-DAG: xvcmpeqsp vs0, v5, v5
+; CHECK-REG-DAG: xvcmpeqsp vs1, v4, v4
+; CHECK-REG-DAG: xvcmpeqsp vs2, v4, v5
+; CHECK-REG-DAG: xxlnor vs0, vs0, vs0
+; CHECK-REG-DAG: xxlnor vs1, vs1, vs1
+; CHECK-REG-DAG: xxlor vs0, vs1, vs0
+; CHECK-REG-DAG: xxlor vs0, vs2, vs0
+; CHECK-REG: xxsel v2, v3, v2, vs0
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test22
-; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
-; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
-; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
-; CHECK-FISL-DAG: xxlnor
-; CHECK-FISL-DAG: xxlnor
-; CHECK-FISL-DAG: xxlor
-; CHECK-FISL-DAG: xxlor
-; CHECK-FISL: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-FISL-DAG: xvcmpeqsp vs0, v4, v5
+; CHECK-FISL-DAG: xvcmpeqsp v5, v5, v5
+; CHECK-FISL-DAG: xvcmpeqsp v4, v4, v4
+; CHECK-FISL-DAG: xxlnor v5, v5, v5
+; CHECK-FISL-DAG: xxlnor v4, v4, v4
+; CHECK-FISL-DAG: xxlor v4, v4, v5
+; CHECK-FISL-DAG: xxlor vs0, vs0, v4
+; CHECK-FISL: xxsel v2, v3, v2, vs0
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test22
-; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
-; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
-; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
-; CHECK-LE-DAG: xxlnor
-; CHECK-LE-DAG: xxlnor
-; CHECK-LE-DAG: xxlor
-; CHECK-LE-DAG: xxlor
-; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-LE-DAG: xvcmpeqsp vs0, v5, v5
+; CHECK-LE-DAG: xvcmpeqsp vs1, v4, v4
+; CHECK-LE-DAG: xvcmpeqsp vs2, v4, v5
+; CHECK-LE-DAG: xxlnor vs0, vs0, vs0
+; CHECK-LE-DAG: xxlnor vs1, vs1, vs1
+; CHECK-LE-DAG: xxlor vs0, vs1, vs0
+; CHECK-LE-DAG: xxlor vs0, vs2, vs0
+; CHECK-LE: xxsel v2, v3, v2, vs0
 ; CHECK-LE: blr
 }
 
 define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
 entry:
   %m = icmp eq <8 x i16> %c, %d
   %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
   ret <8 x i16> %v
 
 ; CHECK-REG-LABEL: @test23
-; CHECK-REG: vcmpequh {{[0-9]+}}, 4, 5
-; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-REG: vcmpequh v4, v4, v5
+; CHECK-REG: xxsel v2, v3, v2, v4
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test23
-; CHECK-FISL: vcmpequh 4, 4, 5
-; CHECK-FISL: xxsel 34, 35, 34, 36
+; CHECK-FISL: vcmpequh v4, v4, v5
+; CHECK-FISL: xxsel v2, v3, v2, v4
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test23
-; CHECK-LE: vcmpequh {{[0-9]+}}, 4, 5
-; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-LE: vcmpequh v4, v4, v5
+; CHECK-LE: xxsel v2, v3, v2, v4
 ; CHECK-LE: blr
 }
 
 define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
 entry:
   %m = icmp eq <16 x i8> %c, %d
   %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
   ret <16 x i8> %v
 
 ; CHECK-REG-LABEL: @test24
-; CHECK-REG: vcmpequb {{[0-9]+}}, 4, 5
-; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-REG: vcmpequb v4, v4, v5
+; CHECK-REG: xxsel v2, v3, v2, v4
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test24
-; CHECK-FISL: vcmpequb 4, 4, 5
-; CHECK-FISL: xxsel 34, 35, 34, 36
+; CHECK-FISL: vcmpequb v4, v4, v5
+; CHECK-FISL: xxsel v2, v3, v2, v4
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test24
-; CHECK-LE: vcmpequb {{[0-9]+}}, 4, 5
-; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-LE: vcmpequb v4, v4, v5
+; CHECK-LE: xxsel v2, v3, v2, v4
 ; CHECK-LE: blr
 }
 
 define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
 entry:
   %m = fcmp oeq <2 x double> %c, %d
   %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test25
-; CHECK: xvcmpeqdp [[V1:[0-9]+]], 36, 37
-; CHECK: xxsel 34, 35, 34, [[V1]]
+; CHECK: xvcmpeqdp v4, v4, v5
+; CHECK: xxsel v2, v3, v2, vs0
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test25
-; CHECK-LE: xvcmpeqdp [[V1:[0-9]+]], 36, 37
-; CHECK-LE: xxsel 34, 35, 34, [[V1]]
+; CHECK-LE: xvcmpeqdp v4, v4, v5
+; CHECK-LE: xxsel v2, v3, v2, v4
 ; CHECK-LE: blr
 }
 
 define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
   %v = add <2 x i64> %a, %b
   ret <2 x i64> %v
 
 ; CHECK-LABEL: @test26
 
 ; Make sure we use only two stores (one for each operand).
-; CHECK: stxvd2x 35,
-; CHECK: stxvd2x 34,
+; CHECK: stxvd2x v3, 0, r3
+; CHECK: stxvd2x v2, 0, r4
 ; CHECK-NOT: stxvd2x
 
 ; FIXME: The code quality here is not good; just make sure we do something for now.
-; CHECK: add
-; CHECK: add
+; CHECK: add r3, r4, r3
+; CHECK: add r3, r4, r3
 ; CHECK: blr
 
-; CHECK-LE: vaddudm 2, 2, 3
+; CHECK-LE: vaddudm v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {
   %v = and <2 x i64> %a, %b
   ret <2 x i64> %v
 
 ; CHECK-LABEL: @test27
-; CHECK: xxland 34, 34, 35
+; CHECK: xxland v2, v2, v3
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test27
-; CHECK-LE: xxland 34, 34, 35
+; CHECK-LE: xxland v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <2 x double> @test28(<2 x double>* %a) {
   %v = load <2 x double>, <2 x double>* %a, align 16
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test28
-; CHECK: lxvd2x 34, 0, 3
+; CHECK: lxvd2x v2, 0, r3
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test28
-; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
-; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: lxvd2x vs0, 0, r3
+; CHECK-LE: xxswapd v2, vs0
 ; CHECK-LE: blr
 }
 
 define void @test29(<2 x double>* %a, <2 x double> %b) {
   store <2 x double> %b, <2 x double>* %a, align 16
   ret void
 
 ; CHECK-LABEL: @test29
-; CHECK: stxvd2x 34, 0, 3
+; CHECK: stxvd2x v2, 0, r3
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test29
-; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
-; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: xxswapd vs0, v2
+; CHECK-LE: stxvd2x vs0, 0, r3
 ; CHECK-LE: blr
 }
 
 define <2 x double> @test28u(<2 x double>* %a) {
   %v = load <2 x double>, <2 x double>* %a, align 8
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test28u
-; CHECK: lxvd2x 34, 0, 3
+; CHECK: lxvd2x v2, 0, r3
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test28u
-; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
-; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: lxvd2x vs0, 0, r3
+; CHECK-LE: xxswapd v2, vs0
 ; CHECK-LE: blr
 }
 
 define void @test29u(<2 x double>* %a, <2 x double> %b) {
   store <2 x double> %b, <2 x double>* %a, align 8
   ret void
 
 ; CHECK-LABEL: @test29u
-; CHECK: stxvd2x 34, 0, 3
+; CHECK: stxvd2x v2, 0, r3
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test29u
-; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
-; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: xxswapd vs0, v2
+; CHECK-LE: stxvd2x vs0, 0, r3
 ; CHECK-LE: blr
 }
 
 define <2 x i64> @test30(<2 x i64>* %a) {
   %v = load <2 x i64>, <2 x i64>* %a, align 16
   ret <2 x i64> %v
 
 ; CHECK-REG-LABEL: @test30
-; CHECK-REG: lxvd2x 34, 0, 3
+; CHECK-REG: lxvd2x v2, 0, r3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test30
-; CHECK-FISL: lxvd2x 0, 0, 3
-; CHECK-FISL: xxlor 34, 0, 0
+; CHECK-FISL: lxvd2x vs0, 0, r3
+; CHECK-FISL: xxlor v2, vs0, vs0
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test30
-; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
-; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: lxvd2x vs0, 0, r3
+; CHECK-LE: xxswapd v2, vs0
 ; CHECK-LE: blr
 }
 
 define void @test31(<2 x i64>* %a, <2 x i64> %b) {
   store <2 x i64> %b, <2 x i64>* %a, align 16
   ret void
 
 ; CHECK-LABEL: @test31
-; CHECK: stxvd2x 34, 0, 3
+; CHECK: stxvd2x v2, 0, r3
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test31
-; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
-; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: xxswapd vs0, v2
+; CHECK-LE: stxvd2x vs0, 0, r3
 ; CHECK-LE: blr
 }
 
 define <4 x float> @test32(<4 x float>* %a) {
   %v = load <4 x float>, <4 x float>* %a, align 16
   ret <4 x float> %v
 
 ; CHECK-REG-LABEL: @test32
-; CHECK-REG: lxvw4x 34, 0, 3
+; CHECK-REG: lxvw4x v2, 0, r3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test32
-; CHECK-FISL: lxvw4x 34, 0, 3
+; CHECK-FISL: lxvw4x v2, 0, r3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test32
-; CHECK-LE: lvx 2, 0, 3
+; CHECK-LE: lvx v2, 0, r3
 ; CHECK-LE-NOT: xxswapd
 ; CHECK-LE: blr
 }
 
 define void @test33(<4 x float>* %a, <4 x float> %b) {
   store <4 x float> %b, <4 x float>* %a, align 16
   ret void
 
 ; CHECK-REG-LABEL: @test33
-; CHECK-REG: stxvw4x 34, 0, 3
+; CHECK-REG: stxvw4x v2, 0, r3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test33
-; CHECK-FISL: stxvw4x 34, 0, 3
+; CHECK-FISL: stxvw4x v2, 0, r3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test33
 ; CHECK-LE-NOT: xxswapd
-; CHECK-LE: stvx 2, 0, 3
+; CHECK-LE: stvx v2, 0, r3
 ; CHECK-LE: blr
 }
 
 define <4 x float> @test32u(<4 x float>* %a) {
   %v = load <4 x float>, <4 x float>* %a, align 8
   ret <4 x float> %v
 
 ; CHECK-LABEL: @test32u
-; CHECK-DAG: lvsl
-; CHECK-DAG: lvx
-; CHECK-DAG: lvx
-; CHECK: vperm 2,
+; CHECK-DAG: lvsl v3, 0, r3
+; CHECK-DAG: lvx v2, r3, r4
+; CHECK-DAG: lvx v4, 0, r3
+; CHECK: vperm v2, v4, v2, v3
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test32u
-; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
-; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: lxvd2x vs0, 0, r3
+; CHECK-LE: xxswapd v2, vs0
 ; CHECK-LE: blr
 }
 
 define void @test33u(<4 x float>* %a, <4 x float> %b) {
   store <4 x float> %b, <4 x float>* %a, align 8
   ret void
 
 ; CHECK-REG-LABEL: @test33u
-; CHECK-REG: stxvw4x 34, 0, 3
+; CHECK-REG: stxvw4x v2, 0, r3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test33u
-; CHECK-FISL: stxvw4x 34, 0, 3
+; CHECK-FISL: stxvw4x v2, 0, r3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test33u
-; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
-; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: xxswapd vs0, v2
+; CHECK-LE: stxvd2x vs0, 0, r3
 ; CHECK-LE: blr
 }
 
 define <4 x i32> @test34(<4 x i32>* %a) {
   %v = load <4 x i32>, <4 x i32>* %a, align 16
   ret <4 x i32> %v
 
 ; CHECK-REG-LABEL: @test34
-; CHECK-REG: lxvw4x 34, 0, 3
+; CHECK-REG: lxvw4x v2, 0, r3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test34
-; CHECK-FISL: lxvw4x 34, 0, 3
+; CHECK-FISL: lxvw4x v2, 0, r3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test34
-; CHECK-LE: lvx 2, 0, 3
+; CHECK-LE: lvx v2, 0, r3
 ; CHECK-LE-NOT: xxswapd
 ; CHECK-LE: blr
 }
 
 define void @test35(<4 x i32>* %a, <4 x i32> %b) {
   store <4 x i32> %b, <4 x i32>* %a, align 16
   ret void
 
 ; CHECK-REG-LABEL: @test35
-; CHECK-REG: stxvw4x 34, 0, 3
+; CHECK-REG: stxvw4x v2, 0, r3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test35
-; CHECK-FISL: stxvw4x 34, 0, 3
+; CHECK-FISL: stxvw4x v2, 0, r3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test35
 ; CHECK-LE-NOT: xxswapd
-; CHECK-LE: stvx 2, 0, 3
+; CHECK-LE: stvx v2, 0, r3
 ; CHECK-LE: blr
 }
 
 define <2 x double> @test40(<2 x i64> %a) {
   %v = uitofp <2 x i64> %a to <2 x double>
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test40
-; CHECK: xvcvuxddp 34, 34
+; CHECK: xvcvuxddp v2, v2
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test40
-; CHECK-LE: xvcvuxddp 34, 34
+; CHECK-LE: xvcvuxddp v2, v2
 ; CHECK-LE: blr
 }
 
 define <2 x double> @test41(<2 x i64> %a) {
   %v = sitofp <2 x i64> %a to <2 x double>
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test41
-; CHECK: xvcvsxddp 34, 34
+; CHECK: xvcvsxddp v2, v2
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test41
-; CHECK-LE: xvcvsxddp 34, 34
+; CHECK-LE: xvcvsxddp v2, v2
 ; CHECK-LE: blr
 }
 
 define <2 x i64> @test42(<2 x double> %a) {
   %v = fptoui <2 x double> %a to <2 x i64>
   ret <2 x i64> %v
 
 ; CHECK-LABEL: @test42
-; CHECK: xvcvdpuxds 34, 34
+; CHECK: xvcvdpuxds v2, v2
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test42
-; CHECK-LE: xvcvdpuxds 34, 34
+; CHECK-LE: xvcvdpuxds v2, v2
 ; CHECK-LE: blr
 }
 
 define <2 x i64> @test43(<2 x double> %a) {
   %v = fptosi <2 x double> %a to <2 x i64>
   ret <2 x i64> %v
 
 ; CHECK-LABEL: @test43
-; CHECK: xvcvdpsxds 34, 34
+; CHECK: xvcvdpsxds v2, v2
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test43
-; CHECK-LE: xvcvdpsxds 34, 34
+; CHECK-LE: xvcvdpsxds v2, v2
 ; CHECK-LE: blr
 }
 
 define <2 x float> @test44(<2 x i64> %a) {
   %v = uitofp <2 x i64> %a to <2 x float>
   ret <2 x float> %v
 
 ; CHECK-LABEL: @test44
 ; FIXME: The code quality here looks pretty bad.
 ; CHECK: blr
+; CHECK-LE-LABEL: @test44
+; CHECK-LE: xxswapd vs0, v2
+; CHECK-LE: xxlor vs1, v2, v2
+; CHECK-LE: xscvuxdsp f1, f1
+; CHECK-LE: xscvuxdsp f0, f0
+; CHECK-LE: xscvdpspn vs1, f1
+; CHECK-LE: xscvdpspn vs0, f0
+; CHECK-LE: xxsldwi v3, vs1, vs1, 1
+; CHECK-LE: xxsldwi v2, vs0, vs0, 1
+; CHECK-LE: vmrglw v2, v3, v2
+; CHECK-LE: blr
 }
 
 define <2 x float> @test45(<2 x i64> %a) {
   %v = sitofp <2 x i64> %a to <2 x float>
   ret <2 x float> %v
 
 ; CHECK-LABEL: @test45
 ; FIXME: The code quality here looks pretty bad.
 ; CHECK: blr
+; CHECK-LE-LABEL: @test45
+; CHECK-LE: blr
 }
 
 define <2 x i64> @test46(<2 x float> %a) {
   %v = fptoui <2 x float> %a to <2 x i64>
   ret <2 x i64> %v
 
 ; CHECK-LABEL: @test46
 ; FIXME: The code quality here looks pretty bad.

 
 define <2 x double> @test50(double* %a) {
   %v = load double, double* %a, align 8
   %w = insertelement <2 x double> undef, double %v, i32 0
   %x = insertelement <2 x double> %w, double %v, i32 1
   ret <2 x double> %x
 
 ; CHECK-LABEL: @test50
-; CHECK: lxvdsx 34, 0, 3
+; CHECK: lxvdsx v2, 0, r3
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test50
-; CHECK-LE: lxvdsx 34, 0, 3
+; CHECK-LE: lxvdsx v2, 0, r3
 ; CHECK-LE: blr
 }
 
 define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
   %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 0>
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test51
-; CHECK: xxspltd 34, 34, 0
+; CHECK: xxspltd v2, v2, 0
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test51
-; CHECK-LE: xxspltd 34, 34, 1
+; CHECK-LE: xxspltd v2, v2, 1
 ; CHECK-LE: blr
 }
 
 define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
   %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2>
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test52
-; CHECK: xxmrghd 34, 34, 35
+; CHECK: xxmrghd v2, v2, v3
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test52
-; CHECK-LE: xxmrgld 34, 35, 34
+; CHECK-LE: xxmrgld v2, v3, v2
 ; CHECK-LE: blr
 }
 
 define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
   %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 2, i32 0>
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test53
-; CHECK: xxmrghd 34, 35, 34
+; CHECK: xxmrghd v2, v3, v2
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test53
-; CHECK-LE: xxmrgld 34, 34, 35
+; CHECK-LE: xxmrgld v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <2 x double> @test54(<2 x double> %a, <2 x double> %b) {
   %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2>
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test54
-; CHECK: xxpermdi 34, 34, 35, 2
+; CHECK: xxpermdi v2, v2, v3, 2
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test54
-; CHECK-LE: xxpermdi 34, 35, 34, 2
+; CHECK-LE: xxpermdi v2, v3, v2, 2
 ; CHECK-LE: blr
 }
 
 define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
   %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3>
   ret <2 x double> %v
 
 ; CHECK-LABEL: @test55
-; CHECK: xxmrgld 34, 34, 35
+; CHECK: xxmrgld v2, v2, v3
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test55
-; CHECK-LE: xxmrghd 34, 35, 34
+; CHECK-LE: xxmrghd v2, v3, v2
 ; CHECK-LE: blr
 }
 
 define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
   %v = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
   ret <2 x i64> %v
 
 ; CHECK-LABEL: @test56
-; CHECK: xxmrgld 34, 34, 35
+; CHECK: xxmrgld v2, v2, v3
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test56
-; CHECK-LE: xxmrghd 34, 35, 34
+; CHECK-LE: xxmrghd v2, v3, v2
 ; CHECK-LE: blr
 }
 
 define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
   %v = shl <2 x i64> %a, %b
   ret <2 x i64> %v
 
 ; CHECK-LABEL: @test60
 ; This should scalarize, and the current code quality is not good.
-; CHECK: stxvd2x
-; CHECK: stxvd2x
-; CHECK: sld
-; CHECK: sld
-; CHECK: lxvd2x
+; CHECK: stxvd2x v3, 0, r3
+; CHECK: stxvd2x v2, 0, r4
+; CHECK: sld r3, r4, r3
+; CHECK: sld r3, r4, r3
+; CHECK: lxvd2x v2, 0, r3
 ; CHECK: blr
 }
 
 define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) {
   %v = lshr <2 x i64> %a, %b
   ret <2 x i64> %v
 
 ; CHECK-LABEL: @test61
 ; This should scalarize, and the current code quality is not good.
-; CHECK: stxvd2x
-; CHECK: stxvd2x
-; CHECK: srd
-; CHECK: srd
-; CHECK: lxvd2x
+; CHECK: stxvd2x v3, 0, r3
+; CHECK: stxvd2x v2, 0, r4
+; CHECK: srd r3, r4, r3
+; CHECK: srd r3, r4, r3
+; CHECK: lxvd2x v2, 0, r3
 ; CHECK: blr
 }
 
 define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
   %v = ashr <2 x i64> %a, %b
   ret <2 x i64> %v
 
 ; CHECK-LABEL: @test62
 ; This should scalarize, and the current code quality is not good.
-; CHECK: stxvd2x
-; CHECK: stxvd2x
-; CHECK: srad
-; CHECK: srad
-; CHECK: lxvd2x
+; CHECK: stxvd2x v3, 0, r3
+; CHECK: stxvd2x v2, 0, r4
+; CHECK: srad r3, r4, r3
+; CHECK: srad r3, r4, r3
+; CHECK: lxvd2x v2, 0, r3
 ; CHECK: blr
 }
 
 define double @test63(<2 x double> %a) {
   %v = extractelement <2 x double> %a, i32 0
   ret double %v
 
 ; CHECK-REG-LABEL: @test63
-; CHECK-REG: xxlor 1, 34, 34
+; CHECK-REG: xxlor f1, v2, v2
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test63
-; CHECK-FISL: xxlor 0, 34, 34
-; CHECK-FISL: fmr 1, 0
+; CHECK-FISL: xxlor f0, v2, v2
+; CHECK-FISL: fmr f1, f0
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test63
-; CHECK-LE: xxswapd 1, 34
+; CHECK-LE: xxswapd vs1, v2
 ; CHECK-LE: blr
 }
 
 define double @test64(<2 x double> %a) {
   %v = extractelement <2 x double> %a, i32 1
   ret double %v
 
 ; CHECK-REG-LABEL: @test64
-; CHECK-REG: xxswapd 1, 34
+; CHECK-REG: xxswapd vs1, v2
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test64
-; CHECK-FISL: xxswapd  34, 34
-; CHECK-FISL: xxlor 0, 34, 34
-; CHECK-FISL: fmr 1, 0
+; CHECK-FISL: xxswapd v2, v2
+; CHECK-FISL: xxlor f0, v2, v2
+; CHECK-FISL: fmr f1, f0
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test64
-; CHECK-LE: xxlor 1, 34, 34
+; CHECK-LE: xxlor f1, v2, v2
+; CHECK-LE: blr
 }
 
 define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
   %w = icmp eq <2 x i64> %a, %b
   ret <2 x i1> %w
 
 ; CHECK-REG-LABEL: @test65
-; CHECK-REG: vcmpequw 2, 2, 3
+; CHECK-REG: vcmpequw v2, v2, v3
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test65
-; CHECK-FISL: vcmpequw 2, 2, 3
+; CHECK-FISL: vcmpequw v2, v2, v3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test65
-; CHECK-LE: vcmpequd 2, 2, 3
+; CHECK-LE: vcmpequd v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
   %w = icmp ne <2 x i64> %a, %b
   ret <2 x i1> %w
 
 ; CHECK-REG-LABEL: @test66
-; CHECK-REG: vcmpequw {{[0-9]+}}, 2, 3
-; CHECK-REG: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
+; CHECK-REG: vcmpequw v2, v2, v3
+; CHECK-REG: xxlnor v2, v2, v2
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test66
-; CHECK-FISL: vcmpequw 2, 2, 3
-; CHECK-FISL: xxlnor 34, 34, 34
+; CHECK-FISL: vcmpequw v2, v2, v3
+; CHECK-FISL: xxlnor v2, v2, v2
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test66
-; CHECK-LE: vcmpequd {{[0-9]+}}, 2, 3
-; CHECK-LE: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
+; CHECK-LE: vcmpequd v2, v2, v3
+; CHECK-LE: xxlnor v2, v2, v2
 ; CHECK-LE: blr
 }
 
 define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
   %w = icmp ult <2 x i64> %a, %b
   ret <2 x i1> %w
 
 ; CHECK-LABEL: @test67
 ; This should scalarize, and the current code quality is not good.
-; CHECK: stxvd2x
-; CHECK: stxvd2x
-; CHECK: cmpld
-; CHECK: cmpld
-; CHECK: lxvd2x
+; CHECK: stxvd2x v3, 0, r3
+; CHECK: stxvd2x v2, 0, r4
+; CHECK: cmpld r4, r3
+; CHECK: cmpld r6, r5
+; CHECK: lxvd2x v2, 0, r3
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test67
-; CHECK-LE: vcmpgtud 2, 3, 2
+; CHECK-LE: vcmpgtud v2, v3, v2
 ; CHECK-LE: blr
 }
 
 define <2 x double> @test68(<2 x i32> %a) {
   %w = sitofp <2 x i32> %a to <2 x double>
   ret <2 x double> %w
 
 ; CHECK-LABEL: @test68
-; CHECK: xxmrghw [[V1:[0-9]+]]
-; CHECK: xvcvsxwdp 34, [[V1]]
+; CHECK: xxmrghw vs0, v2, v2
+; CHECK: xvcvsxwdp v2, vs0
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test68
-; CHECK-LE: xxmrglw [[V1:[0-9]+]], 34, 34
-; CHECK-LE: xvcvsxwdp 34, [[V1]]
+; CHECK-LE: xxmrglw v2, v2, v2
+; CHECK-LE: xvcvsxwdp v2, v2
 ; CHECK-LE: blr
 }
 
 ; This gets scalarized so the code isn't great
 define <2 x double> @test69(<2 x i16> %a) {
   %w = sitofp <2 x i16> %a to <2 x double>
   ret <2 x double> %w
 
 ; CHECK-LABEL: @test69
-; CHECK-DAG: lfiwax
-; CHECK-DAG: lfiwax
-; CHECK-DAG: xscvsxddp
-; CHECK-DAG: xscvsxddp
-; CHECK: xxmrghd
+; CHECK-DAG: lfiwax f0, 0, r3
+; CHECK-DAG: lfiwax f1, 0, r3
+; CHECK-DAG: xscvsxddp f0, f0
+; CHECK-DAG: xscvsxddp f1, f1
+; CHECK: xxmrghd v2, vs1, vs0
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test69
 ; CHECK-LE: mfvsrd
 ; CHECK-LE: mtvsrwa
 ; CHECK-LE: mtvsrwa
 ; CHECK-LE: xscvsxddp
 ; CHECK-LE: xscvsxddp
 ; CHECK-LE: xxmrghd
 ; CHECK-LE: blr
 }
 
 ; This gets scalarized so the code isn't great
 define <2 x double> @test70(<2 x i8> %a) {
   %w = sitofp <2 x i8> %a to <2 x double>
   ret <2 x double> %w
 
 ; CHECK-LABEL: @test70
-; CHECK-DAG: lfiwax
-; CHECK-DAG: lfiwax
-; CHECK-DAG: xscvsxddp
-; CHECK-DAG: xscvsxddp
-; CHECK: xxmrghd
+; CHECK-DAG: lfiwax f0, 0, r3
+; CHECK-DAG: lfiwax f1, 0, r3
+; CHECK-DAG: xscvsxddp f0, f0
+; CHECK-DAG: xscvsxddp f1, f1
+; CHECK: xxmrghd v2, vs1, vs0
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test70
 ; CHECK-LE: mfvsrd
 ; CHECK-LE: mtvsrwa
 ; CHECK-LE: mtvsrwa
 ; CHECK-LE: xscvsxddp
 ; CHECK-LE: xscvsxddp
 ; CHECK-LE: xxmrghd
 ; CHECK-LE: blr
 }
 
 ; This gets scalarized so the code isn't great
 define <2 x i32> @test80(i32 %v) {
   %b1 = insertelement <2 x i32> undef, i32 %v, i32 0
   %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
   %i = add <2 x i32> %b2, <i32 2, i32 3>
   ret <2 x i32> %i
 
 ; CHECK-REG-LABEL: @test80
-; CHECK-REG-DAG: stw 3, -16(1)
-; CHECK-REG-DAG: addi [[R1:[0-9]+]], 1, -16
-; CHECK-REG: addis [[R2:[0-9]+]]
-; CHECK-REG-DAG: addi [[R2]], [[R2]]
-; CHECK-REG-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]]
-; CHECK-REG-DAG: lxvw4x 35, 0, [[R2]]
-; CHECK-REG: xxspltw 34, [[VS1]], 0
-; CHECK-REG: vadduwm 2, 2, 3
+; CHECK-REG-DAG: stw r3, -16(r1)
+; CHECK-REG-DAG: addi r4, r1, -16
+; CHECK-REG: addis r3, r2, .LCPI65_0@toc@ha
+; CHECK-REG-DAG: addi r3, r3, .LCPI65_0@toc@l
+; CHECK-REG-DAG: lxvw4x vs0, 0, r4
+; CHECK-REG-DAG: lxvw4x v3, 0, r3
+; CHECK-REG: xxspltw v2, vs0, 0
+; CHECK-REG: vadduwm v2, v2, v3
 ; CHECK-REG-NOT: stxvw4x
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test80
-; CHECK-FISL: mr 4, 3
-; CHECK-FISL: stw 4, -16(1)
-; CHECK-FISL: addi [[R1:[0-9]+]], 1, -16
-; CHECK-FISL-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]]
-; CHECK-FISL-DAG: xxspltw {{[0-9]+}}, [[VS1]], 0
-; CHECK-FISL: addis [[R2:[0-9]+]]
-; CHECK-FISL: addi [[R2]], [[R2]]
-; CHECK-FISL-DAG: lxvw4x {{[0-9]+}}, 0, [[R2]]
+; CHECK-FISL: mr r4, r3
+; CHECK-FISL: stw r4, -16(r1)
+; CHECK-FISL: addi r3, r1, -16
+; CHECK-FISL-DAG: lxvw4x vs0, 0, r3
+; CHECK-FISL-DAG: xxspltw v2, vs0, 0
+; CHECK-FISL: addis r3, r2, .LCPI65_0@toc@ha
+; CHECK-FISL: addi r3, r3, .LCPI65_0@toc@l
+; CHECK-FISL-DAG: lxvw4x v3, 0, r3
 ; CHECK-FISL: vadduwm
 ; CHECK-FISL-NOT: stxvw4x
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test80
-; CHECK-LE-DAG: mtvsrd [[R1:[0-9]+]], 3
-; CHECK-LE-DAG: xxswapd  [[V1:[0-9]+]], [[R1]]
-; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI
-; CHECK-LE-DAG: lvx 3, 0, [[R2]]
-; CHECK-LE-DAG: xxspltw 34, [[V1]]
-; CHECK-LE-NOT: xxswapd 35, [[V2]]
-; CHECK-LE: vadduwm 2, 2, 3
+; CHECK-LE-DAG: mtvsrd f0, r3
+; CHECK-LE-DAG: xxswapd vs0, vs0
+; CHECK-LE-DAG: addi r3, r4, .LCPI65_0@toc@l
+; CHECK-LE-DAG: lvx v3, 0, r3
+; CHECK-LE-DAG: xxspltw v2, vs0, 3
+; CHECK-LE-NOT: xxswapd v3,
+; CHECK-LE: vadduwm v2, v2, v3
 ; CHECK-LE: blr
 }
 
 define <2 x double> @test81(<4 x float> %b) {
   %w = bitcast <4 x float> %b to <2 x double>
   ret <2 x double> %w
 
 ; CHECK-LABEL: @test81
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test81
 ; CHECK-LE: blr
 }
 
 define double @test82(double %a, double %b, double %c, double %d) {
 entry:
   %m = fcmp oeq double %c, %d
   %v = select i1 %m, double %a, double %b
   ret double %v
 
 ; CHECK-REG-LABEL: @test82
-; CHECK-REG: xscmpudp [[REG:[0-9]+]], 3, 4
-; CHECK-REG: beqlr [[REG]]
+; CHECK-REG: xscmpudp cr0, f3, f4
+; CHECK-REG: beqlr cr0
 
 ; CHECK-FISL-LABEL: @test82
-; CHECK-FISL: xscmpudp [[REG:[0-9]+]], 3, 4
-; CHECK-FISL: beq [[REG]], {{.*}}
+; CHECK-FISL: xscmpudp cr0, f3, f4
+; CHECK-FISL: beq cr0
 
 ; CHECK-LE-LABEL: @test82
-; CHECK-LE: xscmpudp [[REG:[0-9]+]], 3, 4
-; CHECK-LE: beqlr [[REG]]
+; CHECK-LE: xscmpudp cr0, f3, f4
+; CHECK-LE: beqlr cr0
 }
 
 ; Function Attrs: nounwind readnone
 define <4 x i32> @test83(i8* %a) {
   entry:
     %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %a)
-      ret <4 x i32> %0
-      ; CHECK-LABEL: test83
-      ; CHECK: lxvw4x 34, 0, 3
-      ; CHECK: blr
+; CHECK: lxvw4x v2, 0, r3
 }
 ; Function Attrs: nounwind readnone
 declare <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8*)
 
 ; Function Attrs: nounwind readnone
 define <2 x double> @test84(i8* %a) {
   entry:
     %0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %a)
-      ret <2 x double> %0
-      ; CHECK-LABEL: test84
-      ; CHECK: lxvd2x 34, 0, 3
-      ; CHECK: blr
+; CHECK: lxvd2x v2, 0, r3
 }
 ; Function Attrs: nounwind readnone
 declare <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8*)
 
 ; Function Attrs: nounwind readnone
 define void @test85(<4 x i32> %a, i8* %b) {
   entry:
     tail call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %a, i8* %b)
     ret void
-      ; CHECK-LABEL: test85
-      ; CHECK: stxvw4x 34, 0, 5
-      ; CHECK: blr
+; CHECK: stxvw4x v2, 0, r5
 }
+
 ; Function Attrs: nounwind readnone
 declare void @llvm.ppc.vsx.stxvw4x.be(<4 x i32>, i8*)
 
 ; Function Attrs: nounwind readnone
 define void @test86(<2 x double> %a, i8* %b) {
   entry:
     tail call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %a, i8* %b)
     ret void
-      ; CHECK-LABEL: test86
-      ; CHECK: stxvd2x 34, 0, 5
-      ; CHECK: blr
+; CHECK: stxvd2x v2, 0, r5
 }
 ; Function Attrs: nounwind readnone
 declare void @llvm.ppc.vsx.stxvd2x.be(<2 x double>, i8*)