AMDGPU: Force skip over s_sendmsg and exp instructions

[nhaehnle]

Summary

These instructions interact with hardware blocks outside the shader core,
and they can have "scalar" side effects even when EXEC = 0. We don't
want these scalar side effects to occur when all lanes want to skip
these instructions, so always add the execz skip branch instruction
for basic blocks that contain them.

Change-Id: Ieaeb58352e2789ffd64745603c14970c60819d44

[arsenm]

We really need to invert how this pass works

[nhaehnle]

In D48431#1139259, @arsenm wrote:

We really need to invert how this pass works

Yes. Although the code itself is really fine, isn't it? One way to think about it is that SI_MASK_BRANCH has different semantics before this pass and after this pass, and we should split it into two pseudo instructions to express this difference in semantics.

Anyway, I'd say that should be a separate change.

[arsenm]

In D48431#1141832, @nhaehnle wrote:

In D48431#1139259, @arsenm wrote:

We really need to invert how this pass works

Yes. Although the code itself is really fine, isn't it? One way to think about it is that SI_MASK_BRANCH has different semantics before this pass and after this pass, and we should split it into two pseudo instructions to express this difference in semantics.

Anyway, I'd say that should be a separate change.

I can see it being useful in the future to factor this condition into a TII->hasEffectsWhenEXECEmpty() or something like that predicate function

[nhaehnle]

Factor out SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty

[arsenm]

LGTM

lib/Target/AMDGPU/SIInsertSkips.cpp

for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end();
       // defining the register that is used by the scalar one is not executed
       // and scalar instruction will operate on undefined data. For
       // V_READFIRSTLANE/V_READLANE we should avoid predicated execution.
       if ((I->getOpcode() == AMDGPU::V_READFIRSTLANE_B32) ||
           (I->getOpcode() == AMDGPU::V_READLANE_B32)) {
         return true;
       }
 
+      // These instructions cause shader I/O that may cause hardware lockups
+      // when executed with an empty EXEC mask.
+      //
+      // Note: exp with VM = DONE = 0 is automatically skipped by hardware when
+      //       EXEC = 0, but checking for that case here seems not worth it
+      //       given the typical code patterns.
+      if ((I->getOpcode() == AMDGPU::S_SENDMSG) ||
+          (I->getOpcode() == AMDGPU::S_SENDMSGHALT) ||
+          (I->getOpcode() == AMDGPU::EXP) ||
+          (I->getOpcode() == AMDGPU::EXP_DONE))
+        return true;
+
       if (I->isInlineAsm()) {
         const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
         const char *AsmStr = I->getOperand(0).getSymbolName();
 
         // inlineasm length estimate is number of bytes assuming the longest
         // instruction.
         uint64_t MaxAsmSize = TII->getInlineAsmLength(AsmStr, *MAI);
         NumInstr += MaxAsmSize / MAI->getMaxInstLength();

test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll

 ; GCN: exp mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] vm{{$}}
 ; GCN: exp mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done vm{{$}}
 define amdgpu_kernel void @test_export_vm_i32() #0 {
   call void @llvm.amdgcn.exp.i32(i32 0, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 true)
   call void @llvm.amdgcn.exp.i32(i32 0, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 true)
   ret void
 }
 
+; GCN-LABEL: {{^}}test_if_export_f32:
+; GCN: s_cbranch_execz
+; GCN: exp
+define amdgpu_ps void @test_if_export_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 {
+  %cc = icmp eq i32 %flag, 0
+  br i1 %cc, label %end, label %exp
+
+exp:
+  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 false, i1 false)
+  br label %end
+
+end:
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_if_export_vm_f32:
+; GCN: s_cbranch_execz
+; GCN: exp
+define amdgpu_ps void @test_if_export_vm_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 {
+  %cc = icmp eq i32 %flag, 0
+  br i1 %cc, label %end, label %exp
+
+exp:
+  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 false, i1 true)
+  br label %end
+
+end:
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_if_export_done_f32:
+; GCN: s_cbranch_execz
+; GCN: exp
+define amdgpu_ps void @test_if_export_done_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 {
+  %cc = icmp eq i32 %flag, 0
+  br i1 %cc, label %end, label %exp
+
+exp:
+  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 true, i1 false)
+  br label %end
+
+end:
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_if_export_vm_done_f32:
+; GCN: s_cbranch_execz
+; GCN: exp
+define amdgpu_ps void @test_if_export_vm_done_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 {
+  %cc = icmp eq i32 %flag, 0
+  br i1 %cc, label %end, label %exp
+
+exp:
+  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 true, i1 true)
+  br label %end
+
+end:
+  ret void
+}
+
 attributes #0 = { nounwind }
 attributes #1 = { nounwind inaccessiblememonly }

test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll

 define amdgpu_gs void @test_mul24(i32 inreg %arg) {
 body:
   %tmp1 = and i32 %arg, 511
   %tmp2 = mul nuw nsw i32 %tmp1, 12288
   call void @llvm.amdgcn.s.sendmsg(i32 1, i32 %tmp2)
   ret void
 }
 
+; GCN-LABEL: {{^}}if_sendmsg:
+; GCN: s_cbranch_execz
+; GCN: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)
+define amdgpu_gs void @if_sendmsg(i32 %flag) #0 {
+  %cc = icmp eq i32 %flag, 0
+  br i1 %cc, label %sendmsg, label %end
+
+sendmsg:
+  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
+  br label %end
+
+end:
+  ret void
+}
+
 declare void @llvm.amdgcn.s.sendmsg(i32, i32) #0
 declare void @llvm.amdgcn.s.sendmsghalt(i32, i32) #0
 
 attributes #0 = { nounwind }