[PPC64] Add TLS initial exec to local exec relaxation

[syzaara]

Summary

This patch adds the target call back relaxTlsIeToLe to support TLS relaxation from initial exec to local exec model.

[ruiu]

lld/ELF/Arch/PPC64.cpp

164 ↗

(On Diff #151002)

In lld we do not take the approach that "every constant should be defined as variable" but this is perhaps a bit cross the line. Don't you have constants for these values?

[ruiu]

lld/ELF/Arch/PPC64.cpp

25 ↗

(On Diff #151192)

nit: add a blank line before any multi-line class, struct, enum, etc definitions/declarations.

It needs a comment. Is this a instruction number?

183 ↗

(On Diff #151192)

format?

184–185 ↗

(On Diff #151192)

Can you please clang-format?

202–204 ↗

(On Diff #151192)

Which does this mean, we expect the three sequential instructions or one of them?

lld/ELF/Relocations.h

47 ↗

(On Diff #151192)

I don't know if you really need to add a new type. IE→LE relaxation has already implemented for some other architectures. I wonder if you can do the same thing as others.

lld/test/ELF/ppc64-tls-ie-le.s

1 ↗

(On Diff #151192)

How did you create this file? It seems a bit too long. Can you reduce it by hand? Also, splitting to smaller test files might improve maintainability.

[syzaara]

lld/ELF/Arch/PPC64.cpp

202–204 ↗

(On Diff #151192)

These may not be sequential but are all part of the initial exec sequence and we expect each one of them to be converted into a new instruction.
The instructions:

addis r9, r2, x@got@tprel@ha
ld r9, x@got@tprel@l(r9)

are building the offset of x relative to the thread pointer by reading it from the got.
Then,

add r9, r9, x@tls

completes the address by replacing x@tls with r13 which is the thread pointer.

We will do the following replacements as started by the V2 ABI:

addis r9, r2, x@got@tprel@ha  changes into nop
ld r9, x@got@tprel@l(r9) changes into addis r9, r13, x@tprel@ha
add r9, r9, x@tls changes into addi r9, r9, x@tprel@l

This new sequence now calculates the offset of x relative to the thread pointer rather than reading it from the got.

lld/test/ELF/ppc64-tls-ie-le.s

1 ↗

(On Diff #151192)

I created this file by hand. It is composed of multiple small tests that are all related so I think it would be better if we kept them in one file. The small tests are meant to test the same relocation relaxation which has multiple options for the instruction:

lbzx -> lbz
lhzx -> lhz
lwzx -> lwz
ldx -> ld
stbx -> stb
sthx -> sth
stwx -> stw
stdx -> std
add -> addi

[syzaara]

lld/ELF/Relocations.h

47 ↗

(On Diff #151192)

I added this new type because I wanted a relocation which would get ignored similar to how R_HINT and R_NONE are, except for when handling TLS relaxations. I added R_TLS_IE_HINT as the RelExp for R_PPC64_TLS.
R_PPC64_TLS is not suppose to be evaluated into anything, it just gets replaced by r13. Currently we have R_PPC64_TLS mapped to the RelExpr R_HINT. However, for handling TLS relaxations we need to processes the R_PPC64_TLS relocation so that we can perform the relaxation of:

add r9, r9, x@tls
into
addi r9, r9, x@tprel@l

Leaving it as R_HINT causes us to skip calling relaxTlsGdToLe with R_PPC64_TLS and we are unable to do the above change since there is an early exit in scanReloc for R_HINT.

If I use the existing relocation types used for initial exec, like R_GOT_OFF, I would be evaluating it in getRelocTargetVA, just to never use it.

Adding this new type allows me to skip getRelocTargetVA for R_PPC64_TLS, while being able to handle it in the TLS relaxations.

[sfertile]

lld/ELF/Relocations.h

47 ↗

(On Diff #151705)

Maybe R_TLSIE_HINT instead to match R_TLSLD_HINT added in other patch.
Also its in the wrong place, since these are sorted alphabetically.

[ruiu]

lld/ELF/Arch/PPC64.cpp

207 ↗

(On Diff #154139)

nit: error messages should start with a lowercase letter.

238 ↗

(On Diff #154139)

nit: remove {} since we don't need to create a new scope for local variable for this case.

249 ↗

(On Diff #154139)

unsigned -> uint32_t

251 ↗

(On Diff #154139)

U -> u

252–253 ↗

(On Diff #154139)

unsigned -> uint32_t.

lld/ELF/Relocations.h

83 ↗

(On Diff #154139)

Does this compile? R_TLSIE_HINT is added but other files refer R_TLS_IE_HINT.

[MaskRay]

Just a question. Does this patch support the optimization that fills in the GOT slot when a group of initial-exec relocations are known to be link-time constants?

__attribute__((tls_model("initial-exec")))
static __thread DTLS dtls;

48:   00 00 62 3c     addis   r3,r2,0
                      48: R_PPC64_GOT_TPREL16_HA      _ZN11__sanitizerL4dtlsE
4c:   00 00 63 e8     ld      r3,0(r3)
                      4c: R_PPC64_GOT_TPREL16_LO_DS   _ZN11__sanitizerL4dtlsE
50:   14 6a 83 7c     add     r4,r3,r13
                      50: R_PPC64_TLS _ZN11__sanitizerL4dtlsE

https://github.com/llvm-mirror/lld/tree/master/ELF/Relocations.cpp#L747

template <class ELFT> static void addGotEntry(Symbol &Sym) {
...
  bool IsLinkTimeConstant =
      !Sym.IsPreemptible && (!Config->Pic || isAbsolute(Sym));
  /// if R_PPC64_GOT_TPREL16_HA R_PPC64_GOT_TPREL16_LO_DS are link-time constants, they can be filled but `Target->GotRel` should not be used here as it is a 64-bit value.
  /// Target->GotRel is R_PPC64_GLOB_DAT but I think it should not be used.
  if (IsLinkTimeConstant) {
    InX::Got->Relocations.push_back({Expr, Target->GotRel, Off, 0, &Sym});
    return;
  }

[syzaara]

In D48091#1165410, @MaskRay wrote:

Just a question. Does this patch support the optimization that fills in the GOT slot when a group of initial-exec relocations are known to be link-time constants?

__attribute__((tls_model("initial-exec")))
static __thread DTLS dtls;

48:   00 00 62 3c     addis   r3,r2,0
                      48: R_PPC64_GOT_TPREL16_HA      _ZN11__sanitizerL4dtlsE
4c:   00 00 63 e8     ld      r3,0(r3)
                      4c: R_PPC64_GOT_TPREL16_LO_DS   _ZN11__sanitizerL4dtlsE
50:   14 6a 83 7c     add     r4,r3,r13
                      50: R_PPC64_TLS _ZN11__sanitizerL4dtlsE

https://github.com/llvm-mirror/lld/tree/master/ELF/Relocations.cpp#L747

template <class ELFT> static void addGotEntry(Symbol &Sym) {
...
  bool IsLinkTimeConstant =
      !Sym.IsPreemptible && (!Config->Pic || isAbsolute(Sym));
  /// if R_PPC64_GOT_TPREL16_HA R_PPC64_GOT_TPREL16_LO_DS are link-time constants, they can be filled but `Target->GotRel` should not be used here as it is a 64-bit value.
  /// Target->GotRel is R_PPC64_GLOB_DAT but I think it should not be used.
  if (IsLinkTimeConstant) {
    InX::Got->Relocations.push_back({Expr, Target->GotRel, Off, 0, &Sym});
    return;
  }

For the example of:
attribute((tls_model("initial-exec")))
static __thread DTLS dtls;

We handle the TLS relocations for R_PPC64_GOT_TPREL16_HA, R_PPC64_GOT_TPREL16_LO_DS, R_PPC64_TLS before we check for needsGot.
When handling these relocations, they are optimized into the local exec model. This model does not require any GOT slots, so there isn't anything to optimize for the GOT slots.

[sfertile]

lld/ELF/Arch/PPC64.cpp

26 ↗

(On Diff #154286)

Do we need to relax vector load/stores as well?

222 ↗

(On Diff #154286)

A brief description of what x@tls means would be useful here.

225 ↗

(On Diff #154286)

getDFormOp already lists all the instructions we want to convert form X-form to D-form. We can probably condense this comment to not list them all explicitly.

The last instruction in the initial exec sequence has multiple variations that need to be handled. If we are building an address it will use an add instruction, if we are accessing memory it will  use any of the X-form indexed load or store instructions

257 ↗

(On Diff #154286)

We should have a default case with an llvm_unreachable, and do we need to handle R_PPC64_GOT_TPREL16_DS and R_PPC64_GOT_TPREL16_HI?

lld/ELF/InputSection.cpp

515 ↗

(On Diff #154286)

Sort alphabetically.

[ruiu]

Generally looking good.

lld/ELF/Arch/PPC64.cpp

227 ↗

(On Diff #157109)

By the last instruction, do you mean add in the above code? If so, please write it so.

240 ↗

(On Diff #157109)

nit: you can remove ()

249 ↗

(On Diff #157109)

remove space between Op and "(".

[ruiu]

LGTM with this change.

lld/ELF/Arch/PPC64.cpp

228–229 ↗

(On Diff #157273)

Incomplete sentence? Please fix.

lld/trunk/ELF/Arch/PPC64.cpp

 using namespace llvm::support::endian;
 using namespace llvm::ELF;
 using namespace lld;
 using namespace lld::elf;
 
 static uint64_t PPC64TocOffset = 0x8000;
 static uint64_t DynamicThreadPointerOffset = 0x8000;
 
+// The instruction encoding of bits 21-30 from the ISA for the Xform and Dform
+// instructions that can be used as part of the initial exec TLS sequence.
+enum XFormOpcd {
+  LBZX = 87,
+  LHZX = 279,
+  LWZX = 23,
+  LDX = 21,
+  STBX = 215,
+  STHX = 407,
+  STWX = 151,
+  STDX = 149,
+  ADD = 266,
+};
+
+enum DFormOpcd {
+  LBZ = 34,
+  LHZ = 40,
+  LWZ = 32,
+  LD = 58,
+  STB = 38,
+  STH = 44,
+  STW = 36,
+  STD = 62,
+  ADDI = 14
+};
+
 uint64_t elf::getPPC64TocBase() {
   // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
   // TOC starts where the first of these sections starts. We always create a
   // .got when we see a relocation that uses it, so for us the start is always
   // the .got.
   uint64_t TocVA = InX::Got->getVA();
 
   // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
public:
   void writeGotHeader(uint8_t *Buf) const override;
   bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
                   uint64_t BranchAddr, const Symbol &S) const override;
   RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
                           RelExpr Expr) const override;
   void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
   void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
   void relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+  void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
 };
 } // namespace
 
 // Relocation masks following the #lo(value), #hi(value), #ha(value),
 // #higher(value), #highera(value), #highest(value), and #highesta(value)
 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi
 // document.
 static uint16_t lo(uint64_t V) { return V; }
void PPC64::relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
   case R_PPC64_GOT_DTPREL16_HI:
     relocateOne(Loc, Type, Val);
     break;
   default:
     llvm_unreachable("unsupported relocation for TLS LD to LE relaxation");
   }
 }
 
+static unsigned getDFormOp(unsigned SecondaryOp) {
+  switch (SecondaryOp) {
+  case LBZX:
+    return LBZ;
+  case LHZX:
+    return LHZ;
+  case LWZX:
+    return LWZ;
+  case LDX:
+    return LD;
+  case STBX:
+    return STB;
+  case STHX:
+    return STH;
+  case STWX:
+    return STW;
+  case STDX:
+    return STD;
+  case ADD:
+    return ADDI;
+  default:
+    error("unrecognized instruction for IE to LE R_PPC64_TLS");
+    return 0;
+  }
+}
+
+void PPC64::relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
+  // The initial exec code sequence for a global `x` will look like:
+  // Instruction                    Relocation                Symbol
+  // addis r9, r2, x@got@tprel@ha   R_PPC64_GOT_TPREL16_HA      x
+  // ld    r9, x@got@tprel@l(r9)    R_PPC64_GOT_TPREL16_LO_DS   x
+  // add r9, r9, x@tls              R_PPC64_TLS                 x
+
+  // Relaxing to local exec entails converting:
+  // addis r9, r2, x@got@tprel@ha       into        nop
+  // ld r9, x@got@tprel@l(r9)           into        addis r9, r13, x@tprel@ha
+  // add r9, r9, x@tls                  into        addi r9, r9, x@tprel@l
+
+  // x@tls R_PPC64_TLS is a relocation which does not compute anything,
+  // it is replaced with r13 (thread pointer).
+
+  // The add instruction in the initial exec sequence has multiple variations
+  // that need to be handled. If we are building an address it will use an add
+  // instruction, if we are accessing memory it will use any of the X-form
+  // indexed load or store instructions.
+
+  unsigned Offset = (Config->EKind == ELF64BEKind) ? 2 : 0;
+  switch (Type) {
+  case R_PPC64_GOT_TPREL16_HA:
+    write32(Loc - Offset, 0x60000000); // nop
+    break;
+  case R_PPC64_GOT_TPREL16_LO_DS:
+  case R_PPC64_GOT_TPREL16_DS: {
+    uint32_t RegNo = read32(Loc - Offset) & 0x03E00000; // bits 6-10
+    write32(Loc - Offset, 0x3C0D0000 | RegNo);          // addis RegNo, r13
+    relocateOne(Loc, R_PPC64_TPREL16_HA, Val);
+    break;
+  }
+  case R_PPC64_TLS: {
+    uint32_t PrimaryOp = (read32(Loc) & 0xFC000000) >> 26; // bits 0-5
+    if (PrimaryOp != 31)
+      error("unrecognized instruction for IE to LE R_PPC64_TLS");
+    uint32_t SecondaryOp = (read32(Loc) & 0x000007FE) >> 1; // bits 21-30
+    uint32_t DFormOp = getDFormOp(SecondaryOp);
+    write32(Loc, ((DFormOp << 26) | (read32(Loc) & 0x03FFFFFF)));
+    relocateOne(Loc + Offset, R_PPC64_TPREL16_LO, Val);
+    break;
+  }
+  default:
+    llvm_unreachable("unknown relocation for IE to LE");
+    break;
+  }
+}
+
 RelExpr PPC64::getRelExpr(RelType Type, const Symbol &S,
                           const uint8_t *Loc) const {
   switch (Type) {
   case R_PPC64_TOC16:
   case R_PPC64_TOC16_DS:
   case R_PPC64_TOC16_HA:
   case R_PPC64_TOC16_HI:
   case R_PPC64_TOC16_LO:
RelExpr PPC64::getRelExpr(RelType Type, const Symbol &S,
   case R_PPC64_DTPREL16_LO_DS:
   case R_PPC64_DTPREL64:
     return R_ABS;
   case R_PPC64_TLSGD:
     return R_TLSDESC_CALL;
   case R_PPC64_TLSLD:
     return R_TLSLD_HINT;
   case R_PPC64_TLS:
-    return R_HINT;
+    return R_TLSIE_HINT;
   default:
     return R_ABS;
   }
 }
 
 void PPC64::writeGotHeader(uint8_t *Buf) const {
   write64(Buf, getPPC64TocBase());
 }

lld/trunk/ELF/Relocations.h

enum RelExpr {
   R_SIZE,
   R_TLS,
   R_TLSDESC,
   R_TLSDESC_CALL,
   R_TLSDESC_PAGE,
   R_TLSGD_GOT,
   R_TLSGD_GOT_FROM_END,
   R_TLSGD_PC,
+  R_TLSIE_HINT,
   R_TLSLD_GOT,
   R_TLSLD_GOT_FROM_END,
   R_TLSLD_GOT_OFF,
   R_TLSLD_HINT,
   R_TLSLD_PC,
 };
 
 // Build a bitmask with one bit set for each RelExpr.

lld/trunk/ELF/Relocations.cpp

if (Sym.IsPreemptible) {
           {Target->adjustRelaxExpr(Type, nullptr, R_RELAX_TLS_GD_TO_LE), Type,
            Offset, Addend, &Sym});
     }
     return Target->TlsGdRelaxSkip;
   }
 
   // Initial-Exec relocs can be relaxed to Local-Exec if the symbol is locally
   // defined.
-  if (isRelExprOneOf<R_GOT, R_GOT_FROM_END, R_GOT_PC, R_GOT_PAGE_PC>(Expr) &&
+  if (isRelExprOneOf<R_GOT, R_GOT_FROM_END, R_GOT_PC, R_GOT_PAGE_PC, R_GOT_OFF,
+                     R_TLSIE_HINT>(Expr) &&
       !Config->Shared && !Sym.IsPreemptible) {
     C.Relocations.push_back({R_RELAX_TLS_IE_TO_LE, Type, Offset, Addend, &Sym});
     return 1;
   }
 
+  if (Expr == R_TLSIE_HINT)
+    return 1;
   return 0;
 }
 
 static RelType getMipsPairType(RelType Type, bool IsLocal) {
   switch (Type) {
   case R_MIPS_HI16:
     return R_MIPS_LO16;
   case R_MIPS_GOT16:
static bool isStaticLinkTimeConstant(RelExpr E, RelType Type, const Symbol &Sym,
                                      InputSectionBase &S, uint64_t RelOff) {
   // These expressions always compute a constant
   if (isRelExprOneOf<
           R_GOT_FROM_END, R_GOT_OFF, R_TLSLD_GOT_OFF, R_MIPS_GOT_LOCAL_PAGE,
           R_MIPS_GOTREL, R_MIPS_GOT_OFF, R_MIPS_GOT_OFF32, R_MIPS_GOT_GP_PC,
           R_MIPS_TLSGD, R_GOT_PAGE_PC, R_GOT_PC, R_GOTONLY_PC,
           R_GOTONLY_PC_FROM_END, R_PLT_PC, R_TLSGD_GOT, R_TLSGD_GOT_FROM_END,
           R_TLSGD_PC, R_PPC_CALL_PLT, R_TLSDESC_CALL, R_TLSDESC_PAGE, R_HINT,
-          R_TLSLD_HINT>(E))
+          R_TLSLD_HINT, R_TLSIE_HINT>(E))
     return true;
 
   // These never do, except if the entire file is position dependent or if
   // only the low bits are used.
   if (E == R_GOT || E == R_PLT || E == R_TLSDESC)
     return Target->usesOnlyLowPageBits(Type) || !Config->Pic;
 
   if (Sym.IsPreemptible)

lld/trunk/test/ELF/Inputs/ppc64-tls-ie-le.s

+  .text
+  .abiversion 2
+  .type c,@object               # @c
+  .section  .tdata,"awT",@progbits
+  .globl  c
+c:
+  .byte 97                      # 0x61
+  .size c, 1
+
+  .type s,@object               # @s
+  .globl  s
+  .p2align  1
+s:
+  .short  55                      # 0x37
+  .size s, 2
+
+  .type i,@object               # @i
+  .globl  i
+  .p2align  2
+i:
+  .long 55                      # 0x37
+  .size i, 4
+
+  .type l,@object               # @l
+  .globl  l
+  .p2align  3
+l:
+  .quad 55                      # 0x37
+  .size l, 8

lld/trunk/test/ELF/ppc64-tls-ie-le.s

+// REQUIRES: ppc
+
+// RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o
+// RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %p/Inputs/ppc64-tls-ie-le.s -o %t2.o
+// RUN: ld.lld -dynamic-linker /lib64/ld64.so.2 %t.o %t2.o -o %t
+// RUN: llvm-readelf -relocations --wide %t.o | FileCheck --check-prefix=InputRelocs %s
+// RUN: llvm-readelf -relocations --wide %t | FileCheck --check-prefix=OutputRelocs %s
+// RUN: llvm-objdump -D %t | FileCheck --check-prefix=Dis %s
+
+// RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t.o
+// RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %p/Inputs/ppc64-tls-ie-le.s -o %t2.o
+// RUN: ld.lld -dynamic-linker /lib64/ld64.so.2 %t.o %t2.o -o %t
+// RUN: llvm-readelf -relocations --wide %t.o | FileCheck --check-prefix=InputRelocs %s
+// RUN: llvm-readelf -relocations --wide %t | FileCheck --check-prefix=OutputRelocs %s
+// RUN: llvm-objdump -D %t | FileCheck --check-prefix=Dis %s
+
+  .text
+  .abiversion 2
+test1:                                  # @test1
+  addis 3, 2, c@got@tprel@ha
+  ld 3, c@got@tprel@l(3)
+  lbzx 3, 3, c@tls
+  blr
+test2:                                  # @test2
+  addis 3, 2, s@got@tprel@ha
+  ld 3, s@got@tprel@l(3)
+  lhzx 3, 3, s@tls
+  blr
+test3:                                  # @test3
+  addis 3, 2, i@got@tprel@ha
+  ld 3, i@got@tprel@l(3)
+  lwzx 3, 3, i@tls
+  blr
+test4:                                  # @test4
+  addis 3, 2, l@got@tprel@ha
+  ld 3, l@got@tprel@l(3)
+  ldx 3, 3, l@tls
+  blr
+test5:                                  # @test5
+  addis 4, 2, c@got@tprel@ha
+  ld 4, c@got@tprel@l(4)
+  stbx 3, 4, c@tls
+  blr
+test6:                                  # @test6
+  addis 4, 2, s@got@tprel@ha
+  ld 4, s@got@tprel@l(4)
+  sthx 3, 4, s@tls
+  blr
+test7:                                  # @test7
+  addis 4, 2, i@got@tprel@ha
+  ld 4, i@got@tprel@l(4)
+  stwx 3, 4, i@tls
+  blr
+test8:                                  # @test8
+  addis 4, 2, l@got@tprel@ha
+  ld 4, l@got@tprel@l(4)
+  stdx 3, 4, l@tls
+  blr
+test9:                                  # @test9
+  addis 3, 2, i@got@tprel@ha
+  ld 3, i@got@tprel@l(3)
+  add 3, 3, i@tls
+  blr
+test_ds:                                  # @test_ds
+  ld 4, l@got@tprel(2)
+  stdx 3, 4, l@tls
+  blr
+
+
+// Verify that the input has initial-exec tls relocation types.
+// InputRelocs: Relocation section '.rela.text'
+// InputRelocs: R_PPC64_GOT_TPREL16_HA {{0+}} c + 0
+// InputRelocs: R_PPC64_GOT_TPREL16_LO_DS {{0+}} c + 0
+// InputRelocs: R_PPC64_TLS {{0+}} c + 0
+// InputRelocs: R_PPC64_GOT_TPREL16_HA {{0+}} s + 0
+// InputRelocs: R_PPC64_GOT_TPREL16_LO_DS {{0+}} s + 0
+// InputRelocs: R_PPC64_TLS {{0+}} s + 0
+// InputRelocs: R_PPC64_GOT_TPREL16_HA {{0+}} i + 0
+// InputRelocs: R_PPC64_GOT_TPREL16_LO_DS {{0+}} i + 0
+// InputRelocs: R_PPC64_TLS {{0+}} i + 0
+// InputRelocs: R_PPC64_GOT_TPREL16_HA {{0+}} l + 0
+// InputRelocs: R_PPC64_GOT_TPREL16_LO_DS {{0+}} l + 0
+// InputRelocs: R_PPC64_TLS {{0+}} l + 0
+// InputRelocs: R_PPC64_GOT_TPREL16_DS {{0+}} l + 0
+// InputRelocs: R_PPC64_TLS {{0+}} l + 0
+
+// Verify that no initial-exec relocations exist for the dynamic linker.
+// OutputRelocs-NOT: R_PPC64_TPREL64  {{0+}}  c + 0
+// OutputRelocs-NPT: R_PPC64_TPREL64  {{0+}}  s + 0
+// OutputRelocs-NOT: R_PPC64_TPREL64  {{0+}}  i + 0
+// OutputRelocs-NOT: R_PPC64_TPREL64  {{0+}}  l + 0
+
+// Dis: test1:
+// Dis: nop
+// Dis: addis 3, 13, 0
+// Dis: lbz 3, -28672(3)
+
+// Dis: test2:
+// Dis: nop
+// Dis: addis 3, 13, 0
+// Dis: lhz 3, -28670(3)
+
+// Dis: test3:
+// Dis: nop
+// Dis: addis 3, 13, 0
+// Dis: lwz 3, -28668(3)
+
+// Dis: test4:
+// Dis: nop
+// Dis: addis 3, 13, 0
+// Dis: ld 3, -28664(3)
+
+// Dis: test5:
+// Dis: nop
+// Dis: addis 4, 13, 0
+// Dis: stb 3, -28672(4)
+
+// Dis: test6:
+// Dis: nop
+// Dis: addis 4, 13, 0
+// Dis: sth 3, -28670(4)
+
+// Dis: test7:
+// Dis: nop
+// Dis: addis 4, 13, 0
+// Dis: stw 3, -28668(4)
+
+// Dis: test8:
+// Dis: nop
+// Dis: addis 4, 13, 0
+// Dis: std 3, -28664(4)
+
+// Dis: test9:
+// Dis: nop
+// Dis: addis 3, 13, 0
+// Dis: addi 3, 3, -28668
+
+// Dis: test_ds:
+// Dis: addis 4, 13, 0
+// Dis: std 3, -28664(4)