[mips] Support shrink-wrapping

[vstefanovic]

Summary

Except for -O0, it's enabled by default.

[sdardis]

test/CodeGen/Mips/shrink-wrapping.ll

1

Can you use the update_llc_checks.py script to generate the check lines? You'll need to supply a triple instead of -march=

7

Remove the dso_local, local_unamed_addr and nounwind from this.

33

Can you also provide a test case similar to gcc PR86069? For O32 this consists of a branch over a section of code to an early return and the branch has to be expanded into a long jump sequence. You can use .space to create arbitrary size chunks of nops.

34

Similarly here for the dso_local.

[vstefanovic]

Added long branch test, used update_llc_test_checks.py to create checks.

[sdardis]

test/CodeGen/Mips/shrink-wrapping.ll

4

Can you also add mips64 tests?

193–196

Can you remove this alloca, we need to expose the jump in such a way that the shrink wrapping pass tries to move the prologue past it.

[vstefanovic]

Updated the long branch test with actual shrink-wrapping.

[atanasyan]

LGTM

lib/Target/Mips/Mips16FrameLowering.cpp

 
 using namespace llvm;
 
 Mips16FrameLowering::Mips16FrameLowering(const MipsSubtarget &STI)
     : MipsFrameLowering(STI, STI.getStackAlignment()) {}
 
 void Mips16FrameLowering::emitPrologue(MachineFunction &MF,
                                        MachineBasicBlock &MBB) const {
-  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
   MachineFrameInfo &MFI = MF.getFrameInfo();
   const Mips16InstrInfo &TII =
       *static_cast<const Mips16InstrInfo *>(STI.getInstrInfo());
   MachineBasicBlock::iterator MBBI = MBB.begin();
 
   // Debug location must be unknown since the first debug location is used
   // to determine the end of the prologue.
   DebugLoc dl;
void Mips16FrameLowering::emitPrologue(MachineFunction &MF,
   }
   if (hasFP(MF))
     BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
       .addReg(Mips::SP).setMIFlag(MachineInstr::FrameSetup);
 }
 
 void Mips16FrameLowering::emitEpilogue(MachineFunction &MF,
                                  MachineBasicBlock &MBB) const {
-  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
+  MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   const Mips16InstrInfo &TII =
       *static_cast<const Mips16InstrInfo *>(STI.getInstrInfo());
-  DebugLoc dl = MBBI->getDebugLoc();
+  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
   uint64_t StackSize = MFI.getStackSize();
 
   if (!StackSize)
     return;
 
   if (hasFP(MF))
     BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
       .addReg(Mips::S0);
 
   // Adjust stack.
   // assumes stacksize multiple of 8
   TII.restoreFrame(Mips::SP, StackSize, MBB, MBBI);
 }
 
 bool Mips16FrameLowering::
 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MI,
                           const std::vector<CalleeSavedInfo> &CSI,
                           const TargetRegisterInfo *TRI) const {
   MachineFunction *MF = MBB.getParent();
-  MachineBasicBlock *EntryBlock = &MF->front();
 
   //
   // Registers RA, S0,S1 are the callee saved registers and they
   // will be saved with the "save" instruction
   // during emitPrologue
   //
   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
     // Add the callee-saved register as live-in. Do not add if the register is
     // RA and return address is taken, because it has already been added in
     // method MipsTargetLowering::lowerRETURNADDR.
     // It's killed at the spill, unless the register is RA and return address
     // is taken.
     unsigned Reg = CSI[i].getReg();
     bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
       && MF->getFrameInfo().isReturnAddressTaken();
     if (!IsRAAndRetAddrIsTaken)
-      EntryBlock->addLiveIn(Reg);
+      MBB.addLiveIn(Reg);
   }
 
   return true;
 }
 
 bool Mips16FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator MI,
                                        std::vector<CalleeSavedInfo> &CSI,

lib/Target/Mips/MipsFrameLowering.h

public:
   static const MipsFrameLowering *create(const MipsSubtarget &ST);
 
   bool hasFP(const MachineFunction &MF) const override;
 
   bool hasBP(const MachineFunction &MF) const;
 
   bool isFPCloseToIncomingSP() const override { return false; }
 
+  bool enableShrinkWrapping(const MachineFunction &MF) const override {
+    return true;
+  }
+
   MachineBasicBlock::iterator
   eliminateCallFramePseudoInstr(MachineFunction &MF,
                                 MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator I) const override;
 
 protected:
   uint64_t estimateStackSize(const MachineFunction &MF) const;
 };
 
 /// Create MipsFrameLowering objects.
 const MipsFrameLowering *createMips16FrameLowering(const MipsSubtarget &ST);
 const MipsFrameLowering *createMipsSEFrameLowering(const MipsSubtarget &ST);
 
 } // End llvm namespace
 
 #endif

lib/Target/Mips/MipsSEFrameLowering.cpp

bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
   return false;
 }
 
 MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI)
     : MipsFrameLowering(STI, STI.getStackAlignment()) {}
 
 void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
                                        MachineBasicBlock &MBB) const {
-  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
   MachineFrameInfo &MFI    = MF.getFrameInfo();
   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 
   const MipsSEInstrInfo &TII =
       *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
   const MipsRegisterInfo &RegInfo =
       *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
 
void MipsSEFrameLowering::emitInterruptPrologueStub(
   BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
       .addReg(Mips::K1)
       .addImm(0)
       .setMIFlag(MachineInstr::FrameSetup);
 }
 
 void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
                                        MachineBasicBlock &MBB) const {
-  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
+  MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
   MachineFrameInfo &MFI            = MF.getFrameInfo();
   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 
   const MipsSEInstrInfo &TII =
       *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
   const MipsRegisterInfo &RegInfo =
       *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
 
-  DebugLoc DL = MBBI->getDebugLoc();
+  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
   MipsABIInfo ABI = STI.getABI();
   unsigned SP = ABI.GetStackPtr();
   unsigned FP = ABI.GetFramePtr();
   unsigned ZERO = ABI.GetNullPtr();
   unsigned MOVE = ABI.GetGPRMoveOp();
 
   // if framepointer enabled, restore the stack pointer.
   if (hasFP(MF)) {

 }
 
 bool MipsSEFrameLowering::
 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MI,
                           const std::vector<CalleeSavedInfo> &CSI,
                           const TargetRegisterInfo *TRI) const {
   MachineFunction *MF = MBB.getParent();
-  MachineBasicBlock *EntryBlock = &MF->front();
   const TargetInstrInfo &TII = *STI.getInstrInfo();
 
   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
     // Add the callee-saved register as live-in. Do not add if the register is
     // RA and return address is taken, because it has already been added in
     // method MipsTargetLowering::lowerRETURNADDR.
     // It's killed at the spill, unless the register is RA and return address
     // is taken.
     unsigned Reg = CSI[i].getReg();
     bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
         && MF->getFrameInfo().isReturnAddressTaken();
     if (!IsRAAndRetAddrIsTaken)
-      EntryBlock->addLiveIn(Reg);
+      MBB.addLiveIn(Reg);
 
     // ISRs require HI/LO to be spilled into kernel registers to be then
     // spilled to the stack frame.
     bool IsLOHI = (Reg == Mips::LO0 || Reg == Mips::LO0_64 ||
                    Reg == Mips::HI0 || Reg == Mips::HI0_64);
     const Function &Func = MBB.getParent()->getFunction();
     if (IsLOHI && Func.hasFnAttribute("interrupt")) {
       DebugLoc DL = MI->getDebugLoc();
 
       unsigned Op = 0;
       if (!STI.getABI().ArePtrs64bit()) {
         Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO;
         Reg = Mips::K0;
       } else {
         Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64;
         Reg = Mips::K0_64;
       }
       BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0)
           .setMIFlag(MachineInstr::FrameSetup);
     }
 
     // Insert the spill to the stack frame.
     bool IsKill = !IsRAAndRetAddrIsTaken;
     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
-    TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
+    TII.storeRegToStackSlot(MBB, MI, Reg, IsKill,
                             CSI[i].getFrameIdx(), RC, TRI);
   }
 
   return true;
 }
 
 bool
 MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {

test/CodeGen/Mips/blez_bgez.ll

-; RUN: llc -march=mipsel < %s | FileCheck %s
-; RUN: llc -march=mips64el < %s | FileCheck %s
+; RUN: llc -march=mipsel -enable-shrink-wrap=false  < %s | FileCheck %s
+; RUN: llc -march=mips64el -enable-shrink-wrap=false < %s | FileCheck %s
 
 ; CHECK-LABEL: test_blez:
 ; CHECK: blez ${{[0-9]+}}, {{\$|\.L}}BB
 
 define void @test_blez(i32 %a) {
 entry:
   %cmp = icmp sgt i32 %a, 0
   br i1 %cmp, label %if.then, label %if.end

test/CodeGen/Mips/brdelayslot.ll

 ; RUN: llc -march=mipsel -O0 < %s | FileCheck %s -check-prefix=None
 ; RUN: llc -march=mipsel     -relocation-model=pic    < %s | \
 ; RUN: FileCheck %s -check-prefix=Default
 ; RUN: llc -march=mipsel -O1 -relocation-model=static < %s | \
 ; RUN: FileCheck %s -check-prefix=STATICO1
 ; RUN: llc -march=mipsel -disable-mips-df-forward-search=false \
 ; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=FORWARD
 ; RUN: llc -march=mipsel -disable-mips-df-backward-search -relocation-model=pic \
+; RUN: -enable-shrink-wrap=false \
 ; RUN: -disable-mips-df-succbb-search=false -disable-preheader-prot=true < %s | \
 ; RUN: FileCheck %s -check-prefix=SUCCBB
 
 define void @foo1() nounwind {
 entry:
 ; Default:     jalr
 ; Default-NOT: nop
 ; Default:     jr

test/CodeGen/Mips/shrink-wrapping.ll

+; RUN: llc -march=mips -enable-shrink-wrap=true < %s | \
+; RUN:   FileCheck %s -check-prefixes=SHRINK-WRAP,ALL
+
+; RUN: llc -march=mips -enable-shrink-wrap=false < %s | \
+; RUN:   FileCheck %s -check-prefixes=NO-SHRINK-WRAP,ALL
+
+define dso_local i32 @foo(i32 signext %a) local_unnamed_addr nounwind {
+entry:
+; ALL: %bb.0:
+; SHRINK-WRAP-NEXT: beqz
+; NO-SHRINK-WRAP-NEXT: addiu $sp, $sp, -[[SIZE:[0-9]+]]
+; NO-SHRINK-WRAP-NEXT: sw $ra, {{[0-9]+}}($sp)
+  %cmp = icmp eq i32 %a, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:
+; ALL: %bb.1:
+; SHRINK-WRAP-NEXT: addiu $sp, $sp, -[[SIZE:[0-9]+]]
+; SHRINK-WRAP-NEXT: sw $ra, {{[0-9]+}}($sp)
+  %add = add nsw i32 %a, 1
+  tail call void @foo2(i32 signext %add)
+; SHRINK-WRAP: lw $ra, {{[0-9]+}}($sp)
+; SHRINK-WRAP-NEXT: addiu $sp, $sp, [[SIZE]]
+  br label %return
+
+return:
+; ALL: BB0_2
+; NO-SHRINK-WRAP: lw $ra, {{[0-9]+}}($sp)
+; NO-SHRINK-WRAP: addiu $sp, $sp, [[SIZE]]
+; SHRINK-WRAP-NOT: addiu $sp, $sp
+  ret i32 0
+}
+
+declare dso_local void @foo2(i32 signext) local_unnamed_addr