[AMDGPU][MC] Enabled parsing of relocations on VALU instructions

[dp]

Summary

See bug 37566: https://bugs.llvm.org/show_bug.cgi?id=37566

Also enabled expressions for VSrcF32.

[arsenm]

Missing test for the f32 src change?

[dp]

In D47884#1125262, @arsenm wrote:

Missing test for the f32 src change?

I do not think relocations will ever be used with f32 operands, so I added a generic check for expressions:

v_mul_f32 v0, foo+2, v2

Is this sufficient?

[artem.tamazov]

LGTM

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

bool isVCSrcF16() const {
     return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f16);
   }
 
   bool isVCSrcV2F16() const {
     return isVCSrcF16();
   }
 
   bool isVSrcB32() const {
-    return isVCSrcF32() || isLiteralImm(MVT::i32);
+    return isVCSrcF32() || isLiteralImm(MVT::i32) || isExpr();
   }
 
   bool isVSrcB64() const {
     return isVCSrcF64() || isLiteralImm(MVT::i64);
   }
 
   bool isVSrcB16() const {
     return isVCSrcF16() || isLiteralImm(MVT::i16);
   }
 
   bool isVSrcV2B16() const {
     llvm_unreachable("cannot happen");
     return isVSrcB16();
   }
 
   bool isVSrcF32() const {
-    return isVCSrcF32() || isLiteralImm(MVT::f32);
+    return isVCSrcF32() || isLiteralImm(MVT::f32) || isExpr();
   }
 
   bool isVSrcF64() const {
     return isVCSrcF64() || isLiteralImm(MVT::f64);
   }
 
   bool isVSrcF16() const {
     return isVCSrcF16() || isLiteralImm(MVT::f16);

llvm/trunk/test/MC/AMDGPU/expressions.s

 s_mov_b32 s0, foo+2
 // VI: s_mov_b32 s0, 6 ; encoding: [0x86,0x00,0x80,0xbe]
 
 // Use a computed expression that results in a non-inline immediate.
 .set foo, 512
 s_mov_b32 s0, foo+2
 // VI: s_mov_b32 s0, 514 ; encoding: [0xff,0x00,0x80,0xbe,0x02,0x02,0x00,0x00]
 
+v_mul_f32 v0, foo+2, v2
+// VI: v_mul_f32_e32 v0, 514, v2 ; encoding: [0xff,0x04,0x00,0x0a,0x02,0x02,0x00,0x00]
+
 BB1:
 v_nop_e64
 BB2:
 s_sub_u32 vcc_lo, vcc_lo, (BB2+4)-BB1
 // VI: s_sub_u32 vcc_lo, vcc_lo, (BB2+4)-BB1 ; encoding: [0x6a,0xff,0xea,0x80,A,A,A,A]
 // VI-NEXT: ;   fixup A - offset: 4, value: (BB2+4)-BB1, kind: FK_Data_4
 
 t=1
 s_sub_u32 s0, s0, -t
 // VI: s_sub_u32 s0, s0, -1            ; encoding: [0x00,0xc1,0x80,0x80]
 
 t=-1
 s_sub_u32 s0, s0, -t
 // VI: s_sub_u32 s0, s0, 1             ; encoding: [0x00,0x81,0x80,0x80]

llvm/trunk/test/MC/AMDGPU/reloc.s

 // RUN: llvm-mc -filetype=obj -triple amdgcn-- -mcpu=kaveri -show-encoding %s | llvm-readobj -relocations | FileCheck %s
 
 // CHECK: Relocations [
 // CHECK: .rel.text {
 // CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0
 // CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0
 // CHECK: R_AMDGPU_GOTPCREL global_var0 0x0
 // CHECK: R_AMDGPU_GOTPCREL32_LO global_var1 0x0
 // CHECK: R_AMDGPU_GOTPCREL32_HI global_var2 0x0
 // CHECK: R_AMDGPU_REL32_LO global_var3 0x0
 // CHECK: R_AMDGPU_REL32_HI global_var4 0x0
+// CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0
+// CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0
+// CHECK: R_AMDGPU_GOTPCREL global_var0 0x0
+// CHECK: R_AMDGPU_GOTPCREL32_LO global_var1 0x0
+// CHECK: R_AMDGPU_GOTPCREL32_HI global_var2 0x0
+// CHECK: R_AMDGPU_REL32_LO global_var3 0x0
+// CHECK: R_AMDGPU_REL32_HI global_var4 0x0
 // CHECK: R_AMDGPU_ABS32 var 0x0
 // CHECK: }
 // CHECK: .rel.data {
 // CHECK: R_AMDGPU_ABS64 temp 0x0
 // CHECK: R_AMDGPU_REL64 temp 0x0
 // CHECK: }
 // CHECK: ]
 
 kernel:
   s_mov_b32 s0, SCRATCH_RSRC_DWORD0
   s_mov_b32 s1, SCRATCH_RSRC_DWORD1
   s_mov_b32 s2, global_var0@GOTPCREL
   s_mov_b32 s3, global_var1@gotpcrel32@lo
   s_mov_b32 s4, global_var2@gotpcrel32@hi
   s_mov_b32 s5, global_var3@rel32@lo
   s_mov_b32 s6, global_var4@rel32@hi
 
+  v_mov_b32 v0, SCRATCH_RSRC_DWORD0
+  v_mov_b32 v1, SCRATCH_RSRC_DWORD1
+  v_mov_b32 v2, global_var0@GOTPCREL
+  v_mov_b32 v3, global_var1@gotpcrel32@lo
+  v_mov_b32 v4, global_var2@gotpcrel32@hi
+  v_mov_b32 v5, global_var3@rel32@lo
+  v_mov_b32 v6, global_var4@rel32@hi
+
 .globl global_var0
 .globl global_var1
 .globl global_var2
 .globl global_var3
 .globl global_var4
 
 .globl SCRATCH_RSRC_DWORD0