Initial support for Hexagon target.

[sidneym]

Summary

Support B22_PCREL relocation along with a simple test.

I'm also working on a llvmSupport patch that will detail the instruction set encoding. Many of Hexagon's instructions have immediates that are peppered throughout the word makeing application of fixups tedious since the same relocation fixup may need to be placed in different bits depending on the instruction. That change will be made in llvmSupport so that both lld and llvm-rtdyld can share encoding information.

[ruiu]

ELF/Arch/Hexagon.cpp

46 ↗

(On Diff #149991)

sizeof(uint32_t) * 8 is always 32.

77 ↗

(On Diff #149991)

Remove extraneous blank line. If you take a look at other files in lld, you'd notice that we normally don't add a blank line before "default:".

test/ELF/Inputs/hexagon.s

1 ↗

(On Diff #149991)

Remove a leading empty line.

test/ELF/hexagon.s

2 ↗

(On Diff #149991)

Remove extranesous space between "mc" and "-filetype"

9 ↗

(On Diff #149991)

Remove extraneous space characters.

[sidneym]

Made the changes Rui suggested.

[ruiu]

ELF/Arch/Hexagon.cpp

47 ↗

(On Diff #150013)

We normally don't add const if the variable's scope is narrow.

72 ↗

(On Diff #150013)

We usually use much shorter variable name for a variable whose scope is very narrow. Just V would be enough for this.

74 ↗

(On Diff #150013)

I believe we have or32le.

[sidneym]

Adopted more of Rui's suggestions.

[ruiu]

ELF/Arch/Hexagon.cpp

26 ↗

(On Diff #150150)

Please read other files in the same directory and follow the same naming convention. This should be named just Hexagon.

38 ↗

(On Diff #150150)

You don't need this assert as you are not depending on it.

50 ↗

(On Diff #150150)

I believe ValBit (which is bool) is promoted to int because of the usual integer promotion before << is applied, but this is perhaps a bit confusing. It is better to make their types uint32_t.

73 ↗

(On Diff #150150)

You don't need {} if you do not define a new variable inside {}.

[sidneym]

Integrated suggested changes.

[ruiu]

ELF/Arch/Hexagon.cpp

46–47 ↗

(On Diff #150429)

Please do not use auto as well. As I said, if you read other code in this directory or other directories in lld, you'd notice that we normally don't use auto unless its type is obvious (i.e. to avoid a repetition like Foo *X = dyn_cast<Foo>(Y)). I'd be more careful to follow the convention by reading code first.

[sidneym]

Use type instead of auto.

[ruiu]

ELF/Arch/Hexagon.cpp

41 ↗

(On Diff #151139)

I think it needs a comment, but I'll do that in a follow-up patch.

lld/trunk/ELF/Arch/Hexagon.cpp

+//===-- Hexagon.cpp -------------------------------------------------------===//
+//
+//                             The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "InputFiles.h"
+#include "Symbols.h"
+#include "Target.h"
+#include "lld/Common/ErrorHandler.h"
+#include "llvm/BinaryFormat/ELF.h"
+#include "llvm/Object/ELF.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::object;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+class Hexagon final : public TargetInfo {
+public:
+  uint32_t calcEFlags() const override;
+  uint32_t applyMask(uint32_t Mask, uint32_t Data) const;
+  RelExpr getRelExpr(RelType Type, const Symbol &S,
+                     const uint8_t *Loc) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+};
+} // namespace
+
+// Support V60 only at the moment.
+uint32_t Hexagon::calcEFlags() const {
+  return 0x60;
+}
+
+uint32_t Hexagon::applyMask(uint32_t Mask, uint32_t Data) const {
+  uint32_t Result = 0;
+  size_t Off = 0;
+
+  for (size_t Bit = 0; Bit != 32; ++Bit) {
+    uint32_t ValBit = (Data >> Off) & 1;
+    uint32_t MaskBit = (Mask >> Bit) & 1;
+    if (MaskBit) {
+      Result |= (ValBit << Bit);
+      ++Off;
+    }
+  }
+  return Result;
+}
+
+RelExpr Hexagon::getRelExpr(RelType Type, const Symbol &S,
+                                 const uint8_t *Loc) const {
+  switch (Type) {
+  case R_HEX_B22_PCREL:
+    return R_PC;
+  default:
+    return R_ABS;
+  }
+}
+
+static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
+
+void Hexagon::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
+  switch (Type) {
+  case R_HEX_NONE:
+    break;
+  case R_HEX_B22_PCREL:
+    or32le(Loc, applyMask(0x01ff3ffe, ((Val >> 2) & 0x3fffff)));
+    break;
+  default:
+    error(getErrorLocation(Loc) + "unrecognized reloc " + toString(Type));
+    break;
+  }
+}
+
+TargetInfo *elf::getHexagonTargetInfo() {
+  static Hexagon Target;
+  return &Target;
+}

lld/trunk/ELF/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS Options.td)
 tablegen(LLVM Options.inc -gen-opt-parser-defs)
 add_public_tablegen_target(ELFOptionsTableGen)
 
 if(NOT LLD_BUILT_STANDALONE)
   set(tablegen_deps intrinsics_gen)
 endif()
 
 add_lld_library(lldELF
   AArch64ErrataFix.cpp
   Arch/AArch64.cpp
   Arch/AMDGPU.cpp
   Arch/ARM.cpp
   Arch/AVR.cpp
+  Arch/Hexagon.cpp
   Arch/Mips.cpp
   Arch/MipsArchTree.cpp
   Arch/PPC.cpp
   Arch/PPC64.cpp
   Arch/SPARCV9.cpp
   Arch/X86.cpp
   Arch/X86_64.cpp
   CallGraphSort.cpp

lld/trunk/ELF/Target.h

protected:
   // Given that, the smallest value that can be used in here is 0x10000.
   uint64_t DefaultImageBase = 0x10000;
 };
 
 TargetInfo *getAArch64TargetInfo();
 TargetInfo *getAMDGPUTargetInfo();
 TargetInfo *getARMTargetInfo();
 TargetInfo *getAVRTargetInfo();
+TargetInfo *getHexagonTargetInfo();
 TargetInfo *getPPC64TargetInfo();
 TargetInfo *getPPCTargetInfo();
 TargetInfo *getSPARCV9TargetInfo();
 TargetInfo *getX32TargetInfo();
 TargetInfo *getX86TargetInfo();
 TargetInfo *getX86_64TargetInfo();
 template <class ELFT> TargetInfo *getMipsTargetInfo();
 

lld/trunk/ELF/Target.cpp

TargetInfo *elf::getTarget() {
   case EM_AARCH64:
     return getAArch64TargetInfo();
   case EM_AMDGPU:
     return getAMDGPUTargetInfo();
   case EM_ARM:
     return getARMTargetInfo();
   case EM_AVR:
     return getAVRTargetInfo();
+  case EM_HEXAGON:
+    return getHexagonTargetInfo();
   case EM_MIPS:
     switch (Config->EKind) {
     case ELF32LEKind:
       return getMipsTargetInfo<ELF32LE>();
     case ELF32BEKind:
       return getMipsTargetInfo<ELF32BE>();
     case ELF64LEKind:
       return getMipsTargetInfo<ELF64LE>();

lld/trunk/test/ELF/Inputs/hexagon.s

+.global _start
+_start:
+  nop
+.global foo
+foo:
+  jumpr lr

lld/trunk/test/ELF/hexagon.s

+# REQUIRES: hexagon
+# RUN: llvm-mc -filetype=obj -triple=hexagon-unknown-elf %s -o %t
+# RUN: llvm-mc -filetype=obj -triple=hexagon-unknown-elf %S/Inputs/hexagon.s -o %t2
+# RUN: ld.lld %t2 %t  -o %t3
+# RUN: llvm-objdump -d  %t3 | FileCheck %s
+
+# R_HEX_B22_PCREL
+call #_start
+# CHECK: call 0x11000

lld/trunk/test/lit.cfg.py

 
 llvm_config.feature_config(
     [('--build-mode', {'DEBUG': 'debug'}),
      ('--assertion-mode', {'ON': 'asserts'}),
      ('--targets-built', {'AArch64': 'aarch64',
                           'AMDGPU': 'amdgpu',
                           'ARM': 'arm',
                           'AVR': 'avr',
+                          'Hexagon': 'hexagon',
                           'Mips': 'mips',
                           'PowerPC': 'ppc',
                           'Sparc': 'sparc',
                           'WebAssembly': 'wasm',
                           'X86': 'x86'})
      ])
 
 # Set a fake constant version so that we get consistent output.