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[AArch64][SVE] Add VScale Intrinsic

Authored by huntergr on Jun 5 2018, 5:34 AM.



Adds a new experimental vscale intrinsic to represent the runtime
multiple for scalable vectors.

Implements lowering/legalization for this in the AArch64 backend,
and a unit test for the SVE 'rdvl' instruction over scalable integer
vector types.

Part of the initial SVE codegen series, rfc will be posted soon. Note: this patch is currently just to support the scalable vector codegen rfc, and does not need a full review yet.

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Event Timeline

huntergr created this revision.Jun 5 2018, 5:34 AM
huntergr planned changes to this revision.Mar 22 2019, 3:00 AM

Needs to be updated with better isel patterns, instead of just the bare minimum required for demonstration.

huntergr abandoned this revision.Jan 23 2020, 6:46 AM

Superseded by D68203