[AArch64][SVE] Add VScale Intrinsic

[huntergr]

Summary

Adds a new experimental vscale intrinsic to represent the runtime
multiple for scalable vectors.

Implements lowering/legalization for this in the AArch64 backend,
and a unit test for the SVE 'rdvl' instruction over scalable integer
vector types.

Part of the initial SVE codegen series, rfc will be posted soon. Note: this patch is currently just to support the scalable vector codegen rfc, and does not need a full review yet.

[huntergr]

Needs to be updated with better isel patterns, instead of just the bare minimum required for demonstration.

[huntergr]

Superseded by D68203

include/llvm/IR/Intrinsics.td

 def int_experimental_vector_reduce_fmin : Intrinsic<[llvm_anyfloat_ty],
                                                     [llvm_anyvector_ty],
                                                     [IntrNoMem]>;
 
 //===----- Intrinsics that are used to provide predicate information -----===//
 
 def int_ssa_copy : Intrinsic<[llvm_any_ty], [LLVMMatchType<0>],
                              [IntrNoMem, Returned<0>]>;
+
+//===--------- Intrinsics that are used with scalable vector types --------===//
+
+def int_experimental_vector_vscale : Intrinsic<[llvm_anyint_ty],
+                                               [],
+                                               [IntrNoMem]>;
+
 //===----------------------------------------------------------------------===//
 // Target-specific intrinsics
 //===----------------------------------------------------------------------===//
 
 include "llvm/IR/IntrinsicsPowerPC.td"
 include "llvm/IR/IntrinsicsX86.td"
 include "llvm/IR/IntrinsicsARM.td"
 include "llvm/IR/IntrinsicsAArch64.td"
 include "llvm/IR/IntrinsicsXCore.td"
 include "llvm/IR/IntrinsicsHexagon.td"
 include "llvm/IR/IntrinsicsNVVM.td"
 include "llvm/IR/IntrinsicsMips.td"
 include "llvm/IR/IntrinsicsAMDGPU.td"
 include "llvm/IR/IntrinsicsBPF.td"
 include "llvm/IR/IntrinsicsSystemZ.td"
 include "llvm/IR/IntrinsicsWebAssembly.td"

lib/Target/AArch64/AArch64ISelLowering.h

enum NodeType : unsigned {
 
   SMULL,
   UMULL,
 
   // Reciprocal estimates and steps.
   FRECPE, FRECPS,
   FRSQRTE, FRSQRTS,
 
+  // SVE specific
+  /// VSCALE(IMM) - Returns the runtime scaling factor used to calculate the
+  /// number of elements within a scalable vector.  IMM is a constant integer
+  /// multiplier that is applied to the runtime value and is usual some
+  /// multiple of MVT.getVectorNumElements().
+  VSCALE,
+
   // NEON Load/Store with post-increment base updates
   LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
   LD3post,
   LD4post,
   ST2post,
   ST3post,
   ST4post,
   LD1x2post,

lib/Target/AArch64/AArch64ISelLowering.cpp

const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
   case AArch64ISD::ST3LANEpost:       return "AArch64ISD::ST3LANEpost";
   case AArch64ISD::ST4LANEpost:       return "AArch64ISD::ST4LANEpost";
   case AArch64ISD::SMULL:             return "AArch64ISD::SMULL";
   case AArch64ISD::UMULL:             return "AArch64ISD::UMULL";
   case AArch64ISD::FRECPE:            return "AArch64ISD::FRECPE";
   case AArch64ISD::FRECPS:            return "AArch64ISD::FRECPS";
   case AArch64ISD::FRSQRTE:           return "AArch64ISD::FRSQRTE";
   case AArch64ISD::FRSQRTS:           return "AArch64ISD::FRSQRTS";
+  case AArch64ISD::VSCALE:            return "AArch64ISD::VSCALE";
   }
   return nullptr;
 }
 
 MachineBasicBlock *
 AArch64TargetLowering::EmitF128CSEL(MachineInstr &MI,
                                     MachineBasicBlock *MBB) const {
   // We materialise the F128CSEL pseudo-instruction as some control flow and a
SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
   case Intrinsic::aarch64_neon_smax:
     return DAG.getNode(ISD::SMAX, dl, VT, Op.getOperand(1), Op.getOperand(2));
   case Intrinsic::aarch64_neon_umax:
     return DAG.getNode(ISD::UMAX, dl, VT, Op.getOperand(1), Op.getOperand(2));
   case Intrinsic::aarch64_neon_smin:
     return DAG.getNode(ISD::SMIN, dl, VT, Op.getOperand(1), Op.getOperand(2));
   case Intrinsic::aarch64_neon_umin:
     return DAG.getNode(ISD::UMIN, dl, VT, Op.getOperand(1), Op.getOperand(2));
+  case Intrinsic::experimental_vector_vscale: {
+    // TODO: Something smarter than just using a constant of 1
+    auto VScale = DAG.getNode(AArch64ISD::VSCALE, dl, MVT::i64,
+                              DAG.getConstant(1, dl, MVT::i32));
+    if (VT != MVT::i64)
+      VScale = DAG.getZExtOrTrunc(VScale, dl, VT);
+
+    return VScale;
+  }
   }
 }
 
 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
                                               SelectionDAG &DAG) const {
   LLVM_DEBUG(dbgs() << "Custom lowering: ");
   LLVM_DEBUG(Op.dump());
 

lib/Target/AArch64/AArch64SVEInstrInfo.td

 //=- AArch64SVEInstrInfo.td -  AArch64 SVE Instructions -*- tablegen -*-----=//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // AArch64 Scalable Vector Extension (SVE) Instruction definitions.
 //
 //===----------------------------------------------------------------------===//
 
+def SDT_AArch64VScale : SDTypeProfile<1, 1, [SDTCisVT<0,i64>, SDTCisInt<1>]>; 
+def AArch64vscale : SDNode<"AArch64ISD::VSCALE", SDT_AArch64VScale>;
 let Predicates = [HasSVE] in {
   defm ADD_ZZZ   : sve_int_bin_cons_arit_0<0b000, "add">;
   defm SUB_ZZZ   : sve_int_bin_cons_arit_0<0b001, "sub">;
 
   def AND_ZZZ : sve_int_bin_cons_log<0b00, "and">;
   def ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">;
   def EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">;
   def BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">;
let Predicates = [HasSVE] in {
   defm LSL_ZZI : sve_int_bin_cons_shift_b_left< 0b11, "lsl">;
 
   defm LSR_ZPmZ  : sve_int_bin_pred_shift_1<0b001, "lsr">;
   defm LSL_ZPmZ  : sve_int_bin_pred_shift_1<0b011, "lsl">;
 
   // InstAliases
   def : InstAlias<"mov $Zd, $Zn",
                   (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>;
+
+
+  // Simple codegen Patterns
+  // Unoptimized vscale
+  def : Pat<(AArch64vscale (simm6_32b:$imm)), (RDVLI_XI $imm)>;
+
 }

test/CodeGen/AArch64/SVE/rdvl.ll

+; RUN: llc -verify-machineinstrs -mattr=+sve < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-gnueabi"
+
+declare i64 @llvm.experimental.vector.vscale.i64()
+
+define i8 @rdvl_nxv16i8() {
+; CHECK-LABEL: rdvl_nxv16i8:
+; CHECK: orr [[MULT:w[0-9]+]], wzr, #0x1
+; CHECK-NEXT: rdvl x[[RDVL:[0-9]+]], [[MULT]]
+; CHECK-NEXT: lsl w0, w[[RDVL]], #4
+; CHECK-NEXT: ret
+  %vscale = call i64 @llvm.experimental.vector.vscale.i64()
+  %trunc = trunc i64 %vscale to i8
+  %eltcount = mul i8 %trunc, 16
+  ret i8 %eltcount
+}
+
+define i16 @rdvl_nxv8i16() {
+; CHECK-LABEL: rdvl_nxv8i16:
+; CHECK: orr [[MULT:w[0-9]+]], wzr, #0x1
+; CHECK-NEXT: rdvl x[[RDVL:[0-9]+]], [[MULT]]
+; CHECK-NEXT: lsl w0, w[[RDVL]], #3
+; CHECK-NEXT: ret
+  %vscale = call i64 @llvm.experimental.vector.vscale.i64()
+  %trunc = trunc i64 %vscale to i16
+  %eltcount = mul i16 %trunc, 8
+  ret i16 %eltcount
+}
+
+define i32 @rdvl_nxv4i32() {
+; CHECK-LABEL: rdvl_nxv4i32:
+; CHECK: orr [[MULT:w[0-9]+]], wzr, #0x1
+; CHECK-NEXT: rdvl x[[RDVL:[0-9]+]], [[MULT]]
+; CHECK-NEXT: lsl w0, w[[RDVL]], #2
+; CHECK-NEXT: ret
+  %vscale = call i64 @llvm.experimental.vector.vscale.i64()
+  %trunc = trunc i64 %vscale to i32
+  %eltcount = mul i32 %trunc, 4
+  ret i32 %eltcount
+}
+
+define i64 @rdvl_nxv2i64() {
+; CHECK-LABEL: rdvl_nxv2i64:
+; CHECK: orr [[MULT:w[0-9]+]], wzr, #0x1
+; CHECK-NEXT: rdvl x[[RDVL:[0-9]+]], [[MULT]]
+; CHECK-NEXT: lsl x0, x[[RDVL]], #1
+; CHECK-NEXT: ret
+  %vscale = call i64 @llvm.experimental.vector.vscale.i64()
+  %eltcount = mul i64 %vscale, 2
+  ret i64 %eltcount
+}