[AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions.

[sdesmalen]

Summary

The variants added by this patch are:

• SQINC signed increment, e.g. sqinc x0, w0, all, mul #4
• SQDEC signed decrement, e.g. sqdec x0, w0, all, mul #4
• UQINC unsigned increment, e.g. uqinc w0, all, mul #4
• UQDEC unsigned decrement, e.g. uqdec w0, all, mul #4

This patch includes asmparser changes to parse a GPR64 as a GPR32 in
order to satisfy the constraint check:

x0 == GPR64(w0)

in:

sqinc x0, w0, all, mul #4
       ^___^ (must match)

[samparker]

test/MC/AArch64/SVE/sqdecd-diagnostics.s

31

After the effort of producing useful diagnostics, why isn't this message so vague?

[sdesmalen]

test/MC/AArch64/SVE/sqdecd-diagnostics.s

31

Good point, I see that I wasn't yet using the DiagnosticPredicate for these operands. I'll fix this in a separate patch (because this also affects ptrue(s)).

[fhahn]

LGTM, given there are no objections in D47714

lib/Target/AArch64/AArch64InstrFormats.td

 def CondCode : AsmOperandClass {
   let Name = "CondCode";
   let DiagnosticType = "InvalidCondCode";
 }
 
 // A 32-bit register pasrsed as 64-bit
 def GPR32as64Operand : AsmOperandClass {
   let Name = "GPR32as64";
+  let ParserMethod =
+      "tryParseGPROperand<false, RegConstraintEqualityTy::EqualsSubReg>";
 }
 def GPR32as64 : RegisterOperand<GPR32> {
   let ParserMatchClass = GPR32as64Operand;
 }
 
+// A 64-bit register pasrsed as 32-bit
+def GPR64as32Operand : AsmOperandClass {
+  let Name = "GPR64as32";
+  let ParserMethod =
+      "tryParseGPROperand<false, RegConstraintEqualityTy::EqualsSuperReg>";
+}
+def GPR64as32 : RegisterOperand<GPR64, "printGPR64as32"> {
+  let ParserMatchClass = GPR64as32Operand;
+}
+
 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
 // are encoded as the eight bit value 'abcdefgh'.
 def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; }
 
 class UImmScaledMemoryIndexed<int Width, int Scale> : AsmOperandClass {
   let Name = "UImm" # Width # "s" # Scale;
   let DiagnosticType = "InvalidMemoryIndexed" # Scale # "UImm" # Width;

lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE] in {
   defm DECB_XPiI : sve_int_pred_pattern_a<0b001, "decb">;
   defm INCH_XPiI : sve_int_pred_pattern_a<0b010, "inch">;
   defm DECH_XPiI : sve_int_pred_pattern_a<0b011, "dech">;
   defm INCW_XPiI : sve_int_pred_pattern_a<0b100, "incw">;
   defm DECW_XPiI : sve_int_pred_pattern_a<0b101, "decw">;
   defm INCD_XPiI : sve_int_pred_pattern_a<0b110, "incd">;
   defm DECD_XPiI : sve_int_pred_pattern_a<0b111, "decd">;
 
+  defm SQINCB_XPiWdI : sve_int_pred_pattern_b_s32<0b00000, "sqincb">;
+  defm UQINCB_WPiI   : sve_int_pred_pattern_b_u32<0b00001, "uqincb">;
+  defm SQDECB_XPiWdI : sve_int_pred_pattern_b_s32<0b00010, "sqdecb">;
+  defm UQDECB_WPiI   : sve_int_pred_pattern_b_u32<0b00011, "uqdecb">;
   defm SQINCB_XPiI   : sve_int_pred_pattern_b_x64<0b00100, "sqincb">;
   defm UQINCB_XPiI   : sve_int_pred_pattern_b_x64<0b00101, "uqincb">;
   defm SQDECB_XPiI   : sve_int_pred_pattern_b_x64<0b00110, "sqdecb">;
   defm UQDECB_XPiI   : sve_int_pred_pattern_b_x64<0b00111, "uqdecb">;
 
+  defm SQINCH_XPiWdI : sve_int_pred_pattern_b_s32<0b01000, "sqinch">;
+  defm UQINCH_WPiI   : sve_int_pred_pattern_b_u32<0b01001, "uqinch">;
+  defm SQDECH_XPiWdI : sve_int_pred_pattern_b_s32<0b01010, "sqdech">;
+  defm UQDECH_WPiI   : sve_int_pred_pattern_b_u32<0b01011, "uqdech">;
   defm SQINCH_XPiI   : sve_int_pred_pattern_b_x64<0b01100, "sqinch">;
   defm UQINCH_XPiI   : sve_int_pred_pattern_b_x64<0b01101, "uqinch">;
   defm SQDECH_XPiI   : sve_int_pred_pattern_b_x64<0b01110, "sqdech">;
   defm UQDECH_XPiI   : sve_int_pred_pattern_b_x64<0b01111, "uqdech">;
 
+  defm SQINCW_XPiWdI : sve_int_pred_pattern_b_s32<0b10000, "sqincw">;
+  defm UQINCW_WPiI   : sve_int_pred_pattern_b_u32<0b10001, "uqincw">;
+  defm SQDECW_XPiWdI : sve_int_pred_pattern_b_s32<0b10010, "sqdecw">;
+  defm UQDECW_WPiI   : sve_int_pred_pattern_b_u32<0b10011, "uqdecw">;
   defm SQINCW_XPiI   : sve_int_pred_pattern_b_x64<0b10100, "sqincw">;
   defm UQINCW_XPiI   : sve_int_pred_pattern_b_x64<0b10101, "uqincw">;
   defm SQDECW_XPiI   : sve_int_pred_pattern_b_x64<0b10110, "sqdecw">;
   defm UQDECW_XPiI   : sve_int_pred_pattern_b_x64<0b10111, "uqdecw">;
 
+  defm SQINCD_XPiWdI : sve_int_pred_pattern_b_s32<0b11000, "sqincd">;
+  defm UQINCD_WPiI   : sve_int_pred_pattern_b_u32<0b11001, "uqincd">;
+  defm SQDECD_XPiWdI : sve_int_pred_pattern_b_s32<0b11010, "sqdecd">;
+  defm UQDECD_WPiI   : sve_int_pred_pattern_b_u32<0b11011, "uqdecd">;
   defm SQINCD_XPiI   : sve_int_pred_pattern_b_x64<0b11100, "sqincd">;
   defm UQINCD_XPiI   : sve_int_pred_pattern_b_x64<0b11101, "uqincd">;
   defm SQDECD_XPiI   : sve_int_pred_pattern_b_x64<0b11110, "sqdecd">;
   defm UQDECD_XPiI   : sve_int_pred_pattern_b_x64<0b11111, "uqdecd">;
 
   defm INDEX_RR : sve_int_index_rr<"index">;
   defm INDEX_IR : sve_int_index_ir<"index">;
   defm INDEX_RI : sve_int_index_ri<"index">;

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

 
 enum class RegKind {
   Scalar,
   NeonVector,
   SVEDataVector,
   SVEPredicateVector
 };
 
+enum RegConstraintEqualityTy {
+  EqualsReg,
+  EqualsSuperReg,
+  EqualsSubReg
+};
+
 class AArch64AsmParser : public MCTargetAsmParser {
 private:
   StringRef Mnemonic; ///< Instruction mnemonic.
 
   // Map of register aliases registers via the .req directive.
   StringMap<std::pair<RegKind, unsigned>> RegisterReqs;
 
   AArch64TargetStreamer &getTargetStreamer() {
private:
   unsigned matchRegisterNameAlias(StringRef Name, RegKind Kind);
   bool parseRegister(OperandVector &Operands);
   bool parseSymbolicImmVal(const MCExpr *&ImmVal);
   bool parseNeonVectorList(OperandVector &Operands);
   bool parseOptionalMulOperand(OperandVector &Operands);
   bool parseOperand(OperandVector &Operands, bool isCondCode,
                     bool invertCondCode);
 
-  bool showMatchError(SMLoc Loc, unsigned ErrCode, OperandVector &Operands);
+  bool showMatchError(SMLoc Loc, unsigned ErrCode, uint64_t ErrorInfo,
+                      OperandVector &Operands);
 
   bool parseDirectiveArch(SMLoc L);
   bool parseDirectiveCPU(SMLoc L);
   bool parseDirectiveInst(SMLoc L);
 
   bool parseDirectiveTLSDescCall(SMLoc L);
 
   bool parseDirectiveLOH(StringRef LOH, SMLoc L);
#include "AArch64GenAsmMatcher.inc"
   OperandMatchResultTy tryParseAdrLabel(OperandVector &Operands);
   OperandMatchResultTy tryParseFPImm(OperandVector &Operands);
   OperandMatchResultTy tryParseExactFPImm(OperandVector &Operands);
   OperandMatchResultTy tryParseImmWithOptionalShift(OperandVector &Operands);
   OperandMatchResultTy tryParseGPR64sp0Operand(OperandVector &Operands);
   bool tryParseNeonVectorRegister(OperandVector &Operands);
   OperandMatchResultTy tryParseVectorIndex(OperandVector &Operands);
   OperandMatchResultTy tryParseGPRSeqPair(OperandVector &Operands);
-  template <bool ParseShiftExtend>
+  template <bool ParseShiftExtend,
+            RegConstraintEqualityTy EqTy = RegConstraintEqualityTy::EqualsReg>
   OperandMatchResultTy tryParseGPROperand(OperandVector &Operands);
   template <bool ParseShiftExtend, bool ParseSuffix>
   OperandMatchResultTy tryParseSVEDataVector(OperandVector &Operands);
   OperandMatchResultTy tryParseSVEPredicateVector(OperandVector &Operands);
   template <RegKind VectorKind>
   OperandMatchResultTy tryParseVectorList(OperandVector &Operands,
                                           bool ExpectMatch = false);
   OperandMatchResultTy tryParseSVEPattern(OperandVector &Operands);
AArch64AsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
     Parser.addAliasForDirective(".hword", ".2byte");
     Parser.addAliasForDirective(".word", ".4byte");
     Parser.addAliasForDirective(".xword", ".8byte");
 
     // Initialize the set of available features.
     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
   }
 
+  bool regsEqual(const MCParsedAsmOperand &Op1,
+                 const MCParsedAsmOperand &Op2) const override;
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
   bool ParseDirective(AsmToken DirectiveID) override;
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
                                       unsigned Kind) override;
 
   static bool classifySymbolRef(const MCExpr *Expr,
struct ShiftExtendOp {
     bool HasExplicitAmount;
   };
 
   struct RegOp {
     unsigned RegNum;
     RegKind Kind;
     int ElementWidth;
 
+    // The register may be allowed as a different register class,
+    // e.g. for GPR64as32 or GPR32as64.
+    RegConstraintEqualityTy EqualityTy;
+
     // In some cases the shift/extend needs to be explicitly parsed together
     // with the register, rather than as a separate operand. This is needed
     // for addressing modes where the instruction as a whole dictates the
     // scaling/extend, rather than specific bits in the instruction.
     // By parsing them as a single operand, we avoid the need to pass an
     // extra operand in all CodeGen patterns (because all operands need to
     // have an associated value), and we avoid the need to update TableGen to
     // accept operands that have no associated bits in the instruction.
StringRef getBarrierName() const {
     return StringRef(Barrier.Data, Barrier.Length);
   }
 
   unsigned getReg() const override {
     assert(Kind == k_Register && "Invalid access!");
     return Reg.RegNum;
   }
 
+  RegConstraintEqualityTy getRegEqualityTy() const {
+    assert(Kind == k_Register && "Invalid access!");
+    return Reg.EqualityTy;
+  }
+
   unsigned getVectorListStart() const {
     assert(Kind == k_VectorList && "Invalid access!");
     return VectorList.RegNum;
   }
 
   unsigned getVectorListCount() const {
     assert(Kind == k_VectorList && "Invalid access!");
     return VectorList.Count;
DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
     return DiagnosticPredicateTy::NearMatch;
   }
 
   bool isGPR32as64() const {
     return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
       AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);
   }
 
+  bool isGPR64as32() const {
+    return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
+      AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.RegNum);
+  }
+
   bool isWSeqPair() const {
     return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
            AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID].contains(
                Reg.RegNum);
   }
 
   bool isXSeqPair() const {
     return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
void addGPR32as64Operands(MCInst &Inst, unsigned N) const {
 
     const MCRegisterInfo *RI = Ctx.getRegisterInfo();
     uint32_t Reg = RI->getRegClass(AArch64::GPR32RegClassID).getRegister(
         RI->getEncodingValue(getReg()));
 
     Inst.addOperand(MCOperand::createReg(Reg));
   }
 
+  void addGPR64as32Operands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    assert(
+        AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(getReg()));
+
+    const MCRegisterInfo *RI = Ctx.getRegisterInfo();
+    uint32_t Reg = RI->getRegClass(AArch64::GPR64RegClassID).getRegister(
+        RI->getEncodingValue(getReg()));
+
+    Inst.addOperand(MCOperand::createReg(Reg));
+  }
+
   template <int Width>
   void addFPRasZPRRegOperands(MCInst &Inst, unsigned N) const {
     unsigned Base;
     switch (Width) {
     case 8:   Base = AArch64::B0; break;
     case 16:  Base = AArch64::H0; break;
     case 32:  Base = AArch64::S0; break;
     case 64:  Base = AArch64::D0; break;
CreateToken(StringRef Str, bool IsSuffix, SMLoc S, MCContext &Ctx) {
     Op->Tok.IsSuffix = IsSuffix;
     Op->StartLoc = S;
     Op->EndLoc = S;
     return Op;
   }
 
   static std::unique_ptr<AArch64Operand>
   CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx,
+            RegConstraintEqualityTy EqTy = RegConstraintEqualityTy::EqualsReg,
             AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL,
             unsigned ShiftAmount = 0,
             unsigned HasExplicitAmount = false) {
     auto Op = make_unique<AArch64Operand>(k_Register, Ctx);
     Op->Reg.RegNum = RegNum;
     Op->Reg.Kind = Kind;
     Op->Reg.ElementWidth = 0;
+    Op->Reg.EqualityTy = EqTy;
     Op->Reg.ShiftExtend.Type = ExtTy;
     Op->Reg.ShiftExtend.Amount = ShiftAmount;
     Op->Reg.ShiftExtend.HasExplicitAmount = HasExplicitAmount;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
   }
 
   static std::unique_ptr<AArch64Operand>
   CreateVectorReg(unsigned RegNum, RegKind Kind, unsigned ElementWidth,
                   SMLoc S, SMLoc E, MCContext &Ctx,
                   AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL,
                   unsigned ShiftAmount = 0,
                   unsigned HasExplicitAmount = false) {
     assert((Kind == RegKind::NeonVector || Kind == RegKind::SVEDataVector ||
             Kind == RegKind::SVEPredicateVector) &&
            "Invalid vector kind");
-    auto Op = CreateReg(RegNum, Kind, S, E, Ctx, ExtTy, ShiftAmount,
+    auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount,
                         HasExplicitAmount);
     Op->Reg.ElementWidth = ElementWidth;
     return Op;
   }
 
   static std::unique_ptr<AArch64Operand>
   CreateVectorList(unsigned RegNum, unsigned Count, unsigned NumElements,
                    unsigned ElementWidth, RegKind RegisterKind, SMLoc S, SMLoc E,
if (getParser().parseExpression(ImmVal) || !isa<MCConstantExpr>(ImmVal) ||
     return MatchOperand_ParseFail;
   }
 
   Operands.push_back(AArch64Operand::CreateReg(
       RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext()));
   return MatchOperand_Success;
 }
 
-template <bool ParseShiftExtend>
+template <bool ParseShiftExtend, RegConstraintEqualityTy EqTy>
 OperandMatchResultTy
 AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) {
   SMLoc StartLoc = getLoc();
 
   unsigned RegNum;
   OperandMatchResultTy Res = tryParseScalarRegister(RegNum);
   if (Res != MatchOperand_Success)
     return Res;
 
   // No shift/extend is the default.
   if (!ParseShiftExtend || getParser().getTok().isNot(AsmToken::Comma)) {
     Operands.push_back(AArch64Operand::CreateReg(
-        RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext()));
+        RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext(), EqTy));
     return MatchOperand_Success;
   }
 
   // Eat the comma
   getParser().Lex();
 
   // Match the shift
   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> ExtOpnd;
   Res = tryParseOptionalShiftExtend(ExtOpnd);
   if (Res != MatchOperand_Success)
     return Res;
 
   auto Ext = static_cast<AArch64Operand*>(ExtOpnd.back().get());
-  Operands.push_back(AArch64Operand::CreateReg(RegNum, RegKind::Scalar,
-                     StartLoc, Ext->getEndLoc(), getContext(),
-                     Ext->getShiftExtendType(), Ext->getShiftExtendAmount(),
-                     Ext->hasShiftExtendAmount()));
+  Operands.push_back(AArch64Operand::CreateReg(
+      RegNum, RegKind::Scalar, StartLoc, Ext->getEndLoc(), getContext(), EqTy,
 
   return MatchOperand_Success;
 }
 
 bool AArch64AsmParser::parseOptionalMulOperand(OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
 
   // Some SVE instructions have a decoration after the immediate, i.e.
case AsmToken::Equal: {
     const MCExpr *CPLoc =
         getTargetStreamer().addConstantPoolEntry(SubExprVal, IsXReg ? 8 : 4, Loc);
     Operands.push_back(AArch64Operand::CreateImm(CPLoc, S, E, Ctx));
     return false;
   }
   }
 }
 
+bool AArch64AsmParser::regsEqual(const MCParsedAsmOperand &Op1,
+                                 const MCParsedAsmOperand &Op2) const {
+  auto &AOp1 = static_cast<const AArch64Operand&>(Op1);
+  auto &AOp2 = static_cast<const AArch64Operand&>(Op2);
+  if (AOp1.getRegEqualityTy() == RegConstraintEqualityTy::EqualsReg &&
+      AOp2.getRegEqualityTy() == RegConstraintEqualityTy::EqualsReg)
+    return MCTargetAsmParser::regsEqual(Op1, Op2);
+
+  assert(AOp1.isScalarReg() && AOp2.isScalarReg() &&
+         "Testing equality of non-scalar registers not supported");
+
+  // Check if a registers match their sub/super register classes.
+  if (AOp1.getRegEqualityTy() == EqualsSuperReg)
+    return getXRegFromWReg(Op1.getReg()) == Op2.getReg();
+  if (AOp1.getRegEqualityTy() == EqualsSubReg)
+    return getWRegFromXReg(Op1.getReg()) == Op2.getReg();
+  if (AOp2.getRegEqualityTy() == EqualsSuperReg)
+    return getXRegFromWReg(Op2.getReg()) == Op1.getReg();
+  if (AOp2.getRegEqualityTy() == EqualsSubReg)
+    return getWRegFromXReg(Op2.getReg()) == Op1.getReg();
+
+  return false;
+}
+
 /// ParseInstruction - Parse an AArch64 instruction mnemonic followed by its
 /// operands.
 bool AArch64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
                                         StringRef Name, SMLoc NameLoc,
                                         OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
   Name = StringSwitch<StringRef>(Name.lower())
              .Case("beq", "b.eq")
default:
     return false;
   }
 }
 
 static std::string AArch64MnemonicSpellCheck(StringRef S, uint64_t FBS,
                                              unsigned VariantID = 0);
 
 bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
+                                      uint64_t ErrorInfo,
                                       OperandVector &Operands) {
   switch (ErrCode) {
-  case Match_InvalidTiedOperand:
+  case Match_InvalidTiedOperand: {
+    RegConstraintEqualityTy EqTy =
+        static_cast<const AArch64Operand &>(*Operands[ErrorInfo])
+            .getRegEqualityTy();
+    switch (EqTy) {
+    case RegConstraintEqualityTy::EqualsSubReg:
+      return Error(Loc, "operand must be 64-bit form of destination register");
+    case RegConstraintEqualityTy::EqualsSuperReg:
+      return Error(Loc, "operand must be 32-bit form of destination register");
+    case RegConstraintEqualityTy::EqualsReg:
       return Error(Loc, "operand must match destination register");
+    default:
+      llvm_unreachable("Unsupported case");
+    }
+  }
   case Match_MissingFeature:
     return Error(Loc,
                  "instruction requires a CPU feature not currently enabled");
   case Match_InvalidOperand:
     return Error(Loc, "invalid operand for instruction");
   case Match_InvalidSuffix:
     return Error(Loc, "invalid type suffix for instruction");
   case Match_InvalidCondCode:
for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
         Msg += " ";
         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
       }
       Mask <<= 1;
     }
     return Error(IDLoc, Msg);
   }
   case Match_MnemonicFail:
-    return showMatchError(IDLoc, MatchResult, Operands);
+    return showMatchError(IDLoc, MatchResult, ErrorInfo, Operands);
   case Match_InvalidOperand: {
     SMLoc ErrorLoc = IDLoc;
 
     if (ErrorInfo != ~0ULL) {
       if (ErrorInfo >= Operands.size())
         return Error(IDLoc, "too few operands for instruction",
                      SMRange(IDLoc, getTok().getLoc()));
 
       ErrorLoc = ((AArch64Operand &)*Operands[ErrorInfo]).getStartLoc();
       if (ErrorLoc == SMLoc())
         ErrorLoc = IDLoc;
     }
     // If the match failed on a suffix token operand, tweak the diagnostic
     // accordingly.
     if (((AArch64Operand &)*Operands[ErrorInfo]).isToken() &&
         ((AArch64Operand &)*Operands[ErrorInfo]).isTokenSuffix())
       MatchResult = Match_InvalidSuffix;
 
-    return showMatchError(ErrorLoc, MatchResult, Operands);
+    return showMatchError(ErrorLoc, MatchResult, ErrorInfo, Operands);
   }
   case Match_InvalidTiedOperand:
   case Match_InvalidMemoryIndexed1:
   case Match_InvalidMemoryIndexed2:
   case Match_InvalidMemoryIndexed4:
   case Match_InvalidMemoryIndexed8:
   case Match_InvalidMemoryIndexed16:
   case Match_InvalidCondCode:
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_MRS: {
     if (ErrorInfo >= Operands.size())
       return Error(IDLoc, "too few operands for instruction", SMRange(IDLoc, (*Operands.back()).getEndLoc()));
     // Any time we get here, there's nothing fancy to do. Just get the
     // operand SMLoc and display the diagnostic.
     SMLoc ErrorLoc = ((AArch64Operand &)*Operands[ErrorInfo]).getStartLoc();
     if (ErrorLoc == SMLoc())
       ErrorLoc = IDLoc;
-    return showMatchError(ErrorLoc, MatchResult, Operands);
+    return showMatchError(ErrorLoc, MatchResult, ErrorInfo, Operands);
   }
   }
 
   llvm_unreachable("Implement any new match types added!");
 }
 
 /// ParseDirective parses the arm specific directives
 bool AArch64AsmParser::ParseDirective(AsmToken DirectiveID) {

lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h

protected:
   template <typename T>
   void printSVELogicalImm(const MCInst *MI, unsigned OpNum,
                           const MCSubtargetInfo &STI, raw_ostream &O);
   void printSVEPattern(const MCInst *MI, unsigned OpNum,
                        const MCSubtargetInfo &STI, raw_ostream &O);
   template <char = 0>
   void printSVERegOp(const MCInst *MI, unsigned OpNum,
                     const MCSubtargetInfo &STI, raw_ostream &O);
+  void printGPR64as32(const MCInst *MI, unsigned OpNum,
+                      const MCSubtargetInfo &STI, raw_ostream &O);
   template <int Width>
   void printZPRasFPR(const MCInst *MI, unsigned OpNum,
                      const MCSubtargetInfo &STI, raw_ostream &O);
   template <unsigned ImmIs0, unsigned ImmIs1>
   void printExactFPImm(const MCInst *MI, unsigned OpNum,
                        const MCSubtargetInfo &STI, raw_ostream &O);
 };
 

lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp

 void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
                                          const MCSubtargetInfo &STI,
                                          raw_ostream  &O) {
   auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
   auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
   unsigned Val = MI->getOperand(OpNum).getImm();
   O << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr);
 }
+
+void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
+                                        const MCSubtargetInfo &STI,
+                                        raw_ostream &O) {
+  unsigned Reg = MI->getOperand(OpNum).getReg();
+  O << getRegisterName(getWRegFromXReg(Reg));
+}

lib/Target/AArch64/SVEInstrFormats.td

: I<(outs dt:$Rdn), (ins st:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
   let Inst{21}    = 0b1;
   let Inst{20}    = opc{2};
   let Inst{19-16} = imm4;
   let Inst{15-12} = 0b1111;
   let Inst{11-10} = opc{1-0};
   let Inst{9-5}   = pattern;
   let Inst{4-0}   = Rdn;
 
+  // Signed 32bit forms require their GPR operand printed.
+  let AsmString = !if(!eq(opc{2,0}, 0b00),
+                      !strconcat(asm, "\t$Rdn, $_Rdn, $pattern, mul $imm4"),
+                      !strconcat(asm, "\t$Rdn, $pattern, mul $imm4"));
+
   let Constraints = "$Rdn = $_Rdn";
 }
 
+multiclass sve_int_pred_pattern_b_s32<bits<5> opc, string asm> {
+  def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64as32>;
+
+  def : InstAlias<asm # "\t$Rd, $Rn, $pattern",
+                  (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1), 1>;
+  def : InstAlias<asm # "\t$Rd, $Rn",
+                  (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, 0b11111, 1), 2>;
+}
+
+multiclass sve_int_pred_pattern_b_u32<bits<5> opc, string asm> {
+  def NAME : sve_int_pred_pattern_b<opc, asm, GPR32z, GPR32z>;
+
+  def : InstAlias<asm # "\t$Rdn, $pattern",
+                  (!cast<Instruction>(NAME) GPR32z:$Rdn, sve_pred_enum:$pattern, 1), 1>;
+  def : InstAlias<asm # "\t$Rdn",
+                  (!cast<Instruction>(NAME) GPR32z:$Rdn, 0b11111, 1), 2>;
+}
+
 multiclass sve_int_pred_pattern_b_x64<bits<5> opc, string asm> {
   def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64z>;
 
   def : InstAlias<asm # "\t$Rdn, $pattern",
                   (!cast<Instruction>(NAME) GPR64z:$Rdn, sve_pred_enum:$pattern, 1), 1>;
   def : InstAlias<asm # "\t$Rdn",
                   (!cast<Instruction>(NAME) GPR64z:$Rdn, 0b11111, 1), 2>;
 }

test/MC/AArch64/SVE/sqdecb-diagnostics.s

 
 sqdecb sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: sqdecb sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqdecb x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqdecb x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecb x0, x1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecb x0, x1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqdecb x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: sqdecb x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sqdecb x0, all, mul #0

test/MC/AArch64/SVE/sqdecb.s

 sqdecb  x0, all, mul #16
 // CHECK-INST: sqdecb  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xfb,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 fb 3f 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqdecb  x0, w0
+// CHECK-INST: sqdecb  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 20 04 <unknown>
+
+sqdecb  x0, w0, all
+// CHECK-INST: sqdecb  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 20 04 <unknown>
+
+sqdecb  x0, w0, all, mul #1
+// CHECK-INST: sqdecb  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 20 04 <unknown>
+
+sqdecb  x0, w0, all, mul #16
+// CHECK-INST: sqdecb  x0, w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xfb,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 2f 04 <unknown>
+
+sqdecb  x0, w0, pow2
+// CHECK-INST: sqdecb  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf8,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 20 04 <unknown>
+
+sqdecb  x0, w0, pow2, mul #16
+// CHECK-INST: sqdecb  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf8,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 2f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 sqdecb  x0, pow2
 // CHECK-INST: sqdecb  x0, pow2
 // CHECK-ENCODING: [0x00,0xf8,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 f8 30 04 <unknown>

test/MC/AArch64/SVE/sqdecd-diagnostics.s

 
 sqdecd sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: sqdecd sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqdecd x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqdecd x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecd x0, x1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecd x0, x1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqdecd x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: sqdecd x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sqdecd x0, all, mul #0

test/MC/AArch64/SVE/sqdecd.s

 sqdecd  x0, all, mul #16
 // CHECK-INST: sqdecd  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xfb,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 fb ff 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqdecd  x0, w0
+// CHECK-INST: sqdecd  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb e0 04 <unknown>
+
+sqdecd  x0, w0, all
+// CHECK-INST: sqdecd  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb e0 04 <unknown>
+
+sqdecd  x0, w0, all, mul #1
+// CHECK-INST: sqdecd  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb e0 04 <unknown>
+
+sqdecd  x0, w0, all, mul #16
+// CHECK-INST: sqdecd  x0, w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xfb,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb ef 04 <unknown>
+
+sqdecd  x0, w0, pow2
+// CHECK-INST: sqdecd  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf8,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 e0 04 <unknown>
+
+sqdecd  x0, w0, pow2, mul #16
+// CHECK-INST: sqdecd  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf8,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 ef 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 sqdecd  x0, pow2
 // CHECK-INST: sqdecd  x0, pow2
 // CHECK-ENCODING: [0x00,0xf8,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 f8 f0 04 <unknown>

test/MC/AArch64/SVE/sqdech-diagnostics.s

 
 sqdech sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: sqdech sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqdech x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqdech x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdech x0, x1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdech x0, x1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqdech x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: sqdech x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sqdech x0, all, mul #0

test/MC/AArch64/SVE/sqdech.s

 sqdech  x0, all, mul #16
 // CHECK-INST: sqdech  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xfb,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 fb 7f 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqdech  x0, w0
+// CHECK-INST: sqdech  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 60 04 <unknown>
+
+sqdech  x0, w0, all
+// CHECK-INST: sqdech  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 60 04 <unknown>
+
+sqdech  x0, w0, all, mul #1
+// CHECK-INST: sqdech  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 60 04 <unknown>
+
+sqdech  x0, w0, all, mul #16
+// CHECK-INST: sqdech  x0, w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xfb,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 6f 04 <unknown>
+
+sqdech  x0, w0, pow2
+// CHECK-INST: sqdech  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf8,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 60 04 <unknown>
+
+sqdech  x0, w0, pow2, mul #16
+// CHECK-INST: sqdech  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf8,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 6f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 sqdech  x0, pow2
 // CHECK-INST: sqdech  x0, pow2
 // CHECK-ENCODING: [0x00,0xf8,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 f8 70 04 <unknown>

test/MC/AArch64/SVE/sqdecw-diagnostics.s

 
 sqdecw sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: sqdecw sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqdecw x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqdecw x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecw x0, x1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecw x0, x1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqdecw x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: sqdecw x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sqdecw x0, all, mul #0

test/MC/AArch64/SVE/sqdecw.s

 sqdecw  x0, all, mul #16
 // CHECK-INST: sqdecw  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xfb,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 fb bf 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqdecw  x0, w0
+// CHECK-INST: sqdecw  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb a0 04 <unknown>
+
+sqdecw  x0, w0, all
+// CHECK-INST: sqdecw  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb a0 04 <unknown>
+
+sqdecw  x0, w0, all, mul #1
+// CHECK-INST: sqdecw  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb a0 04 <unknown>
+
+sqdecw  x0, w0, all, mul #16
+// CHECK-INST: sqdecw  x0, w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xfb,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb af 04 <unknown>
+
+sqdecw  x0, w0, pow2
+// CHECK-INST: sqdecw  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf8,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 a0 04 <unknown>
+
+sqdecw  x0, w0, pow2, mul #16
+// CHECK-INST: sqdecw  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf8,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 af 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 sqdecw  x0, pow2
 // CHECK-INST: sqdecw  x0, pow2
 // CHECK-ENCODING: [0x00,0xf8,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 f8 b0 04 <unknown>

test/MC/AArch64/SVE/sqincb-diagnostics.s

 
 sqincb sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: sqincb sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqincb x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqincb x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincb x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincb x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqincb x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: sqincb x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sqincb x0, all, mul #0

test/MC/AArch64/SVE/sqincb.s

 sqincb  x0, all, mul #16
 // CHECK-INST: sqincb  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf3,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 f3 3f 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqincb  x0, w0
+// CHECK-INST: sqincb  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 20 04 <unknown>
+
+sqincb  x0, w0, all
+// CHECK-INST: sqincb  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 20 04 <unknown>
+
+sqincb  x0, w0, all, mul #1
+// CHECK-INST: sqincb  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 20 04 <unknown>
+
+sqincb  x0, w0, all, mul #16
+// CHECK-INST: sqincb  x0, w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf3,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 2f 04 <unknown>
+
+sqincb  x0, w0, pow2
+// CHECK-INST: sqincb  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf0,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 20 04 <unknown>
+
+sqincb  x0, w0, pow2, mul #16
+// CHECK-INST: sqincb  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf0,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 2f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 sqincb  x0, pow2
 // CHECK-INST: sqincb  x0, pow2
 // CHECK-ENCODING: [0x00,0xf0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 f0 30 04 <unknown>

test/MC/AArch64/SVE/sqincd-diagnostics.s

 
 sqincd sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: sqincd sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqincd x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqincd x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincd x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincd x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqincd x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: sqincd x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sqincd x0, all, mul #0

test/MC/AArch64/SVE/sqincd.s

 sqincd  x0, all, mul #16
 // CHECK-INST: sqincd  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf3,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 f3 ff 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqincd  x0, w0
+// CHECK-INST: sqincd  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 e0 04 <unknown>
+
+sqincd  x0, w0, all
+// CHECK-INST: sqincd  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 e0 04 <unknown>
+
+sqincd  x0, w0, all, mul #1
+// CHECK-INST: sqincd  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 e0 04 <unknown>
+
+sqincd  x0, w0, all, mul #16
+// CHECK-INST: sqincd  x0, w0, all
+// CHECK-ENCODING: [0xe0,0xf3,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 ef 04 <unknown>
+
+sqincd  x0, w0, pow2
+// CHECK-INST: sqincd  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf0,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 e0 04 <unknown>
+
+sqincd  x0, w0, pow2, mul #16
+// CHECK-INST: sqincd  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf0,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 ef 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 sqincd  x0, pow2
 // CHECK-INST: sqincd  x0, pow2
 // CHECK-ENCODING: [0x00,0xf0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 f0 f0 04 <unknown>

test/MC/AArch64/SVE/sqinch-diagnostics.s

 
 sqinch sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: sqinch sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqinch x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqinch x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqinch x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqinch x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqinch x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: sqinch x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sqinch x0, all, mul #0

test/MC/AArch64/SVE/sqinch.s

 sqinch  x0, all, mul #16
 // CHECK-INST: sqinch  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf3,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 f3 7f 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqinch  x0, w0
+// CHECK-INST: sqinch  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 60 04 <unknown>
+
+sqinch  x0, w0, all
+// CHECK-INST: sqinch  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 60 04 <unknown>
+
+sqinch  x0, w0, all, mul #1
+// CHECK-INST: sqinch  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 60 04 <unknown>
+
+sqinch  x0, w0, all, mul #16
+// CHECK-INST: sqinch  x0, w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf3,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 6f 04 <unknown>
+
+sqinch  x0, w0, pow2
+// CHECK-INST: sqinch  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf0,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 60 04 <unknown>
+
+sqinch  x0, w0, pow2, mul #16
+// CHECK-INST: sqinch  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf0,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 6f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 sqinch  x0, pow2
 // CHECK-INST: sqinch  x0, pow2
 // CHECK-ENCODING: [0x00,0xf0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 f0 70 04 <unknown>

test/MC/AArch64/SVE/sqincw-diagnostics.s

 
 sqincw sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: sqincw sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqincw x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqincw x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincw x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincw x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqincw x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: sqincw x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sqincw x0, all, mul #0

test/MC/AArch64/SVE/sqincw.s

 sqincw  x0, all, mul #16
 // CHECK-INST: sqincw  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf3,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 f3 bf 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqincw  x0, w0
+// CHECK-INST: sqincw  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
+
+sqincw  x0, w0, all
+// CHECK-INST: sqincw  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
+
+sqincw  x0, w0, all, mul #1
+// CHECK-INST: sqincw  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
+
+sqincw  x0, w0, all, mul #16
+// CHECK-INST: sqincw  x0, w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf3,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 af 04 <unknown>
+
+sqincw  x0, w0, pow2
+// CHECK-INST: sqincw  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf0,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 a0 04 <unknown>
+
+sqincw  x0, w0, pow2, mul #16
+// CHECK-INST: sqincw  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf0,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 af 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 sqincw  x0, pow2
 // CHECK-INST: sqincw  x0, pow2
 // CHECK-ENCODING: [0x00,0xf0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 f0 b0 04 <unknown>

test/MC/AArch64/SVE/uqdecb-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqdecb w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqdecb w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqdecb wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqdecb wsp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqdecb sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqdecb sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned dec only has one register operand)
+
+uqdecb x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecb x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecb w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecb w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecb x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecb x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqdecb x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: uqdecb x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqdecb x0, all, mul #0

test/MC/AArch64/SVE/uqdecb.s

 uqdecb  x0, all, mul #16
 // CHECK-INST: uqdecb  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xff,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 ff 3f 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqdecb  w0
+// CHECK-INST: uqdecb  w0
+// CHECK-ENCODING: [0xe0,0xff,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 20 04 <unknown>
+
+uqdecb  w0, all
+// CHECK-INST: uqdecb  w0
+// CHECK-ENCODING: [0xe0,0xff,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 20 04 <unknown>
+
+uqdecb  w0, all, mul #1
+// CHECK-INST: uqdecb  w0
+// CHECK-ENCODING: [0xe0,0xff,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 20 04 <unknown>
+
+uqdecb  w0, all, mul #16
+// CHECK-INST: uqdecb  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xff,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 2f 04 <unknown>
+
+uqdecb  w0, pow2
+// CHECK-INST: uqdecb  w0, pow2
+// CHECK-ENCODING: [0x00,0xfc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc 20 04 <unknown>
+
+uqdecb  w0, pow2, mul #16
+// CHECK-INST: uqdecb  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xfc,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc 2f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 uqdecb  x0, pow2
 // CHECK-INST: uqdecb  x0, pow2
 // CHECK-ENCODING: [0x00,0xfc,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 fc 30 04 <unknown>

test/MC/AArch64/SVE/uqdecd-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqdecd w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqdecd w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqdecd wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqdecd wsp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqdecd sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqdecd sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned dec only has one register operand)
+
+uqdecd x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecd x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecd w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecd w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecd x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecd x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqdecd x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: uqdecd x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqdecd x0, all, mul #0

test/MC/AArch64/SVE/uqdecd.s

 uqdecd  x0, all, mul #16
 // CHECK-INST: uqdecd  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xff,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 ff ff 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqdecd  w0
+// CHECK-INST: uqdecd  w0
+// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff e0 04 <unknown>
+
+uqdecd  w0, all
+// CHECK-INST: uqdecd  w0
+// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff e0 04 <unknown>
+
+uqdecd  w0, all, mul #1
+// CHECK-INST: uqdecd  w0
+// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff e0 04 <unknown>
+
+uqdecd  w0, all, mul #16
+// CHECK-INST: uqdecd  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xff,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff ef 04 <unknown>
+
+uqdecd  w0, pow2
+// CHECK-INST: uqdecd  w0, pow2
+// CHECK-ENCODING: [0x00,0xfc,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc e0 04 <unknown>
+
+uqdecd  w0, pow2, mul #16
+// CHECK-INST: uqdecd  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xfc,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc ef 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 uqdecd  x0, pow2
 // CHECK-INST: uqdecd  x0, pow2
 // CHECK-ENCODING: [0x00,0xfc,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 fc f0 04 <unknown>

test/MC/AArch64/SVE/uqdech-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqdech w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqdech w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqdech wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqdech wsp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqdech sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqdech sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned dec only has one register operand)
+
+uqdech x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdech x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdech w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdech w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdech x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdech x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqdech x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: uqdech x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqdech x0, all, mul #0

test/MC/AArch64/SVE/uqdech.s

 uqdech  x0, all, mul #16
 // CHECK-INST: uqdech  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xff,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 ff 7f 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqdech  w0
+// CHECK-INST: uqdech  w0
+// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
+
+uqdech  w0, all
+// CHECK-INST: uqdech  w0
+// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
+
+uqdech  w0, all, mul #1
+// CHECK-INST: uqdech  w0
+// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
+
+uqdech  w0, all, mul #16
+// CHECK-INST: uqdech  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xff,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 6f 04 <unknown>
+
+uqdech  w0, pow2
+// CHECK-INST: uqdech  w0, pow2
+// CHECK-ENCODING: [0x00,0xfc,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc 60 04 <unknown>
+
+uqdech  w0, pow2, mul #16
+// CHECK-INST: uqdech  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xfc,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc 6f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 uqdech  x0, pow2
 // CHECK-INST: uqdech  x0, pow2
 // CHECK-ENCODING: [0x00,0xfc,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 fc 70 04 <unknown>

test/MC/AArch64/SVE/uqdecw-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqdecw w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqdecw w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqdecw wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqdecw wsp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqdecw sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqdecw sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned dec only has one register operand)
+
+uqdecw x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecw x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecw w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecw w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecw x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecw x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqdecw x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: uqdecw x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqdecw x0, all, mul #0

test/MC/AArch64/SVE/uqdecw.s

 uqdecw  x0, all, mul #16
 // CHECK-INST: uqdecw  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xff,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 ff bf 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqdecw  w0
+// CHECK-INST: uqdecw  w0
+// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff a0 04 <unknown>
+
+uqdecw  w0, all
+// CHECK-INST: uqdecw  w0
+// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff a0 04 <unknown>
+
+uqdecw  w0, all, mul #1
+// CHECK-INST: uqdecw  w0
+// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff a0 04 <unknown>
+
+uqdecw  w0, all, mul #16
+// CHECK-INST: uqdecw  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xff,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff af 04 <unknown>
+
+uqdecw  w0, pow2
+// CHECK-INST: uqdecw  w0, pow2
+// CHECK-ENCODING: [0x00,0xfc,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc a0 04 <unknown>
+
+uqdecw  w0, pow2, mul #16
+// CHECK-INST: uqdecw  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xfc,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc af 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 uqdecw  x0, pow2
 // CHECK-INST: uqdecw  x0, pow2
 // CHECK-ENCODING: [0x00,0xfc,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 fc b0 04 <unknown>

test/MC/AArch64/SVE/uqincb-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqincb w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqincb w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqincb wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqincb wsp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqincb sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqincb sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned inc only has one register operand)
+
+uqincb x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincb x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincb w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincb w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincb x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincb x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqincb x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: uqincb x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqincb x0, all, mul #0

test/MC/AArch64/SVE/uqincb.s

 uqincb  x0, all, mul #16
 // CHECK-INST: uqincb  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf7,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 f7 3f 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqincb  w0
+// CHECK-INST: uqincb  w0
+// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 20 04 <unknown>
+
+uqincb  w0, all
+// CHECK-INST: uqincb  w0
+// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 20 04 <unknown>
+
+uqincb  w0, all, mul #1
+// CHECK-INST: uqincb  w0
+// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 20 04 <unknown>
+
+uqincb  w0, all, mul #16
+// CHECK-INST: uqincb  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf7,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 2f 04 <unknown>
+
+uqincb  w0, pow2
+// CHECK-INST: uqincb  w0, pow2
+// CHECK-ENCODING: [0x00,0xf4,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 20 04 <unknown>
+
+uqincb  w0, pow2, mul #16
+// CHECK-INST: uqincb  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf4,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 2f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 uqincb  x0, pow2
 // CHECK-INST: uqincb  x0, pow2
 // CHECK-ENCODING: [0x00,0xf4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 f4 30 04 <unknown>

test/MC/AArch64/SVE/uqincd-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqincd w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqincd w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqincd wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqincd wsp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqincd sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqincd sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned inc only has one register operand)
+
+uqincd x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincd x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincd w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincd w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincd x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincd x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqincd x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: uqincd x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqincd x0, all, mul #0

test/MC/AArch64/SVE/uqincd.s

 uqincd  x0, all, mul #16
 // CHECK-INST: uqincd  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf7,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 f7 ff 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqincd  w0
+// CHECK-INST: uqincd  w0
+// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 e0 04 <unknown>
+
+uqincd  w0, all
+// CHECK-INST: uqincd  w0
+// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 e0 04 <unknown>
+
+uqincd  w0, all, mul #1
+// CHECK-INST: uqincd  w0
+// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 e0 04 <unknown>
+
+uqincd  w0, all, mul #16
+// CHECK-INST: uqincd  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf7,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 ef 04 <unknown>
+
+uqincd  w0, pow2
+// CHECK-INST: uqincd  w0, pow2
+// CHECK-ENCODING: [0x00,0xf4,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 e0 04 <unknown>
+
+uqincd  w0, pow2, mul #16
+// CHECK-INST: uqincd  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf4,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 ef 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 uqincd  x0, pow2
 // CHECK-INST: uqincd  x0, pow2
 // CHECK-ENCODING: [0x00,0xf4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 f4 f0 04 <unknown>

test/MC/AArch64/SVE/uqinch-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqinch w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqinch w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqinch wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqinch wsp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqinch sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqinch sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned inc only has one register operand)
+
+uqinch x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqinch x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqinch w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqinch w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqinch x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqinch x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqinch x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: uqinch x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqinch x0, all, mul #0

test/MC/AArch64/SVE/uqinch.s

 uqinch  x0, all, mul #16
 // CHECK-INST: uqinch  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf7,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 f7 7f 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqinch  w0
+// CHECK-INST: uqinch  w0
+// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 60 04 <unknown>
+
+uqinch  w0, all
+// CHECK-INST: uqinch  w0
+// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 60 04 <unknown>
+
+uqinch  w0, all, mul #1
+// CHECK-INST: uqinch  w0
+// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 60 04 <unknown>
+
+uqinch  w0, all, mul #16
+// CHECK-INST: uqinch  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf7,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 6f 04 <unknown>
+
+uqinch  w0, pow2
+// CHECK-INST: uqinch  w0, pow2
+// CHECK-ENCODING: [0x00,0xf4,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 60 04 <unknown>
+
+uqinch  w0, pow2, mul #16
+// CHECK-INST: uqinch  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf4,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 6f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 uqinch  x0, pow2
 // CHECK-INST: uqinch  x0, pow2
 // CHECK-ENCODING: [0x00,0xf4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 f4 70 04 <unknown>

test/MC/AArch64/SVE/uqincw-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqincw w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqincw w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqincw wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqincw wsp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqincw sp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqincw sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned inc only has one register operand)
+
+uqincw x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincw x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincw w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincw w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincw x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincw x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqincw x0, all, mul #-1
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
 // CHECK-NEXT: uqincw x0, all, mul #-1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 uqincw x0, all, mul #0

test/MC/AArch64/SVE/uqincw.s

 uqincw  x0, all, mul #16
 // CHECK-INST: uqincw  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf7,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 f7 bf 04 <unknown>
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqincw  w0
+// CHECK-INST: uqincw  w0
+// CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 a0 04 <unknown>
+
+uqincw  w0, all
+// CHECK-INST: uqincw  w0
+// CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 a0 04 <unknown>
+
+uqincw  w0, all, mul #1
+// CHECK-INST: uqincw  w0
+// CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 a0 04 <unknown>
+
+uqincw  w0, all, mul #16
+// CHECK-INST: uqincw  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf7,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 af 04 <unknown>
+
+uqincw  w0, pow2
+// CHECK-INST: uqincw  w0, pow2
+// CHECK-ENCODING: [0x00,0xf4,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 a0 04 <unknown>
+
+uqincw  w0, pow2, mul #16
+// CHECK-INST: uqincw  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf4,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 af 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
 uqincw  x0, pow2
 // CHECK-INST: uqincw  x0, pow2
 // CHECK-ENCODING: [0x00,0xf4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 f4 b0 04 <unknown>