DAG: Avoid bitcast/ext/build_vector combine

[arsenm]

Summary

This avoids regressions in a future AMDGPU change
to make v4i16/v4f16 legal. For these types, build_vector
is implemented as bitcasted operations on v2i32. This
combine was creating v4i16s out of what would have been
already been a v2i32 build_vector, creating a mess
of nodes that never get cleaned up.

I'm not sure this is the right condition to check.
I initially tried just checking for the legality of the
new build_vector. This works for my case, but breaks dozens
of x86 tests. A Mips test seems to show some improvement
or at least a neutral change. I don't want to think
about how long it would take to analyze the set of
different x86 vector operations impacted.

Test included in future commit.

[hliao]

please add regression tests

[arsenm]

In D47207#1108244, @hliao wrote:

please add regression tests

As noted in the message this can't be tested until a later commit

[RKSimon]

In D47207#1108259, @arsenm wrote:

In D47207#1108244, @hliao wrote:

please add regression tests

As noted in the message this can't be tested until a later commit

Instead is it possible to add the dependent phab for v4i16/v4f16 legal types?

[arsenm]

In D47207#1114198, @RKSimon wrote:

In D47207#1108259, @arsenm wrote:

In D47207#1108244, @hliao wrote:

please add regression tests

As noted in the message this can't be tested until a later commit

Instead is it possible to add the dependent phab for v4i16/v4f16 legal types?

Done now

[arsenm]

r334218

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
     Ops[Index] = In;
   }
 
   // The type of the new BUILD_VECTOR node.
   EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
   assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
          "Invalid vector size");
   // Check if the new vector type is legal.
-  if (!isTypeLegal(VecVT)) return SDValue();
+  if (!isTypeLegal(VecVT) ||
+      (!TLI.isOperationLegal(ISD::BUILD_VECTOR, VecVT) &&
+       TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)))
+    return SDValue();
 
   // Make the new BUILD_VECTOR.
   SDValue BV = DAG.getBuildVector(VecVT, DL, Ops);
 
   // The new BUILD_VECTOR node has the potential to be further optimized.
   AddToWorklist(BV.getNode());
   // Bitcast to the desired type.
   return DAG.getBitcast(VT, BV);