DAG: Fix extract_subvector combine for a single element

[arsenm]

Summary

This would fail before because 1x vectors aren't legal,
so instead just use the scalar type.

Avoids regressions in a future AMDGPU commit to add
v4i16/v4f16 as legal types.

Test update is just the one test that this triggers
on in tree now. It wasn't checking anything before.
The result is completely changed since the selects
are eliminated. Not sure if it's considered better
or not.

[arsenm]

Fix missing test update

[craig.topper]

Can you clarify what "fails" means in your description? It would have create a <1 x iX> or <1 x fX> BUILD_VECTOR but it could only do that before type legalization if that type isn't legal. Type legalization should then scalarize that since its an illegal type.

[arsenm]

In D47215#1123942, @craig.topper wrote:

Can you clarify what "fails" means in your description? It would have create a <1 x iX> or <1 x fX> BUILD_VECTOR but it could only do that before type legalization if that type isn't legal. Type legalization should then scalarize that since its an illegal type.

I mean the optimization doesn't happen, because the the "isOperationLegal(ISD::BUILD_VECTOR, MVT::v1X)" check fails after legalization.

[craig.topper]

Is v1X a legal type, but not a legal build_vector? i.e. how do you pass the isTypeLegal check?

[arsenm]

In D47215#1123993, @craig.topper wrote:

Is v1X a legal type, but not a legal build_vector? i.e. how do you pass the isTypeLegal check?

No, v1 is illegal (as it should be on every target, although I know ARM at least has some legal v1 types as a hack). That was also failing, but now it's checking the legality of the scalar type

[craig.topper]

LGTM

[craig.topper]

Can this break if the build vector operand type is larger than the build vector element type? As happens when the element type isn’t a legal scalar type.

[arsenm]

In D47215#1126880, @craig.topper wrote:

Can this break if the build vector operand type is larger than the build vector element type? As happens when the element type isn’t a legal scalar type.

There probably needs to be a truncate, but I don't know how to construct a test that would need this

[arsenm]

r334440. I added the truncate, but it's untested.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
   if (V->getOpcode() == ISD::BUILD_VECTOR) {
     if (auto *Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
       EVT InVT = V->getValueType(0);
       unsigned ExtractSize = NVT.getSizeInBits();
       unsigned EltSize = InVT.getScalarSizeInBits();
       // Only do this if we won't split any elements.
       if (ExtractSize % EltSize == 0) {
         unsigned NumElems = ExtractSize / EltSize;
-        EVT ExtractVT = EVT::getVectorVT(*DAG.getContext(),
-                                         InVT.getVectorElementType(), NumElems);
+        EVT EltVT = InVT.getVectorElementType();
+        EVT ExtractVT = NumElems == 1 ? EltVT :
+          EVT::getVectorVT(*DAG.getContext(), EltVT, NumElems);
         if ((Level < AfterLegalizeDAG ||
-             TLI.isOperationLegal(ISD::BUILD_VECTOR, ExtractVT)) &&
+             (NumElems == 1 ||
+              TLI.isOperationLegal(ISD::BUILD_VECTOR, ExtractVT))) &&
             (!LegalTypes || TLI.isTypeLegal(ExtractVT))) {
           unsigned IdxVal = (Idx->getZExtValue() * NVT.getScalarSizeInBits()) /
                             EltSize;
+          if (NumElems == 1)
+            return DAG.getBitcast(NVT, V->getOperand(IdxVal));
 
           // Extract the pieces from the original build_vector.
           SDValue BuildVec = DAG.getBuildVector(ExtractVT, SDLoc(N),
                                             makeArrayRef(V->op_begin() + IdxVal,
                                                          NumElems));
           return DAG.getBitcast(NVT, BuildVec);
         }
       }

test/CodeGen/ARM/2013-05-13-DAGCombiner-undef-mask.ll

-; RUN: llc < %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
 target triple = "armv7-none-linux-gnueabi"
 
+; CHECK-LABEL: {{^}}shuffle:
 define <3 x i64> @shuffle(i1 %dec1, i1 %dec0, <3 x i64> %b) {
+; CHECK-LABEL: shuffle:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    tst r1, #1
+; CHECK-NEXT:    moveq r1, #0
+; CHECK-NEXT:    vmoveq d16, r1, r1
+; CHECK-NEXT:    vldrne d16, [sp]
+; CHECK-NEXT:    tst r2, #1
+; CHECK-NEXT:    moveq r1, #0
+; CHECK-NEXT:    vmoveq d18, r1, r1
+; CHECK-NEXT:    vldrne d18, [sp, #8]
+; CHECK-NEXT:    vorr d17, d18, d18
+; CHECK-NEXT:    vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT:    bx lr
 entry:
   %.sink = select i1 %dec1, <3 x i64> %b, <3 x i64> zeroinitializer
   %.sink15 = select i1 %dec0, <3 x i64> %b, <3 x i64> zeroinitializer
   %vecinit7 = shufflevector <3 x i64> %.sink, <3 x i64> %.sink15, <3 x i32> <i32 0, i32 4, i32 undef>
   ret <3 x i64> %vecinit7
 }