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[AArch64] Improve single vector lane unscaled stores
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Authored by evandro on May 11 2018, 10:58 AM.

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Summary

When storing the 0th lane of a vector, use a simpler and usually more efficient scalar store instead. In this case, also using the unscaled offset.

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rL LLVM

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evandro created this revision.May 11 2018, 10:58 AM
efriedma accepted this revision.May 15 2018, 12:51 PM
efriedma added a subscriber: efriedma.

LGTM with a minor comment on the test changes.

llvm/test/CodeGen/AArch64/arm64-st1.ll
72

Using patterns rather than the actual instruction doesn't seem helpful here: you know exactly which registers the two inputs will be in, and the exact offset, so the output should be stable. (Patterns are more useful when the registers aren't predictable, like temporary values.)

This revision is now accepted and ready to land.May 15 2018, 12:51 PM
evandro marked an inline comment as done.May 15 2018, 1:27 PM
This revision was automatically updated to reflect the committed changes.