[AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.

[sdesmalen]

Summary

For regular SVE vector operands, this patch introduces a more
sensible diagnostic when the vector has a wrong suffix (e.g. z0.s vs z0.b).

For example:

add z0.s, z1.s, z2.b      -> invalid element width
             ^_____^
             mismatch

For the vector-with-shift/extend (e.g. z0.s, uxtw #2) this patch takes
a slightly different approach and instead returns a 'invalid operand'
if the element size is not as expected. This is because the diagnostics
are more specificied to suggest using the right shift/extend suffix. This
is a trade-off not to introduce more operand classes and still provide
useful diagnostics for LD1 and PRF instructions.

For example:

ld1w z1.s, p0/z, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
ld1w z1.d, p0/z, [x0, z0.s] -> invalid operand
        ^________________^
             mismatch

For gather prefetches, both 'z0.s' and 'z0.d' would be allowed:

prfw #0, p0, [x0, z0.s]   -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
prfw #0, p0, [x0, z0.d]   -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'

Without this change, the diagnostic would unnecessarily suggest a
different element size:

prfw #0, p0, [x0, z0.s]   -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'

[SjoerdMeijer]

test/MC/AArch64/SVE/ld1b-diagnostics.s

118 ↗

(On Diff #146107)

Is this a regression? Is the old diagnostic more accurate? If so, can we avoid this regression? There is quite a few of them below.

[sdesmalen]

test/MC/AArch64/SVE/ld1b-diagnostics.s

118 ↗

(On Diff #146107)

It is, but a conscious one. I tried to explain it a bit in the description of the patch, but I can understand this may not have been very clear :)
This regression is a trade-off to get better diagnostics for the prefetches. We could avoid the regression if we create new operand classes for each shift/extend where it makes the distinction between "both z0.s and z0.d are allowed in this position", and "only z0.d is allowed". That way, the assembler can make the choice what diagnostic to emit. However, I think that would (over)complicate the operand classes.
Please have a second look at the commit message to see some examples of this trade-off and let me know what you think is the best way forward.

[SjoerdMeijer]

test/MC/AArch64/SVE/ld1b-diagnostics.s

118 ↗

(On Diff #146107)

Ah, sorry, I guess I didn't read the description carefully enough!

I didn't count the number of regressions, but this change looks neutral: there are as many regressions in the diagnostics as there are improvements. Perhaps there are slightly more improvements.

The royal approach of course would be to have the best of both worlds (i.e. no regressions), but you write that would require more operands classes. I don't know if that would make things messy or not, but given that the change is neutral, I can live with this change. Perhaps you can wait a day before committing just in case someone can't.

llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td

class PPRClass<int lastreg> : RegisterClass<
   let Size = 16;
 }
 
 def PPR    : PPRClass<15>;
 def PPR_3b : PPRClass<7>; // Restricted 3 bit SVE predicate register class.
 
 class PPRAsmOperand <string name, string RegClass, int Width>: AsmOperandClass {
   let Name = "SVE" # name # "Reg";
-  let PredicateMethod = "isSVEVectorRegOfWidth<"
+  let PredicateMethod = "isSVEPredicateVectorRegOfWidth<"
                             # Width # ", " # "AArch64::" # RegClass # "RegClassID>";
   let DiagnosticType = "InvalidSVE" # name # "Reg";
   let RenderMethod = "addRegOperands";
   let ParserMethod = "tryParseSVEPredicateVector";
 }
 
 def PPRAsmOpAny : PPRAsmOperand<"PredicateAny", "PPR",  0>;
 def PPRAsmOp8   : PPRAsmOperand<"PredicateB",   "PPR",  8>;
def ZPR : RegisterClass<"AArch64",
                          nxv1f32, nxv2f32, nxv4f32,
                          nxv1f64, nxv2f64],
                         128, (sequence "Z%u", 0, 31)> {
   let Size = 128;
 }
 
 class ZPRAsmOperand <string name, int Width>: AsmOperandClass {
   let Name = "SVE" # name # "Reg";
-  let PredicateMethod = "isSVEVectorRegOfWidth<"
+  let PredicateMethod = "isSVEDataVectorRegOfWidth<"
                             # Width # ", AArch64::ZPRRegClassID>";
   let RenderMethod = "addRegOperands";
+  let DiagnosticType = "InvalidZPR" # Width;
   let ParserMethod = "tryParseSVEDataVector<false, "
                                # !if(!eq(Width, 0), "false", "true") # ">";
 }
 
 def ZPRAsmOpAny : ZPRAsmOperand<"VectorAny", 0>;
 def ZPRAsmOp8   : ZPRAsmOperand<"VectorB",   8>;
 def ZPRAsmOp16  : ZPRAsmOperand<"VectorH",   16>;
 def ZPRAsmOp32  : ZPRAsmOperand<"VectorS",   32>;
def ZZZZ_d : RegisterOperand<ZPR4, "printTypedVectorList<0,'d'>"> {
   let ParserMatchClass = ZPRVectorList<64, 4>;
 }
 
 class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale,
                           bit ScaleAlwaysSame = 0b0> : AsmOperandClass {
   let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale
                          # !if(ScaleAlwaysSame, "Only", "");
 
-  let PredicateMethod = "isSVEVectorRegWithShiftExtend<"
+  let PredicateMethod = "isSVEDataVectorRegWithShiftExtend<"
                           # RegWidth # ", AArch64::ZPRRegClassID, "
                           # "AArch64_AM::" # ShiftExtend # ", "
                           # Scale # ", "
                           # !if(ScaleAlwaysSame, "true", "false")
                           # ">";
   let DiagnosticType = "InvalidZPR" # RegWidth # ShiftExtend # Scale;
   let RenderMethod = "addRegOperands";
   let ParserMethod = "tryParseSVEDataVector<true, true>";

llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

default:
       llvm_unreachable("Unsupport register class");
     }
 
     return (Kind == k_Register && Reg.Kind == RK) &&
            AArch64MCRegisterClasses[Class].contains(getReg());
   }
 
   template <int ElementWidth, unsigned Class>
-  bool isSVEVectorRegOfWidth() const {
-    return isSVEVectorReg<Class>() &&
-           (ElementWidth == 0 || Reg.ElementWidth == ElementWidth);
+  DiagnosticPredicate isSVEPredicateVectorRegOfWidth() const {
+    if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateVector)
+      return DiagnosticPredicateTy::NoMatch;
+
+    if (isSVEVectorReg<Class>() &&
+           (ElementWidth == 0 || Reg.ElementWidth == ElementWidth))
+      return DiagnosticPredicateTy::Match;
+
+    return DiagnosticPredicateTy::NearMatch;
   }
 
-  template <int ElementWidth, unsigned Class,
-            AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth,
-            bool ShiftWidthAlwaysSame>
-  DiagnosticPredicate isSVEVectorRegWithShiftExtend() const {
+  template <int ElementWidth, unsigned Class>
+  DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
     if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
       return DiagnosticPredicateTy::NoMatch;
 
-    if (!isSVEVectorRegOfWidth<ElementWidth, Class>())
-      return DiagnosticPredicateTy::NearMatch;
+    if (isSVEVectorReg<Class>() &&
+           (ElementWidth == 0 || Reg.ElementWidth == ElementWidth))
+      return DiagnosticPredicateTy::Match;
+
+  }
+
+  template <int ElementWidth, unsigned Class,
+            AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth,
+            bool ShiftWidthAlwaysSame>
+  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
+    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
+    if (!VectorMatch.isMatch())
+      return DiagnosticPredicateTy::NoMatch;
 
     // Give a more specific diagnostic when the user has explicitly typed in
     // a shift-amount that does not match what is expected, but for which
     // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
     bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
     if (!MatchShift && (ShiftExtendTy == AArch64_AM::UXTW ||
                         ShiftExtendTy == AArch64_AM::SXTW) &&
         !ShiftWidthAlwaysSame && hasShiftExtendAmount() && ShiftWidth == 8)
bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
   case Match_InvalidZPR64LSL8:
     return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d'");
   case Match_InvalidZPR64LSL16:
     return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, lsl #1'");
   case Match_InvalidZPR64LSL32:
     return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, lsl #2'");
   case Match_InvalidZPR64LSL64:
     return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, lsl #3'");
+  case Match_InvalidZPR0:
+    return Error(Loc, "expected register without element width sufix");
+  case Match_InvalidZPR8:
+  case Match_InvalidZPR16:
+  case Match_InvalidZPR32:
+  case Match_InvalidZPR64:
+  case Match_InvalidZPR128:
+    return Error(Loc, "invalid element width");
   case Match_InvalidSVEPattern:
     return Error(Loc, "invalid predicate pattern");
   case Match_InvalidSVEPredicateAnyReg:
   case Match_InvalidSVEPredicateBReg:
   case Match_InvalidSVEPredicateHReg:
   case Match_InvalidSVEPredicateSReg:
   case Match_InvalidSVEPredicateDReg:
     return Error(Loc, "invalid predicate register.");
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidZPR64UXTW32:
   case Match_InvalidZPR64SXTW32:
   case Match_InvalidZPR64UXTW64:
   case Match_InvalidZPR64SXTW64:
   case Match_InvalidZPR64LSL8:
   case Match_InvalidZPR64LSL16:
   case Match_InvalidZPR64LSL32:
   case Match_InvalidZPR64LSL64:
+  case Match_InvalidZPR0:
+  case Match_InvalidZPR8:
+  case Match_InvalidZPR16:
+  case Match_InvalidZPR32:
+  case Match_InvalidZPR64:
+  case Match_InvalidZPR128:
   case Match_InvalidSVEPredicateAnyReg:
   case Match_InvalidSVEPattern:
   case Match_InvalidSVEPredicateBReg:
   case Match_InvalidSVEPredicateHReg:
   case Match_InvalidSVEPredicateSReg:
   case Match_InvalidSVEPredicateDReg:
   case Match_InvalidSVEPredicate3bAnyReg:
   case Match_InvalidSVEPredicate3bBReg:

llvm/trunk/test/MC/AArch64/SVE/add-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // Register z32 does not exist.
 add z22.h, z10.h, z32.h
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: add z22.h, z10.h, z32.h
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // Invalid element kind.
 add z20.h, z2.h, z31.x
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
 // CHECK-NEXT: add z20.h, z2.h, z31.x
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // Element size specifiers should match.
 add z27.h, z11.h, z27.b
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: add z27.h, z11.h, z27.b
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // Invalid predicate suffix '/a'
 add z29.d, p7/a, z29.d, z8.d
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expecting 'm' or 'z' predication
 // CHECK-NEXT: add z29.d, p7/a, z29.d, z8.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s

 // CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 ld1b z0.d, p0/z, [x0, z0.b]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.b]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1b z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s

 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 ld1d z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, z0.d, uxtw #2]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, uxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, z0.d, lsl #2]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid vector + immediate addressing modes
 
 ld1d z0.s, p0/z, [z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1d z0.s, p0/z, [z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.s, p0/z, [z0.s, #8]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1d z0.s, p0/z, [z0.s, #8]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [z0.d, #-8]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
 // CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #-8]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s

 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 ld1h z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/ld1rd-diagnostics.s

 // CHECK-NEXT: ld1rd z0.d, p1/z, [x0, #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid result vector element size
 
 ld1rd z0.b, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rd z0.b, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rd z0.h, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rd z0.h, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rd z0.s, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rd z0.s, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ld1rd z0.d, p8/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
 // CHECK-NEXT: ld1rd z0.d, p8/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/ld1rh-diagnostics.s

 // CHECK-NEXT: ld1rh z0.h, p1/z, [x0, #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid result vector element size
 
 ld1rh z0.b, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rh z0.b, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ld1rh z0.h, p8/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
 // CHECK-NEXT: ld1rh z0.h, p8/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/ld1rqb-diagnostics.s

 // CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, #16, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid destination register width.
 
 ld1rqb z0.h, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqb z0.h, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqb z0.s, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqb z0.s, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqb z0.d, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqb z0.d, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + scalar addressing modes
 
 ld1rqb z0.b, p0/z, [x0, xzr]

llvm/trunk/test/MC/AArch64/SVE/ld1rqd-diagnostics.s

 // CHECK-NEXT: ld1rqd z0.d, p0/z, [x0, #16, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid destination register width.
 
 ld1rqd z0.b, p0/z, [x0, x1, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqd z0.b, p0/z, [x0, x1, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqd z0.h, p0/z, [x0, x1, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqd z0.h, p0/z, [x0, x1, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqd z0.s, p0/z, [x0, x1, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqd z0.s, p0/z, [x0, x1, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + scalar addressing modes
 
 ld1rqd z0.d, p0/z, [x0, xzr, lsl #3]

llvm/trunk/test/MC/AArch64/SVE/ld1rqh-diagnostics.s

 // CHECK-NEXT: ld1rqh z0.h, p0/z, [x0, #16, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid destination register width.
 
 ld1rqh z0.b, p0/z, [x0, x1, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqh z0.b, p0/z, [x0, x1, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqh z0.s, p0/z, [x0, x1, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqh z0.s, p0/z, [x0, x1, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqh z0.d, p0/z, [x0, x1, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqh z0.d, p0/z, [x0, x1, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + scalar addressing modes
 
 ld1rqh z0.h, p0/z, [x0, xzr, lsl #1]

llvm/trunk/test/MC/AArch64/SVE/ld1rqw-diagnostics.s

 // CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, #16, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid destination register width.
 
 ld1rqw z0.b, p0/z, [x0, x1, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqw z0.b, p0/z, [x0, x1, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqw z0.h, p0/z, [x0, x1, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqw z0.h, p0/z, [x0, x1, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqw z0.d, p0/z, [x0, x1, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqw z0.d, p0/z, [x0, x1, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + scalar addressing modes
 
 ld1rqw z0.s, p0/z, [x0, xzr, lsl #2]

llvm/trunk/test/MC/AArch64/SVE/ld1rsb-diagnostics.s

 // CHECK-NEXT: ld1rsb z0.h, p1/z, [x0, #64]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid result vector element size
 
 ld1rsb z0.b, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rsb z0.b, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ld1rsb z0.h, p8/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
 // CHECK-NEXT: ld1rsb z0.h, p8/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/ld1rsh-diagnostics.s

 // CHECK-NEXT: ld1rsh z0.s, p1/z, [x0, #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid result vector element size
 
 ld1rsh z0.b, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rsh z0.b, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rsh z0.h, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rsh z0.h, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ld1rsh z0.s, p8/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
 // CHECK-NEXT: ld1rsh z0.s, p8/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/ld1rsw-diagnostics.s

 // CHECK-NEXT: ld1rsw z0.d, p1/z, [x0, #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid result vector element size
 
 ld1rsw z0.b, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rsw z0.b, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rsw z0.h, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rsw z0.h, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rsw z0.s, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rsw z0.s, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ld1rsw z0.d, p8/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
 // CHECK-NEXT: ld1rsw z0.d, p8/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/ld1rw-diagnostics.s

 // CHECK-NEXT: ld1rw z0.s, p1/z, [x0, #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid result vector element size
 
 ld1rw z0.b, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rw z0.b, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rw z0.h, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rw z0.h, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ld1rw z0.s, p8/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
 // CHECK-NEXT: ld1rw z0.s, p8/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // --------------------------------------------------------------------------//
 // Invalid operand (.b)
 
 ld1sb z23.b, p0/z, [x13, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sb z23.b, p0/z, [x13, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z29.b, p0/z, [x3, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sb z29.b, p0/z, [x3, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Immediate out of lower bound [-8, 7].
 
 ld1sb z21.h, p4/z, [x17, #-9, MUL VL]

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 ld1sb z0.d, p0/z, [x0, z0.b]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.b]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sb z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // --------------------------------------------------------------------------//
 // Invalid operand (.h)
 
 ld1sh z23.h, p0/z, [x13, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sh z23.h, p0/z, [x13, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z29.h, p0/z, [x3, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sh z29.h, p0/z, [x3, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Immediate out of lower bound [-8, 7].
 
 ld1sh z30.s, p6/z, [x25, #-9, MUL VL]

 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 ld1sh z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // --------------------------------------------------------------------------//
 // Invalid operand (.s)
 
 ld1sw z23.s, p0/z, [x13, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sw z23.s, p0/z, [x13, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z29.s, p0/z, [x3, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sw z29.s, p0/z, [x3, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Immediate out of lower bound [-8, 7].
 
 ld1sw z28.d, p2/z, [x28, #-9, MUL VL]

 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 ld1sw z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
-// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.s]
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-ld1sw z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid vector + immediate addressing modes
 
 ld1sw z0.s, p0/z, [z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sw z0.s, p0/z, [z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.s, p0/z, [z0.s, #4]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sw z0.s, p0/z, [z0.s, #4]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [z0.d, #-4]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
 // CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #-4]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s

 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 ld1w z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/ldff1b-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
 // CHECK-NEXT: ldff1b z0.b, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 ldff1b z0.d, p0/z, [x0, z0.b]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.b]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1b z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1b z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1b z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1b z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // --------------------------------------------------------------------------//
 // Invalid operand (.b, .h, .s)
 
 ldff1d z4.b, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1d z4.b, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z4.h, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1d z4.h, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z4.s, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1d z4.s, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ldff1d z4.d, p8/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].

 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 ldff1d z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z0.d, p0/z, [x0, z0.d, uxtw #2]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.d, uxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z0.d, p0/z, [x0, z0.d, lsl #2]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.d, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid vector + immediate addressing modes
 
 ldff1d z0.s, p0/z, [z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1d z0.s, p0/z, [z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z0.s, p0/z, [z0.s, #8]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1d z0.s, p0/z, [z0.s, #8]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z0.d, p0/z, [z0.d, #-8]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
 // CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #-8]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/ldff1h-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // --------------------------------------------------------------------------//
 // Invalid operand (.b)
 
 ldff1h z9.b, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1h z9.b, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ldff1h z9.h, p8/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].

 // CHECK-NEXT: ldff1h z0.h, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 ldff1h z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1h z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1h z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1h z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1h z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1h z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/ldff1sb-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // --------------------------------------------------------------------------//
 // Invalid operand (.b)
 
 ldff1sb z27.b, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1sb z27.b, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ldff1sb z9.h, p8/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
 // CHECK-NEXT: ldff1sb z0.h, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 ldff1sb z0.d, p0/z, [x0, z0.b]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1sb z0.d, p0/z, [x0, z0.b]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sb z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1sb z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sb z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1sb z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sb z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1sb z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // --------------------------------------------------------------------------//
 // Invalid operand (.h)
 
 ldff1sh z9.h, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1sh z9.h, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ldff1sh z12.s, p8/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
 // CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 ldff1sh z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1sh z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sh z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1sh z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sh z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // --------------------------------------------------------------------------//
 // Invalid operand (.s)
 
 ldff1sw z12.s, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1sw z12.s, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ldff1sw z4.d, p8/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].

 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 ldff1sw z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sw z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
-// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.s]
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-ldff1sw z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sw z0.d, p0/z, [x0, z0.d, uxtw #3]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.d, uxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid vector + immediate addressing modes
 
 ldff1sw z0.s, p0/z, [z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1sw z0.s, p0/z, [z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sw z0.s, p0/z, [z0.s, #4]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1sw z0.s, p0/z, [z0.s, #4]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sw z0.d, p0/z, [z0.d, #-4]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #-4]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // --------------------------------------------------------------------------//
 // Invalid operand (.b, .h)
 
 ldff1w z12.b, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1w z12.b, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1w z4.h, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1w z4.h, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ldff1w z12.s, p8/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].

 // CHECK-NEXT: ldff1w z0.s, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 ldff1w z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1w z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1w z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1w z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1w z0.s, p0/z, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1w z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // --------------------------------------------------------------------------//
 // Invalid operand (.b)
 
 ldnf1sb z23.b, p0/z, [x13, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnf1sb z23.b, p0/z, [x13, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnf1sb z29.b, p0/z, [x3, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnf1sb z29.b, p0/z, [x3, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Immediate out of lower bound [-8, 7].
 
 ldnf1sb z21.h, p4/z, [x17, #-9, MUL VL]

llvm/trunk/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // --------------------------------------------------------------------------//
 // Invalid operand (.h)
 
 ldnf1sh z23.h, p0/z, [x13, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnf1sh z23.h, p0/z, [x13, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnf1sh z29.h, p0/z, [x3, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnf1sh z29.h, p0/z, [x3, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Immediate out of lower bound [-8, 7].
 
 ldnf1sh z30.s, p6/z, [x25, #-9, MUL VL]

llvm/trunk/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // --------------------------------------------------------------------------//
 // Invalid operand (.s)
 
 ldnf1sw z23.s, p0/z, [x13, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnf1sw z23.s, p0/z, [x13, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnf1sw z29.s, p0/z, [x3, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnf1sw z29.s, p0/z, [x3, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Immediate out of lower bound [-8, 7].
 
 ldnf1sw z28.d, p2/z, [x28, #-9, MUL VL]

llvm/trunk/test/MC/AArch64/SVE/ldnt1b-diagnostics.s

 // CHECK-NEXT: ldnt1b z29.b, p0/z, [x3, #8, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid result type.
 
 ldnt1b z0.h, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1b z0.h, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1b z0.s, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1b z0.s, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1b z0.d, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1b z0.d, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ldnt1b z27.b, p8/z, [x0]

llvm/trunk/test/MC/AArch64/SVE/ldnt1d-diagnostics.s

 // CHECK-NEXT: ldnt1d z29.d, p0/z, [x3, #8, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid result type.
 
 ldnt1d z0.b, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1d z0.b, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1d z0.h, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1d z0.h, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1d z0.s, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1d z0.s, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ldnt1d z27.d, p8/z, [x0]

llvm/trunk/test/MC/AArch64/SVE/ldnt1h-diagnostics.s

 // CHECK-NEXT: ldnt1h z29.h, p0/z, [x3, #8, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid result type.
 
 ldnt1h z0.b, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1h z0.b, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1h z0.s, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1h z0.s, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1h z0.d, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1h z0.d, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ldnt1h z27.h, p8/z, [x0]

llvm/trunk/test/MC/AArch64/SVE/ldnt1w-diagnostics.s

 // CHECK-NEXT: ldnt1w z29.s, p0/z, [x3, #8, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid result type.
 
 ldnt1w z0.b, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1w z0.b, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1w z0.h, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1w z0.h, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1w z0.d, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1w z0.d, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // restricted predicate has range [0, 7].
 
 ldnt1w z27.s, p8/z, [x0]

llvm/trunk/test/MC/AArch64/SVE/prfb-diagnostics.s

 // CHECK-NEXT: prfb #0, p0, [x0, x0, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 prfb #0, p0, [x0, z0.b]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: prfb #0, p0, [x0, z0.b]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfb #0, p0, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: prfb #0, p0, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfb #0, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: prfb #0, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfb #0, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: prfb #0, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfb #0, p0, [x0, z0.s, uxtw #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: prfb #0, p0, [x0, z0.s, uxtw #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfb #0, p0, [x0, z0.s, lsl #0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: prfb #0, p0, [x0, z0.s, lsl #0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfb #0, p0, [x0, z0.d, lsl #1]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: prfb #0, p0, [x0, z0.d, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/prfd-diagnostics.s

 // CHECK-NEXT: prfd #0, p0, [x0, x0, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 prfd #0, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #3'
 // CHECK-NEXT: prfd #0, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfd #0, p0, [x0, z0.d, uxtw #2]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
 // CHECK-NEXT: prfd #0, p0, [x0, z0.d, uxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/prfh-diagnostics.s

 // CHECK-NEXT: prfh #0, p0, [x0, x0, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 prfh #0, p0, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: prfh #0, p0, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfh #0, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: prfh #0, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfh #0, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: prfh #0, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfh #0, p0, [x0, z0.s, uxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: prfh #0, p0, [x0, z0.s, uxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfh #0, p0, [x0, z0.s, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: prfh #0, p0, [x0, z0.s, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfh #0, p0, [x0, z0.d, lsl #2]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
 // CHECK-NEXT: prfh #0, p0, [x0, z0.d, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/prfw-diagnostics.s

 // CHECK-NEXT: prfw #0, p0, [x0, x0, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 prfw #0, p0, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: prfw #0, p0, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfw #0, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
 // CHECK-NEXT: prfw #0, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfw #0, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
 // CHECK-NEXT: prfw #0, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfw #0, p0, [x0, z0.s, uxtw #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
 // CHECK-NEXT: prfw #0, p0, [x0, z0.s, uxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfw #0, p0, [x0, z0.s, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
 // CHECK-NEXT: prfw #0, p0, [x0, z0.s, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfw #0, p0, [x0, z0.d, lsl #3]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 // CHECK-NEXT: prfw #0, p0, [x0, z0.d, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s

 // CHECK-NEXT: st1b z0.b, p0, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 st1b z0.d, p0, [x0, z0.b]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1b z0.d, p0, [x0, z0.b]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1b z0.d, p0, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1b z0.d, p0, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1b z0.d, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1b z0.d, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1b z0.s, p0, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: st1b z0.s, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s

 // CHECK-NEXT: st1d z0.d, p0, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 st1d z0.d, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1d z0.d, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1d z0.d, p0, [x0, z0.d, uxtw #2]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
 // CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, uxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1d z0.d, p0, [x0, z0.d, lsl #2]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
 // CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1d z0.d, p0, [x0, z0.d, lsl]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
 // CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, lsl]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid vector + immediate addressing modes
 
 st1d z0.s, p0, [z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: st1d z0.s, p0, [z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1d z0.s, p0, [z0.s, #8]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: st1d z0.s, p0, [z0.s, #8]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1d z0.d, p0, [z0.d, #-1]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
 // CHECK-NEXT: st1d z0.d, p0, [z0.d, #-1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s

 // CHECK-NEXT: st1h z0.h, p0, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 st1h z0.d, p0, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1h z0.d, p0, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1h z0.d, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1h z0.d, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1h z0.s, p0, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: st1h z0.s, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s

 // CHECK-NEXT: st1w z0.s, p0, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + vector addressing modes
 
 st1w z0.d, p0, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1w z0.d, p0, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1w z0.d, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1w z0.d, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1w z0.s, p0, [x0, z0.s]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: st1w z0.s, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/trunk/test/MC/AArch64/SVE/stnt1b-diagnostics.s

 // CHECK-NEXT: stnt1b z29.b, p0, [x3, #8, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid source type.
 
 stnt1b z0.h, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1b z0.h, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1b z0.s, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1b z0.s, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1b z0.d, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1b z0.d, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // invalid predicate
 
 stnt1b z27.b, p8, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
 // CHECK-NEXT: stnt1b z27.b, p8, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1b z0.h, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1b z0.h, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid vector list.
 
 stnt1b { }, p0, [x1, #1, MUL VL]

llvm/trunk/test/MC/AArch64/SVE/stnt1d-diagnostics.s

 // CHECK-NEXT: stnt1d z29.d, p0, [x3, #8, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid source type.
 
 stnt1d z0.b, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1d z0.b, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1d z0.h, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1d z0.h, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1d z0.s, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1d z0.s, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // invalid predicate
 
 stnt1d z27.d, p8, [x0]

llvm/trunk/test/MC/AArch64/SVE/stnt1h-diagnostics.s

 // CHECK-NEXT: stnt1h z29.h, p0, [x3, #8, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid source type.
 
 stnt1h z0.b, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1h z0.b, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1h z0.s, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1h z0.s, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1h z0.d, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1h z0.d, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // invalid predicate
 
 stnt1h z27.h, p8, [x0]

llvm/trunk/test/MC/AArch64/SVE/stnt1w-diagnostics.s

 // CHECK-NEXT: stnt1w z29.s, p0, [x3, #8, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid source type.
 
 stnt1w z0.b, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1w z0.b, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1w z0.h, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1w z0.h, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1w z0.d, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1w z0.d, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // invalid predicate
 
 stnt1w z27.s, p8, [x0]

llvm/trunk/test/MC/AArch64/SVE/sub-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // Register z32 does not exist.
 sub z3.h, z26.h, z32.h
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: sub z3.h, z26.h, z32.h
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // Invalid element kind.
 sub z4.h, z27.h, z31.x
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
 // CHECK-NEXT: sub z4.h, z27.h, z31.x
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // Element size specifiers should match.
 sub z0.h, z8.h, z8.b
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: sub z0.h, z8.h, z8.b
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // Invalid predicate suffix '/a'
 sub z29.d, p7/a, z29.d, z8.d
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expecting 'm' or 'z' predication
 // CHECK-NEXT: sub z29.d, p7/a, z29.d, z8.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/zip1-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // Invalid element kind.
 zip1 z10.h, z22.h, z31.x
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
 // CHECK-NEXT: zip1 z10.h, z22.h, z31.x
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // Element size specifiers should match.
 zip1 z10.h, z3.h, z15.b
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: zip1 z10.h, z3.h, z15.b
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // Too few operands
 zip1 z1.h, z2.h
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
 // CHECK-NEXT: zip1 z1.h, z2.h
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // z32 is not a valid SVE data register
 zip1 z1.s, z2.s, z32.s
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: zip1 z1.s, z2.s, z32.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // p16 is not a valid SVE predicate register
 zip1 p1.s, p2.s, p16.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: zip1 p1.s, p2.s, p16.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // Combining data and predicate registers as operands
 zip1 z1.s, z2.s, p3.s
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: zip1 z1.s, z2.s, p3.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // Combining predicate and data registers as operands
 zip1 p1.s, p2.s, z3.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: zip1 p1.s, p2.s, z3.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE/zip2-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
 
 // Invalid element kind.
 zip2 z6.h, z23.h, z31.x
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
 // CHECK-NEXT: zip2 z6.h, z23.h, z31.x
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // Element size specifiers should match.
 zip2 z0.h, z30.h, z24.b
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: zip2 z0.h, z30.h, z24.b
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // Too few operands
 zip2 z1.h, z2.h
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
 // CHECK-NEXT: zip2 z1.h, z2.h
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // z32 is not a valid SVE data register
 zip2 z1.s, z2.s, z32.s
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: zip2 z1.s, z2.s, z32.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // p16 is not a valid SVE predicate register
 zip2 p1.s, p2.s, p16.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: zip2 p1.s, p2.s, p16.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // Combining data and predicate registers as operands
 zip2 z1.s, z2.s, p3.s
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: zip2 z1.s, z2.s, p3.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // Combining predicate and data registers as operands
 zip2 p1.s, p2.s, z3.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: zip2 p1.s, p2.s, z3.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: