Support inline asm with multiple 64bit output in 32bit GPR

[thopre]

Summary

Extend fix for PR34170 to support inline assembly with multiple output operands that do not naturally go in the register class it is constrained to (eg. double in a 32-bit GPR as in the PR).

[thopre]

Ping?

[thopre]

Rebase

[thopre]

Rename testcase and test both soft and hard float ABI

[thopre]

Rebase on latest version of previous patch in stack

[thopre]

Rebase and rename testcase for consistency

[thopre]

Ping? This fix the bug reported in https://reviews.llvm.org/rL337903

[efriedma]

This fix the bug reported in https://reviews.llvm.org/rL337903

Do we have test coverage for that issue reported in that email? If not, please add a testcase.

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

7719

isSized()? How can you end up with an unsized value here?

7739

This part of the patch is just whitespace changes?

test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll

175 ↗

(On Diff #157980)

Please add a test for multiple return values with matching inputs.

[thopre]

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

7719

It was in the original code so I kept it. I've now changed it to an assert and can confirm the testsuite shows no regression.

7739

The comment yes, the rest is s/ResultType/ResultVT

[thopre]

• Change test for isSized() into assert
• Add test for multiple return values with matching input
• Rewrite hardfloat tests to return a struct to make register used predictable and not dependent on register allocator

[efriedma]

LGTM

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
   Flag = Chain.getValue(1);
 
   // If this asm returns a register value, copy the result from that register
   // and set it as the value of the call.
   if (!RetValRegs.Regs.empty()) {
     SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
                                              Chain, &Flag, CS.getInstruction());
 
-    // FIXME: Why don't we do this for inline asms with MRVs?
-    if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
-      EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
-
+    llvm::Type *CSResultType = CS.getType();
+    unsigned numRet;
+    ArrayRef<Type *> ResultTypes;
+    SmallVector<SDValue, 1> ResultValues(1);
+    if (CSResultType->isSingleValueType()) {
+      numRet = 1;
+      ResultValues[0] = Val;
+      ResultTypes = makeArrayRef(CSResultType);
+    } else {
+      numRet = CSResultType->getNumContainedTypes();
+      assert(Val->getNumOperands() == numRet &&
+             "Mismatch in number of output operands in asm result");
+      ResultTypes = CSResultType->subtypes();
+      ArrayRef<SDUse> ValueUses = Val->ops();
+      ResultValues.resize(numRet);
+      std::transform(ValueUses.begin(), ValueUses.end(), ResultValues.begin(),
+                     [](const SDUse &u) -> SDValue { return u.get(); });
+    }
+    SmallVector<EVT, 1> ResultVTs(numRet);
+    for (unsigned i = 0; i < numRet; i++) {
+      EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), ResultTypes[i]);
+      SDValue Val = ResultValues[i];
+      if (ResultTypes[i]->isSized()) {
         // If the type of the inline asm call site return value is different but
         // has same size as the type of the asm output bitcast it.  One example
         // of this is for vectors with different width / number of elements.
         // This can happen for register classes that can contain multiple
         // different value types.  The preg or vreg allocated may not have the
         // same VT as was expected.
         //
         // This can also happen for a return value that disagrees with the
         // register class it is put in, eg. a double in a general-purpose
         // register on a 32-bit machine.
-      if (ResultType != Val.getValueType() &&
-          ResultType.getSizeInBits() == Val.getValueSizeInBits()) {
-        Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
-                          ResultType, Val);
-
-      } else if (ResultType != Val.getValueType() &&
-                 ResultType.isInteger() && Val.getValueType().isInteger()) {
-        // If a result value was tied to an input value, the computed result may
-        // have a wider width than the expected result.  Extract the relevant
-        // portion.
-        Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
+        if (ResultVT != Val.getValueType() &&
+            ResultVT.getSizeInBits() == Val.getValueSizeInBits()) {
+          Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(), ResultVT, Val);
+
+        } else if (ResultVT != Val.getValueType() && ResultVT.isInteger() &&
+                   Val.getValueType().isInteger()) {
+          // If a result value was tied to an input value, the computed result
+          // may have a wider width than the expected result.  Extract the
+          // relevant portion.
+          Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultVT, Val);
         }
 
-      assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
+        assert(ResultVT == Val.getValueType() && "Asm result value mismatch!");
+      }
+      ResultVTs[i] = ResultVT;
+      ResultValues[i] = Val;
     }
 
+    Val = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
+                      DAG.getVTList(ResultVTs), ResultValues);
     setValue(CS.getInstruction(), Val);
     // Don't need to use this as a chain in this case.
     if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
       return;
   }
 
   std::vector<std::pair<SDValue, const Value *>> StoresToEmit;
 

test/CodeGen/ARM/pr34170.ll

 define double @dbl_gpr_matching_in_op(double %d) nounwind {
 ; CHECK-LABEL: dbl_gpr_matching_in_op
 ; CHECK: mov r1, r0
 ; CHECK: vmov d0, r0, r1
   %1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d)
   ret double %1
 }
 
+; Check support for returning several double in GPR
+define double @zerobits_double_convoluted() #0 {
+; CHECK-LABEL: zerobits_double_convoluted
+; CHECK: mov r0, #0
+; CHECK-NEXT: mov r1, #0
+; CHECK-NEXT: mov r2, #0
+; CHECK-NEXT: mov r3, #0
+; CHECK: vmov {{d[[:digit:]]+}}, r2, r3
+; CHECK-NEXT: vmov {{d[[:digit:]]+}}, r0, r1
+  %1 = call { double, double } asm "mov ${0:Q}, #0; mov ${0:R}, #0; mov ${1:Q}, #0; mov ${1:R}, #0", "=r,=r"()
+  %asmresult = extractvalue { double, double } %1, 0
+  %asmresult1 = extractvalue { double, double } %1, 1
+  %add = fadd double %asmresult, %asmresult1
+  ret double %add
+}
+
 attributes #0 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" }