[AMDGPU][MC][GFX9] Added instructions *saveexec*, *wrexec* and *bitreplicate*

[dp]

Summary

See bug 36840: https://bugs.llvm.org/show_bug.cgi?id=36840

A list of added instructions:

s_andn1_saveexec_b64
s_orn1_saveexec_b64

s_andn1_wrexec_b64
s_andn2_wrexec_b64

s_bitreplicate_b64_b32

[artem.tamazov]

test/MC/AMDGPU/sop1.s

52

Is this being tested for GFX9?

[dp]

test/MC/AMDGPU/sop1.s

52

I tried to minimize changes in tests, so VI means VI+ here.
Should I correct the file using our traditional notation?
I.e. 'VI' means VI only, etc?

[dp]

Corrected asm tests to use traditional notation (GFX89 instead of VI)

[artem.tamazov]

In D45250#1056997, @dp wrote:

Corrected asm tests to use traditional notation (GFX89 instead of VI)

Thanks, I think that's cleaner for dummies like me))

[artem.tamazov]

LGTM

lib/Target/AMDGPU/SOPInstructions.td

 
 let SubtargetPredicate = HasVGPRIndexMode in {
 def S_SET_GPR_IDX_IDX : SOP1_0_32<"s_set_gpr_idx_idx"> {
   let Uses = [M0];
   let Defs = [M0];
 }
 }
 
+let SubtargetPredicate = isGFX9 in {
+  let hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC] in {
+    def S_ANDN1_SAVEEXEC_B64 : SOP1_64<"s_andn1_saveexec_b64">;
+    def S_ORN1_SAVEEXEC_B64  : SOP1_64<"s_orn1_saveexec_b64">;
+    def S_ANDN1_WREXEC_B64   : SOP1_64<"s_andn1_wrexec_b64">;
+    def S_ANDN2_WREXEC_B64   : SOP1_64<"s_andn2_wrexec_b64">;
+  } // End hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC]
+
+  def S_BITREPLICATE_B64_B32 : SOP1_64_32<"s_bitreplicate_b64_b32">;
+} // End SubtargetPredicate = isGFX9
+
 //===----------------------------------------------------------------------===//
 // SOP2 Instructions
 //===----------------------------------------------------------------------===//
 
 class SOP2_Pseudo<string opName, dag outs, dag ins,
                   string asmOps, list<dag> pattern=[]> :
   SOP_Pseudo<opName, outs, ins, asmOps, pattern> {
 

 def S_ADDK_I32_vi          : SOPK_Real_vi <0x0E, S_ADDK_I32>;
 def S_MULK_I32_vi          : SOPK_Real_vi <0x0F, S_MULK_I32>;
 def S_CBRANCH_I_FORK_vi    : SOPK_Real_vi <0x10, S_CBRANCH_I_FORK>;
 def S_GETREG_B32_vi        : SOPK_Real_vi <0x11, S_GETREG_B32>;
 def S_SETREG_B32_vi        : SOPK_Real_vi <0x12, S_SETREG_B32>;
 //def S_GETREG_REGRD_B32_vi  : SOPK_Real_vi <0x13, S_GETREG_REGRD_B32>; // see pseudo for comments
 def S_SETREG_IMM32_B32_vi  : SOPK_Real64<0x14, S_SETREG_IMM32_B32>,
                              Select_vi<S_SETREG_IMM32_B32.Mnemonic>;
+
+//===----------------------------------------------------------------------===//
+// SOP1 - GFX9.
+//===----------------------------------------------------------------------===//
+
+def S_ANDN1_SAVEEXEC_B64_vi   : SOP1_Real_vi<0x33, S_ANDN1_SAVEEXEC_B64>;
+def S_ORN1_SAVEEXEC_B64_vi    : SOP1_Real_vi<0x34, S_ORN1_SAVEEXEC_B64>;
+def S_ANDN1_WREXEC_B64_vi     : SOP1_Real_vi<0x35, S_ANDN1_WREXEC_B64>;
+def S_ANDN2_WREXEC_B64_vi     : SOP1_Real_vi<0x36, S_ANDN2_WREXEC_B64>;
+def S_BITREPLICATE_B64_B32_vi : SOP1_Real_vi<0x37, S_BITREPLICATE_B64_B32>;

test/MC/AMDGPU/sop1.s

 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefix=NOSICI %s
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefix=NOSICI --check-prefix=NOSICIVI %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=VI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s 2>&1 | FileCheck --check-prefix=NOVI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s 2>&1 | FileCheck --check-prefix=NOVI --check-prefix=NOSICIVI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=VI --check-prefix=GFX9 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck --check-prefix=NOGFX89 %s
 
 s_mov_b32 s1, s2
 // SICI: s_mov_b32 s1, s2 ; encoding: [0x02,0x03,0x81,0xbe]
 // VI:   s_mov_b32 s1, s2 ; encoding: [0x02,0x00,0x81,0xbe]
 
 s_mov_b32 s1, 1
 // SICI: s_mov_b32 s1, 1 ; encoding: [0x81,0x03,0x81,0xbe]
 // VI:   s_mov_b32 s1, 1 ; encoding: [0x81,0x00,0x81,0xbe]

 // VI:   s_mov_b64 s[2:3], 0xffffffff ; encoding: [0xff,0x01,0x82,0xbe,0xff,0xff,0xff,0xff]
 
 s_mov_b64 s[0:1], 0x80000000
 // SICI: s_mov_b64 s[0:1], 0x80000000 ; encoding: [0xff,0x04,0x80,0xbe,0x00,0x00,0x00,0x80]
 // VI:   s_mov_b64 s[0:1], 0x80000000 ; encoding: [0xff,0x01,0x80,0xbe,0x00,0x00,0x00,0x80]
 
 s_mov_b64 s[102:103], -1
 // SICI: s_mov_b64 s[102:103], -1 ; encoding: [0xc1,0x04,0xe6,0xbe]
-// NOVI: error: not a valid operand
+// NOGFX89: error: not a valid operand
 
 s_cmov_b32 s1, 200
 // SICI: s_cmov_b32 s1, 0xc8 ; encoding: [0xff,0x05,0x81,0xbe,0xc8,0x00,0x00,0x00]
 // VI:   s_cmov_b32 s1, 0xc8 ; encoding: [0xff,0x02,0x81,0xbe,0xc8,0x00,0x00,0x00]
 
 s_cmov_b32 s1, 1.0
 // SICI: s_cmov_b32 s1, 1.0 ; encoding: [0xf2,0x05,0x81,0xbe]
 // VI:   s_cmov_b32 s1, 1.0 ; encoding: [0xf2,0x02,0x81,0xbe]
 
 s_cmov_b32 s1, s2
 // SICI: s_cmov_b32 s1, s2 ; encoding: [0x02,0x05,0x81,0xbe]
 // VI:   s_cmov_b32 s1, s2 ; encoding: [0x02,0x02,0x81,0xbe]

 // VI:   s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2d,0x82,0xbe]
 
 s_cbranch_join s4
 // SICI: s_cbranch_join s4 ; encoding: [0x04,0x32,0x80,0xbe]
 // VI:   s_cbranch_join s4 ; encoding: [0x04,0x2e,0x80,0xbe]
 
 s_cbranch_join 1
 // NOSICI: error: invalid operand for instruction
-// NOVI: error: invalid operand for instruction
+// NOGFX89: error: invalid operand for instruction
 
 s_cbranch_join 100
 // NOSICI: error: invalid operand for instruction
-// NOVI: error: invalid operand for instruction
+// NOGFX89: error: invalid operand for instruction
 
 s_abs_i32 s1, s2
 // SICI: s_abs_i32 s1, s2 ; encoding: [0x02,0x34,0x81,0xbe]
 // VI:   s_abs_i32 s1, s2 ; encoding: [0x02,0x30,0x81,0xbe]
 
 s_mov_fed_b32 s1, s2
 // SICI: s_mov_fed_b32 s1, s2 ; encoding: [0x02,0x35,0x81,0xbe]
 
 s_set_gpr_idx_idx s0
 // VI: s_set_gpr_idx_idx s0 ; encoding: [0x00,0x32,0x80,0xbe]
 // NOSICI: error: instruction not supported on this GPU
+
+s_andn1_saveexec_b64 s[100:101], s[2:3]
+// GFX9:     s_andn1_saveexec_b64 s[100:101], s[2:3] ; encoding: [0x02,0x33,0xe4,0xbe]
+// NOSICIVI: error: instruction not supported on this GPU
+
+s_andn1_saveexec_b64 s[10:11], s[4:5]
+// GFX9:     s_andn1_saveexec_b64 s[10:11], s[4:5] ; encoding: [0x04,0x33,0x8a,0xbe]
+// NOSICIVI: error: instruction not supported on this GPU
+
+s_andn1_saveexec_b64 s[10:11], -1
+// GFX9:     s_andn1_saveexec_b64 s[10:11], -1 ; encoding: [0xc1,0x33,0x8a,0xbe]
+// NOSICIVI: error: instruction not supported on this GPU
+
+s_andn1_saveexec_b64 s[10:11], 0xaf123456
+// GFX9:     s_andn1_saveexec_b64 s[10:11], 0xaf123456 ; encoding: [0xff,0x33,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+// NOSICIVI: error: instruction not supported on this GPU
+
+s_andn1_wrexec_b64 s[10:11], s[2:3]
+// GFX9:     s_andn1_wrexec_b64 s[10:11], s[2:3] ; encoding: [0x02,0x35,0x8a,0xbe]
+// NOSICIVI: error: instruction not supported on this GPU
+
+s_andn2_wrexec_b64 s[12:13], s[2:3]
+// GFX9:     s_andn2_wrexec_b64 s[12:13], s[2:3] ; encoding: [0x02,0x36,0x8c,0xbe]
+// NOSICIVI: error: instruction not supported on this GPU
+
+s_orn1_saveexec_b64 s[10:11], 0
+// GFX9:     s_orn1_saveexec_b64 s[10:11], 0 ; encoding: [0x80,0x34,0x8a,0xbe]
+// NOSICIVI: error: instruction not supported on this GPU
+
+s_bitreplicate_b64_b32 s[10:11], s101
+// GFX9:     s_bitreplicate_b64_b32 s[10:11], s101 ; encoding: [0x65,0x37,0x8a,0xbe]
+// NOSICIVI: error: instruction not supported on this GPU
+
+s_bitreplicate_b64_b32 s[10:11], -1
+// GFX9:     s_bitreplicate_b64_b32 s[10:11], -1 ; encoding: [0xc1,0x37,0x8a,0xbe]
+// NOSICIVI: error: instruction not supported on this GPU
+
+s_bitreplicate_b64_b32 s[10:11], 0x3f717273
+// GFX9:     s_bitreplicate_b64_b32 s[10:11], 0x3f717273 ; encoding: [0xff,0x37,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+// NOSICIVI: error: instruction not supported on this GPU

test/MC/Disassembler/AMDGPU/sop1_gfx9.txt

+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX9
+
+# GFX9: s_andn1_saveexec_b64 s[10:11], s[2:3] ; encoding: [0x02,0x33,0x8a,0xbe]
+0x02,0x33,0x8a,0xbe
+
+# GFX9: s_andn1_saveexec_b64 s[10:11], 0 ; encoding: [0x80,0x33,0x8a,0xbe]
+0x80,0x33,0x8a,0xbe
+
+# GFX9: s_andn1_wrexec_b64 s[100:101], s[2:3] ; encoding: [0x02,0x35,0xe4,0xbe]
+0x02,0x35,0xe4,0xbe
+
+# GFX9: s_andn1_wrexec_b64 s[10:11], 0xaf123456 ; encoding: [0xff,0x35,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+0xff,0x35,0x8a,0xbe,0x56,0x34,0x12,0xaf
+
+# GFX9: s_andn2_wrexec_b64 s[10:11], s[100:101] ; encoding: [0x64,0x36,0x8a,0xbe]
+0x64,0x36,0x8a,0xbe
+
+# GFX9: s_andn2_wrexec_b64 s[10:11], -1 ; encoding: [0xc1,0x36,0x8a,0xbe]
+0xc1,0x36,0x8a,0xbe
+
+# GFX9: s_orn1_saveexec_b64 s[10:11], -1 ; encoding: [0xc1,0x34,0x8a,0xbe]
+0xc1,0x34,0x8a,0xbe
+
+# GFX9: s_orn1_saveexec_b64 s[10:11], 0x3f717273 ; encoding: [0xff,0x34,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+0xff,0x34,0x8a,0xbe,0x73,0x72,0x71,0x3f
+
+# GFX9: s_bitreplicate_b64_b32 s[10:11], s101 ; encoding: [0x65,0x37,0x8a,0xbe]
+0x65,0x37,0x8a,0xbe
+
+# GFX9: s_bitreplicate_b64_b32 s[10:11], 0 ; encoding: [0x80,0x37,0x8a,0xbe]
+0x80,0x37,0x8a,0xbe
+
+# GFX9: s_bitreplicate_b64_b32 s[10:11], 0xaf123456 ; encoding: [0xff,0x37,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+0xff,0x37,0x8a,0xbe,0x56,0x34,0x12,0xaf