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timcorringham (Tim Corringham)
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User Since
Apr 26 2017, 9:47 AM (177 w, 2 d)

Recent Activity

Mon, Sep 14

timcorringham added a comment to D84779: [AMDGPU] Add amdgpu specific loop threshold metadata.

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Mon, Sep 14, 2:27 AM · Restricted Project

Mon, Sep 7

timcorringham added a comment to D84779: [AMDGPU] Add amdgpu specific loop threshold metadata.

Ping

Mon, Sep 7, 4:55 AM · Restricted Project

Tue, Sep 1

timcorringham added a comment to D84779: [AMDGPU] Add amdgpu specific loop threshold metadata.

Does anyone still have concerns with this change?

Tue, Sep 1, 3:34 AM · Restricted Project

Tue, Aug 25

timcorringham added a comment to D84779: [AMDGPU] Add amdgpu specific loop threshold metadata.

You are correct that the threshold value is something of a magic number, but it is what the unroll pass uses to help decide whether to unroll a loop fully or partially. Even when using an unroll factor the amount of unrolling performed may change in response to changes which affect the loop size computation if that pushes the loop over the threshold.

Tue, Aug 25, 11:28 AM · Restricted Project
timcorringham updated the diff for D84779: [AMDGPU] Add amdgpu specific loop threshold metadata.

Amended variable name

Tue, Aug 25, 11:07 AM · Restricted Project

Mon, Aug 24

timcorringham updated the diff for D84779: [AMDGPU] Add amdgpu specific loop threshold metadata.

Changed the metadata from amdgpu.loop.unroll.threshold to llvm.loop.unroll.threshold

Mon, Aug 24, 6:58 AM · Restricted Project

Aug 18 2020

timcorringham added a comment to D84779: [AMDGPU] Add amdgpu specific loop threshold metadata.

Ignoring the explicit unroll hints (disable, full, count) for now, the loop unrolling is controlled by the threshold. Loops are unrolled. either fully or partially, up to the threshold.

Aug 18 2020, 5:23 AM · Restricted Project

Aug 10 2020

timcorringham added a comment to D84779: [AMDGPU] Add amdgpu specific loop threshold metadata.

As I said in my reply to Matt, I made it target specific to avoid cluttering the llvm.loop metadata with something that is only used by one target. I am happy to make it llvm.loop.unroll.threshold if that is considered better.

Aug 10 2020, 5:27 AM · Restricted Project
timcorringham added inline comments to D84779: [AMDGPU] Add amdgpu specific loop threshold metadata.
Aug 10 2020, 5:21 AM · Restricted Project

Aug 7 2020

timcorringham added a comment to D84779: [AMDGPU] Add amdgpu specific loop threshold metadata.

To answer Matt's question, there isn't currently metadata to set the threshold - there is a function attribute that I added that allows the default to be set which is similar, but that of course uses the same value for all loops within a function. However, that doesn't give the per-loop control we have since discovered we need for graphics applications.

Aug 7 2020, 2:39 AM · Restricted Project

Aug 6 2020

timcorringham added a comment to D84779: [AMDGPU] Add amdgpu specific loop threshold metadata.

There is some more info about the motivation for this in https://github.com/GPUOpen-Drivers/llpc/pull/863

Aug 6 2020, 2:21 AM · Restricted Project

Jul 29 2020

timcorringham updated the diff for D84779: [AMDGPU] Add amdgpu specific loop threshold metadata.

Fixed case style of variable.

Jul 29 2020, 4:21 AM · Restricted Project

Jul 28 2020

timcorringham added reviewers for D84779: [AMDGPU] Add amdgpu specific loop threshold metadata: nhaehnle, arsenm.
Jul 28 2020, 11:26 AM · Restricted Project
timcorringham requested review of D84779: [AMDGPU] Add amdgpu specific loop threshold metadata.
Jul 28 2020, 11:23 AM · Restricted Project

Jun 24 2020

timcorringham committed rGc3b3b999ec9e: [AMDGPU] Avoid redundant mode register writes (authored by timcorringham).
[AMDGPU] Avoid redundant mode register writes
Jun 24 2020, 6:27 AM
timcorringham closed D82215: [AMDGPU] Avoid redundant mode register writes.
Jun 24 2020, 6:27 AM · Restricted Project
timcorringham added inline comments to D82215: [AMDGPU] Avoid redundant mode register writes.
Jun 24 2020, 5:54 AM · Restricted Project

Jun 22 2020

timcorringham committed rG96ecead5a221: [AMDGPU] clang-format of SIModeRegister.cpp (authored by timcorringham).
[AMDGPU] clang-format of SIModeRegister.cpp
Jun 22 2020, 5:53 AM
timcorringham updated the diff for D82215: [AMDGPU] Avoid redundant mode register writes.

Removed changes introduced only by clang-format format.

Jun 22 2020, 5:52 AM · Restricted Project
timcorringham added inline comments to D82215: [AMDGPU] Avoid redundant mode register writes.
Jun 22 2020, 3:43 AM · Restricted Project

Jun 19 2020

timcorringham added reviewers for D82215: [AMDGPU] Avoid redundant mode register writes: arsenm, tpr, foad.
Jun 19 2020, 10:52 AM · Restricted Project
timcorringham created D82215: [AMDGPU] Avoid redundant mode register writes.
Jun 19 2020, 10:52 AM · Restricted Project

Nov 21 2019

timcorringham committed rG6821a3ccd69f: [AMDGPU] Add attribute for target loop unroll threshold default (authored by timcorringham).
[AMDGPU] Add attribute for target loop unroll threshold default
Nov 21 2019, 2:00 AM
timcorringham closed D68873: [AMDGPU] Amend target loop unroll defaults.
Nov 21 2019, 2:00 AM · Restricted Project

Nov 20 2019

timcorringham updated the diff for D68873: [AMDGPU] Amend target loop unroll defaults.

Added test to confirm that the amdgpu-unroll-threshold attribute has the expected effect.

Nov 20 2019, 7:28 AM · Restricted Project

Nov 18 2019

timcorringham updated the diff for D68873: [AMDGPU] Amend target loop unroll defaults.

Function attribute for loop unroll threshold default

Nov 18 2019, 9:20 AM · Restricted Project

Oct 17 2019

timcorringham added inline comments to D68873: [AMDGPU] Amend target loop unroll defaults.
Oct 17 2019, 7:39 AM · Restricted Project
timcorringham updated the diff for D68873: [AMDGPU] Amend target loop unroll defaults.

Changes to address review comments

Oct 17 2019, 7:39 AM · Restricted Project

Oct 11 2019

timcorringham added a reviewer for D68873: [AMDGPU] Amend target loop unroll defaults: Restricted Project.
Oct 11 2019, 9:28 AM · Restricted Project
timcorringham created D68873: [AMDGPU] Amend target loop unroll defaults.
Oct 11 2019, 9:19 AM · Restricted Project

Oct 7 2019

timcorringham closed D45246: Add AMDPAL Code Conventions section to AMD docs.
Oct 7 2019, 4:33 AM · Restricted Project

Sep 23 2019

timcorringham committed rL372584: Request commit access for timcorringham.
Request commit access for timcorringham
Sep 23 2019, 5:02 AM

Aug 8 2019

timcorringham committed rG4f64f1ba3c54: Add llvm.licm.disable metadata (authored by timcorringham).
Add llvm.licm.disable metadata
Aug 8 2019, 6:48 AM
timcorringham committed rL368296: Add llvm.licm.disable metadata.
Add llvm.licm.disable metadata
Aug 8 2019, 6:45 AM
timcorringham closed D64557: Add llvm.loop.licm.disable metadata.
Aug 8 2019, 6:45 AM · Restricted Project

Aug 5 2019

timcorringham added a comment to D64557: Add llvm.loop.licm.disable metadata.

Does anyone have any remaining concerns with this as it is now?

Aug 5 2019, 8:54 AM · Restricted Project

Jul 29 2019

timcorringham updated the diff for D64557: Add llvm.loop.licm.disable metadata.

Simplified the LIT test

Jul 29 2019, 7:36 AM · Restricted Project

Jul 22 2019

timcorringham added a comment to D64557: Add llvm.loop.licm.disable metadata.

Some cases can be undone by rematerialization, but not all, and it can involve a lot of effort which increases compile time. The metadata is a pragmatic approach which helps in some cases.

Jul 22 2019, 3:10 AM · Restricted Project
timcorringham updated the diff for D64557: Add llvm.loop.licm.disable metadata.

Changed the metadata name to llvm.licm.disable

Jul 22 2019, 3:02 AM · Restricted Project

Jul 15 2019

timcorringham accepted D64720: AMDGPU: Fix missing immarg from interp intrinsics.
Jul 15 2019, 6:42 AM

Jul 11 2019

timcorringham added a comment to D64557: Add llvm.loop.licm.disable metadata.

Unfortunately I don't believe I have an example that is suitable for publishing. The problem is basically that the code motion is generally a good thing, but it can increase live ranges significantly pushing register pressure up such that performance is degraded, but that impact isn't apparent at the point at which the transformation is performed. Disabling the pass for certain loops is a low-impact pragmatic (but not ideal) solution.

Jul 11 2019, 7:33 AM · Restricted Project
timcorringham updated the diff for D64557: Add llvm.loop.licm.disable metadata.

Update LangRef doc

Jul 11 2019, 7:06 AM · Restricted Project
timcorringham added a comment to D64557: Add llvm.loop.licm.disable metadata.

The target in this case is AMDGPU, and the problem is that transformations can create excessive register pressure ( but I don't believe this is necessarily unique to that target). The front-end has additional information available which can sometimes be used to identify such cases.

Jul 11 2019, 4:48 AM · Restricted Project
timcorringham added reviewers for D64557: Add llvm.loop.licm.disable metadata: Restricted Project, arsenm.
Jul 11 2019, 4:41 AM · Restricted Project
timcorringham created D64557: Add llvm.loop.licm.disable metadata.
Jul 11 2019, 4:36 AM · Restricted Project

May 8 2019

timcorringham added a comment to D61595: [SIMode] Fix typo in Status constructor.

Sorry not to have noticed this sooner - I was just about to make a fix myself. I chose to change the constructor to

May 8 2019, 2:35 AM · Restricted Project

Feb 1 2019

timcorringham committed rL352885: [AMDGPU] Fix for vector element insertion.
[AMDGPU] Fix for vector element insertion
Feb 1 2019, 8:51 AM
timcorringham closed D57588: [AMDGPU] Fix for vector element insertion.
Feb 1 2019, 8:51 AM · Restricted Project
timcorringham added reviewers for D57588: [AMDGPU] Fix for vector element insertion: arsenm, nhaehnle.
Feb 1 2019, 7:19 AM · Restricted Project
timcorringham created D57588: [AMDGPU] Fix for vector element insertion.
Feb 1 2019, 7:05 AM · Restricted Project

Jan 28 2019

timcorringham committed rL352358: [AMDGPU] Add interpolation builtins.
[AMDGPU] Add interpolation builtins
Jan 28 2019, 5:50 AM
timcorringham committed rC352358: [AMDGPU] Add interpolation builtins.
[AMDGPU] Add interpolation builtins
Jan 28 2019, 5:50 AM
timcorringham closed D46871: [AMDGPU] Add interpolation builtins.
Jan 28 2019, 5:50 AM
timcorringham committed rL352357: [AMDGPU] Add intrinsics for 16 bit interpolation.
[AMDGPU] Add intrinsics for 16 bit interpolation
Jan 28 2019, 5:49 AM
timcorringham closed D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.
Jan 28 2019, 5:49 AM

Jan 24 2019

timcorringham added inline comments to D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.
Jan 24 2019, 9:33 AM
timcorringham updated the diff for D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.

Extended llvm.amdgcn.interp.f16.ll to check that m0 is set before
each interp instruction if necessary, and added a new LIT test
to check that the interp f16 intrinsics are identified as being
divergent.

Jan 24 2019, 9:31 AM

Dec 18 2018

timcorringham updated the diff for D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.

Rebased, and amended LIT test now that the required mode register
pass has been committed.

Dec 18 2018, 1:53 AM

Dec 11 2018

timcorringham closed D50633: [AMDGPU] Add new Mode Register pass.

I forgot to add the Phabricator Review to the commit - whoops!

Dec 11 2018, 3:11 AM

Dec 10 2018

timcorringham committed rL348767: [AMDGPU] Add new Mode Register pass - minor fix.
[AMDGPU] Add new Mode Register pass - minor fix
Dec 10 2018, 8:26 AM
timcorringham committed rL348754: [AMDGPU] Add new Mode Register pass.
[AMDGPU] Add new Mode Register pass
Dec 10 2018, 4:09 AM

Nov 30 2018

timcorringham updated the diff for D50633: [AMDGPU] Add new Mode Register pass.

Reordered the cases dealt with in Phase 1 so that the most specific
case (setreg instruction) is performed first, allowing the removal
of one condition, and reduced indentation for that case accordingly.

Nov 30 2018, 8:33 AM
timcorringham added inline comments to D50633: [AMDGPU] Add new Mode Register pass.
Nov 30 2018, 4:21 AM
timcorringham updated the diff for D50633: [AMDGPU] Add new Mode Register pass.

Removed redundant call to merge mode register status.

Nov 30 2018, 4:19 AM

Nov 21 2018

timcorringham updated the diff for D50633: [AMDGPU] Add new Mode Register pass.

Amended the declaration of NewInfo.

Nov 21 2018, 2:29 AM
timcorringham updated the diff for D50633: [AMDGPU] Add new Mode Register pass.

Fixed minor formatting issues, and amended the way mode changes are
combined into as few setreg instrcutions as possible.

Nov 21 2018, 2:04 AM

Nov 12 2018

timcorringham added a comment to D50633: [AMDGPU] Add new Mode Register pass.

Amended SIModeRegister to address some minor points, and added comments to help explain why it appears more complex than necessary.

Nov 12 2018, 6:58 AM
timcorringham updated the diff for D50633: [AMDGPU] Add new Mode Register pass.

Refactored SIModeRegister.cpp slightly and added more comments to help explain the processing, and made a couple of minor changes to address review comments.

Nov 12 2018, 6:57 AM

Nov 1 2018

timcorringham added a comment to D50633: [AMDGPU] Add new Mode Register pass.

I'm afraid I don't know anything about OpenCL non-default rounding modes - are they set per arithmetic operation or per function? When will these be needed?

Nov 1 2018, 11:47 AM
timcorringham added a comment to D50633: [AMDGPU] Add new Mode Register pass.

Yes, I think that your suggestion is the correct solution in a perfect world. It is one of the possible approaches that we discussed in our team before implementing the current proposed solution.

Nov 1 2018, 11:23 AM

Oct 31 2018

timcorringham updated the diff for D50633: [AMDGPU] Add new Mode Register pass.

Fixes for observed failures:

  • Corrected which instructions are marked as using the double

precision floating point rounding mode flags

  • Changed the position where the first setreg in a block is

inserted in order to reduce the risk of hitting a hazard that
may exist at entry to the first block of a shader.

Oct 31 2018, 1:42 PM

Aug 16 2018

timcorringham added inline comments to D50633: [AMDGPU] Add new Mode Register pass.
Aug 16 2018, 4:25 AM

Aug 13 2018

timcorringham updated the diff for D50633: [AMDGPU] Add new Mode Register pass.

Minor amendments as per review comments.

Aug 13 2018, 12:21 PM
timcorringham added inline comments to D50633: [AMDGPU] Add new Mode Register pass.
Aug 13 2018, 12:20 PM
timcorringham added reviewers for D50633: [AMDGPU] Add new Mode Register pass: arsenm, Restricted Project, tpr.
Aug 13 2018, 6:45 AM
timcorringham created D50633: [AMDGPU] Add new Mode Register pass.
Aug 13 2018, 6:40 AM

Aug 1 2018

timcorringham updated the diff for D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.

Updated the LIT test as per review comments.

Aug 1 2018, 5:55 AM

Jul 24 2018

timcorringham updated the diff for D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.

Removed the mode register pass, as that will be introduced as a
separate change.

Jul 24 2018, 4:51 AM

Jul 10 2018

timcorringham updated the diff for D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.

Changed mode register pass to use an explicit stack instead of recursion.

Jul 10 2018, 8:32 AM
timcorringham updated the diff for D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.

Refactored pass to insert rounding mode to use a style more in line
with other LLVM passes. This fails to optimize a few corner cases,
but they are expected to occur very rarely if at all.

Jul 10 2018, 4:12 AM

Jul 9 2018

timcorringham updated the diff for D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.

A slighly more performant implementation of the pass to add any
required changes to the double precision rounding mode.

Jul 9 2018, 3:04 AM

Jul 3 2018

timcorringham updated the diff for D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.

[AMDGPU] Add intrinsics for 16 bit interpolation

Jul 3 2018, 7:31 AM

May 22 2018

timcorringham updated the diff for D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.

Change the omod operand type to be i32 rather than i1, to avoid
a build failure when building using a debug TableGen.

May 22 2018, 12:30 PM

May 21 2018

timcorringham updated the diff for D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.

Added a divergence LIT test for the 16 bit interp intrinsics.

May 21 2018, 8:50 AM

May 18 2018

timcorringham added a comment to D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.

Or is this bit controlling the weird load from memory? The manual isn't particularly clear to me. I see mention of LDs loads, but also op_sel control of destination bits

May 18 2018, 12:07 PM
timcorringham added a comment to D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.

Even without the high operand I don't think it is possible to overload interp_p1 and interp_p1_f16 as they would have identical types - there is nothing to disambiguate them.

May 18 2018, 11:32 AM
timcorringham updated the diff for D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.

Corrected the ordering of operands to interp_p2_f16, added lowered
intrinsics to list of those that cware a source of divergence, and
amended LIT test.

May 18 2018, 10:00 AM
timcorringham updated the diff for D46871: [AMDGPU] Add interpolation builtins.

[AMDGPU] Add interpolation builtins

May 18 2018, 3:12 AM

May 15 2018

timcorringham added inline comments to D46871: [AMDGPU] Add interpolation builtins.
May 15 2018, 8:07 AM
timcorringham added inline comments to D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.
May 15 2018, 4:56 AM
timcorringham added reviewers for D46871: [AMDGPU] Add interpolation builtins: arsenm, tpr, dstuttard, Restricted Project.
May 15 2018, 4:47 AM
timcorringham created D46871: [AMDGPU] Add interpolation builtins.
May 15 2018, 4:39 AM

May 11 2018

timcorringham added reviewers for D46754: [AMDGPU] Add intrinsics for 16 bit interpolation: Restricted Project, dstuttard, arsenm, tpr.
May 11 2018, 6:51 AM
timcorringham created D46754: [AMDGPU] Add intrinsics for 16 bit interpolation.
May 11 2018, 6:48 AM

Apr 4 2018

timcorringham committed rL329188: Add AMDPAL Code Conventions section to AMD docs.
Add AMDPAL Code Conventions section to AMD docs
Apr 4 2018, 6:05 AM
timcorringham closed D45246: Add AMDPAL Code Conventions section to AMD docs.
Apr 4 2018, 6:05 AM · Restricted Project
timcorringham added reviewers for D45246: Add AMDPAL Code Conventions section to AMD docs: dstuttard, t-tye, tpr.
Apr 4 2018, 3:53 AM · Restricted Project
timcorringham created D45246: Add AMDPAL Code Conventions section to AMD docs.
Apr 4 2018, 3:51 AM · Restricted Project

Mar 26 2018

timcorringham committed rL328553: [AMDGPU] Improve disassembler error handling.
[AMDGPU] Improve disassembler error handling
Mar 26 2018, 10:09 AM
timcorringham closed D44685: [AMDGPU] Improve disassembler error handling.
Mar 26 2018, 10:09 AM