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[GlobalISel][X86] Adding Testgen'd tests for InstructionSelect pass
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Authored by rtereshin on Mar 1 2018, 7:19 PM.

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Summary

Requires https://reviews.llvm.org/D43962, see the review for details.

The tests are generated by

../../utils/update_instruction_select_testgen_tests.sh ../../test/CodeGen/X86/GlobalISel/x86_64-instruction-select-testgen-testgend.mir llc x86_64-- -testgen-exclude-rules=0,378,379,448,449,450,451,452,453,469,470,471,472,473,474,490,491,492,493,494,495,511,512,513,514,515,516

Interestingly enough, turning ABI speculation off with -testgen-no-abi, resulting in defining input vregs with IMPLICIT_DEFs rather than actual copies from live-in phys regs, breaks the InstructionSelector more often. It would break on all the rules excluded above, but also on all of the following ones:

97,98,419,565,626,652,653,654,655,656,657,658,659,660,661,662,663,664,665,666,667,668,669,670,671,672,673,674,675,676,677,678,679,680,681,682,683,684,685,686,687,688,689,690,691,692,693,694,695,696,697,698,699,700,701,702,703,704,705,706,707,708,709,710,711,712,713,714,715,716,717,718,719,720,721,722,723,724,725,726,727,728,729,730,731,732,733,734,735,736,737,738,739,740,741,742,743,744

while having the exact same number of tested generated with failedISel: true.

For instance, in abi-on mode Testgen generates the following test case for selection rule #4 (trimmed a little for brevity):

---
name:            test_rule97_id15615_at_idx8289
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
liveins:
  - { reg: '$eax', virtual-reg: '%1' }
body:             |
  bb.0.entry:
    liveins: $eax

    %1:gpr(s32) = COPY $eax
    %2:gpr(s32) = G_CONSTANT 65535
    %0:gpr(s32) = G_AND %1, %2
    $noreg = PATCHABLE_RET %0(s32)
...

that would select just fine to

name:            test_rule97_id15615_at_idx8289
alignment:       4
legalized:       true
regBankSelected: true
selected:        true
tracksRegLiveness: true
registers:
  - { id: 0, class: gr32 }
  - { id: 1, class: gr32 }
  - { id: 2, class: gpr }
  - { id: 3, class: gr16 }
liveins:
  - { reg: '$eax', virtual-reg: '%1' }
body:             |
  bb.0.entry:
    liveins: $eax

    %1:gr32 = COPY $eax
    %3:gr16 = COPY %1.sub_16bit
    %0:gr32 = MOVZX32rr16 %3
    $noreg = PATCHABLE_RET %0
...

However, in -testgen-no-abi mode Testgen would generate this:

---
name:            test_rule97_id15615_at_idx8289
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
body:             |
  bb.0.entry:
    %1:gpr(s32) = IMPLICIT_DEF
    %2:gpr(s32) = G_CONSTANT 65535
    %0:gpr(s32) = G_AND %1, %2
    $noreg = PATCHABLE_RET %0(s32)
...

and x86's InstructionSelector crashes on it with

Selecting function: test_rule97_id15615_at_idx8289
Selecting:
  $noreg = PATCHABLE_RET %0:gpr(s32)
Into:
  $noreg = PATCHABLE_RET %0:gpr(s32)

Selecting:
  %0:gpr(s32) = G_AND %1:gpr, %2:gpr
Into:
  %3:gr16(s16) = COPY %1.sub_16bit:gpr(s32)
  %0:gr32(s32) = MOVZX32rr16 %3:gr16(s16)

Selecting:
  %2:gpr(s32) = G_CONSTANT 65535
Is dead; erasing.
Selecting:
  %1:gpr(s32) = IMPLICIT_DEF
Into:
  %1:gpr(s32) = IMPLICIT_DEF

Assertion failed: (VRegInfo[Reg].first.is<const TargetRegisterClass *>() && "Register class not set, wrong accessor"), function getRegClass, file ../../include/llvm/CodeGen/MachineRegisterInfo.h, line 607.
<...>
6  llc                      0x000000010ed61608 llvm::MachineRegisterInfo::getRegClass(unsigned int) const + 184
7  llc                      0x00000001100c7fbe llvm::InstructionSelect::runOnMachineFunction(llvm::MachineFunction&) + 3518
<...>
Stack dump:
0.	Program arguments: /Volumes/Data/llvm/build/obj/bin/llc -mtriple x86_64-- -run-pass instruction-select -testgen-set-all-features -disable-gisel-legality-check -verify-machineinstrs -simplify-mir with-no-abi.mir -o - -debug-only=instruction-select
1.	Running pass 'Function Pass Manager' on module 'with-no-abi.mir'.
2.	Running pass 'InstructionSelect' on function '@test_rule97_id15615_at_idx8289'

AFAICT the reason for that is only partial support of EXTRACT_SUBREG by GlobalISel emitter, which in this case is nested and doesn't restrict its operands' regclasses properly.

I would like to underline in this case that having ABI speculation sometimes allows to generate more tests and reach better coverage, that is one of the design goals of the Testgen.

I'm including the larger test with ABI speculation on in this patch, but I used the smaller one with more tests failing generated with -testgen-no-abi for stats presented in Coverage section of https://reviews.llvm.org/D43962

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rL LLVM

Event Timeline

rtereshin created this revision.Mar 1 2018, 7:19 PM
rtereshin abandoned this revision.May 16 2018, 10:08 PM

Dismissing this as outdated.