[PowerPC] Infrastructure work. Implement getting the opcode for a spill in one place.

[stefanp]

Summary

Currently we compute the opcode for a given type of register spill in a couple of different places. This means that when a register class is added or changed multiple places have to be checked to make sure that everything is updated correctly. A new function getOpcodeForSpill should now be the only place to get the opcode for a given spilled register.

[echristo]

Huge fan of refactorings :)

Some inline comments.

-eric

lib/Target/PowerPC/PPCInstrInfo.cpp

355

Could probably just pass the subtarget down rather than have the index.

lib/Target/PowerPC/PPCInstrInfo.h

112

Not a huge fan of this. Perhaps just have a local data structure inside the function?

lib/Target/PowerPC/PPCRegisterInfo.h

95 ↗

(On Diff #133469)

This seems unrelated?

[stefanp]

Addressed comments from reviewer and removed work that was not really related to this patch.
Will split out the work that was not really related into a separate patch.

[nemanjai]

lib/Target/PowerPC/PPCInstrInfo.cpp

76

I like the approach of having named indices into the data structure. However, I find the names a little too tied to the current opcodes. It is especially confusing when the enumerator name doesn't match the actual opcode. For example, on P9, you'll spill a VSR register using PPC::STXV which you get through the OpcodesForSpillKey::PPC_STXVD2X enumerator.

Also, it is somewhat customary and aids readability to have the name of the enum encoded in the names of the enumerators.

Can you rename them to something like enum SpillOpcodeKey for the enum and SOK_Int4Spill, SOK_Float8Spill, or something along those lines.

356

Not that this makes a very big difference, but it is a little more obvious what is happening if you just use std::find here.

1108

I would remove the reliance on opcodes here. You have the register class. Check it and call setSpillsCr() and setSpillsVRSAVE() accordingly.

1114

We are once again keeping a list of opcodes separately from the function that is supposed to have the definitive list of spill opcodes. So we aren't much better off.
I think would be a much cleaner approach to just use a query for whether an opcode is an X-Form or not. A similar trick is used in PPCRegisterInfo with the use of ImmToIdxMap.

I think the most reliable solution would be to implement this in the .td files with a mapping (similar to RecFormRel), but that can be left as a refactoring exercise for the future. For now, I'd implement a set of static function where one will contain the ImmToIdxMap and the rest will just perform queries on it:

static bool PPC::isXFormLdSt(unsigned Opcode);
static bool PPC::isDFormLdSt(unsigned Opcode);
static unsigned PPC::getXFormForDForm(unsigned Opcode);
static unsigned PPC::getDFormForXForm(unsigned Opcode);

Finally, in this function, I would assert that isXFormLdSt(Opcode) || isDFormLdSt(Opcode) to ensure that if we add another opcode for spilling/restoring, we don't break things.

lib/Target/PowerPC/PPCInstrInfo.h

129

This is a member function and you have a PPCSubtarget data member. You can check whether you're compiling for Power9 there, can't you?

[stefanp]

Added the XFormMemOp flag to the td files for the instructions the require it. This flag indicates that this instructions is a memory instruction and that it is an X-Form instruction.
Used a script to compare the modifications against the ISA to make sure that the correct instructions have the flag set.

[nemanjai]

This is starting to take shape quite nicely. I suspect you're planning a similar refactoring for the loads?

lib/Target/PowerPC/PPCInstr64Bit.td

248 ↗

(On Diff #138976)

For all of these, you need to move the line below so that the " lines up under the 3 (i.e. parameters on multiple lines start at the same column).

1160 ↗

(On Diff #138976)

Line too long.

lib/Target/PowerPC/PPCInstrFormats.td

117 ↗

(On Diff #138976)

// Base class for all X-Form memory instructions

449 ↗

(On Diff #138976)

This line is too long. In any case, do we have to redefine this? Seems like just copy-paste. Can we not just inherit from both XForm_base_r3xo and XFormMemOp without a re-definition?

1066 ↗

(On Diff #138976)

Similarly here. Do we have to provide a definition or can we just inherit from XX1Form and XFormMemOp?

But perhaps I've missed something.

lib/Target/PowerPC/PPCInstrInfo.cpp

1098

I prefer that we make arguments self-documenting when possible. Please instead of 0, pass PPC::NoRegister.

1115

This seems like a strange way to get to the flags. Can you not just get(Opcode).TSFlags since you're in PPCInstrInfo already?

2324

Please use a ternary operator here with 0/1. They should be equivalent, but I've come across UBSan failures where we load other values - so until we figure out whether that's a PPC problem or not, I'd prefer being explicit about this.

lib/Target/PowerPC/PPCInstrInfo.td

2025 ↗

(On Diff #138976)

Line too long. I probably won't notice all of them, but please be careful about this.

[stefanp]

Implemented the cleanup for the loads as well.
Addressed comments from the reviewer.

Also had to fixup one test file. After both the stores and the loads were fixed some instructions that had previously incorrectly set the setHasNonRISpills() flag no longer do so.

[nemanjai]

Thank you for your patience with this review cycle and for cleaning this up. It looks much better now and it's really nice not to have to maintain lists of opcodes in multiple places that have to be kept in sync.

Other than the few minor nits which you should feel free to fix on the commit, LGTM.

lib/Target/PowerPC/PPCInstr64Bit.td

841 ↗

(On Diff #139235)

It seems that you've fixed the indentation on the above, but not on any of these. Please indent the continuation line so that the first character (") is under the first character of the parameter in the line above (3).

lib/Target/PowerPC/PPCInstrInfo.cpp

91

Don't forget periods on comments - complete sentences.

1091

Something is off in the formatting of the signature. Please run clang-format on the new code you've added. I think you can run clang-format-diff on the actual diff, but I haven't tried that.

1115

Just another minor suggestion, since this is probably going to be useful in other places, can you just provide something like static bool isXFormMemOp(unsigned Opcode); in PPCInstrInfo? Then we can query it wherever we need it. I don't imagine there's anything about that query that would require an actual instance of the class, but I haven't checked so it may not be possible to make it static.

lib/Target/PowerPC/PPCInstrInfo.h

72

/// This instruction is an X-Form memory operation.

[stefanp]

lib/Target/PowerPC/PPCInstrInfo.cpp

1115

I've created the function bool isXFormMemOp(unsigned Opcode) const;. I was not able to make it static because I have to call MCInstrInfo::get.

lib/Target/PowerPC/PPCInstrInfo.h

 
 enum {
   /// Shift count to bypass PPC970 flags
   NewDef_Shift = 6,
 
   /// The VSX instruction that uses VSX register (vs0-vs63), instead of VMX
   /// register (v0-v31).
   UseVSXReg = 0x1 << NewDef_Shift
 };
 } // end namespace PPCII
 
 // Instructions that have an immediate form might be convertible to that
 // form if the correct input is a result of a load immediate. In order to
 // know whether the transformation is special, we might need to know some
 // of the details of the two forms.
 struct ImmInstrInfo {
   // Is the immediate field in the immediate form signed or unsigned?

 // Information required to convert an instruction to just a materialized
 // immediate.
 struct LoadImmediateInfo {
   unsigned Imm : 16;
   unsigned Is64Bit : 1;
   unsigned SetCR : 1;
 };
 
 class PPCSubtarget;
 class PPCInstrInfo : public PPCGenInstrInfo {
   PPCSubtarget &Subtarget;
   const PPCRegisterInfo RI;
 
-  bool StoreRegToStackSlot(MachineFunction &MF,
-                           unsigned SrcReg, bool isKill, int FrameIdx,
-                           const TargetRegisterClass *RC,
-                           SmallVectorImpl<MachineInstr*> &NewMIs,
-                           bool &NonRI, bool &SpillsVRS) const;
+  void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
+                           int FrameIdx, const TargetRegisterClass *RC,
+                           SmallVectorImpl<MachineInstr *> &NewMIs) const;
   bool LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
                             unsigned DestReg, int FrameIdx,
                             const TargetRegisterClass *RC,
                             SmallVectorImpl<MachineInstr *> &NewMIs,
                             bool &NonRI, bool &SpillsVRS) const;
   bool transformToImmForm(MachineInstr &MI, const ImmInstrInfo &III,
                           unsigned ConstantOpNo, int64_t Imm) const;
   MachineInstr *getConstantDefMI(MachineInstr &MI, unsigned &ConstOp,
                                  bool &SeenIntermediateUse) const;
+  const unsigned *getOpcodesForSpillArray(bool ArchPower9) const;
   virtual void anchor();
 
 protected:
   /// Commutes the operands in the given instruction.
   /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
   ///
   /// Do not call this method for a non-commutable instruction or for
   /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
void storeRegToStackSlot(MachineBasicBlock &MBB,
                            const TargetRegisterInfo *TRI) const override;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
                             unsigned DestReg, int FrameIndex,
                             const TargetRegisterClass *RC,
                             const TargetRegisterInfo *TRI) const override;
 
+  unsigned getOpcodeForSpill(unsigned Reg,
+                             const TargetRegisterClass *RC = nullptr) const;
+
   bool
   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 
   bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
                      MachineRegisterInfo *MRI) const override;
 
   // If conversion by predication (only supported by some branch instructions).
   // All of the profitability checks always return true; it is always

lib/Target/PowerPC/PPCInstrInfo.cpp

 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
 cl::Hidden);
 
 static cl::opt<bool>
 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
   cl::desc("Use the old (incorrect) instruction latency calculation"));
 
+// Index into the OpcodesForSpill array
+enum OpcodesForSpillKey {
+  PPC_STW,
+  PPC_STD,
+  PPC_STFD,
+  PPC_STFS,
+  PPC_SPILL_CR,
+  PPC_SPILL_CRBIT,
+  PPC_STVX,
+  PPC_STXVD2X,
+  PPC_STXSDX,
+  PPC_STXSSPX,
+  PPC_SPILL_VRSAVE,
+  PPC_QVSTFDX,
+  PPC_QVSTFSXs,
+  PPC_QVSTFDXb,
+  PPC_SPILLTOVSR_ST,
+  PPC_LAST_OPCODE_SPILL  // This must be last on the enum
+};
+
 // Pin the vtable to this file.
 void PPCInstrInfo::anchor() {}
 
 PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
     : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
                       /* CatchRetOpcode */ -1,
                       STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
       Subtarget(STI), RI(STI.getTargetMachine()) {}
bool PPCInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
   case PPC::LOAD_STACK_GUARD:
     return true;
   }
   return false;
 }
 
 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
                                           int &FrameIndex) const {
-  // Note: This list must be kept consistent with StoreRegToStackSlot.
-  switch (MI.getOpcode()) {
-  default: break;
-  case PPC::STD:
-  case PPC::STW:
-  case PPC::STFS:
-  case PPC::STFD:
-  case PPC::SPILL_CR:
-  case PPC::SPILL_CRBIT:
-  case PPC::STVX:
-  case PPC::STXVD2X:
-  case PPC::STXV:
-  case PPC::QVSTFDX:
-  case PPC::QVSTFSXs:
-  case PPC::QVSTFDXb:
-  case PPC::SPILL_VRSAVE:
-  case PPC::SPILLTOVSR_ST:
+  unsigned Opcode = MI.getOpcode();
+  const unsigned *OpcodesForSpill =
+      getOpcodesForSpillArray(Subtarget.hasP9Vector());
+
+  for (unsigned i = 0; i < PPC_LAST_OPCODE_SPILL; i++) {
+    if (OpcodesForSpill[i] == Opcode) {
       // Check for the operands added by addFrameReference (the immediate is the
       // offset which defaults to 0).
       if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
           MI.getOperand(2).isFI()) {
         FrameIndex = MI.getOperand(2).getIndex();
         return MI.getOperand(0).getReg();
       }
-    break;
+    }
   }
   return 0;
 }
 
 MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
                                                    unsigned OpIdx1,
                                                    unsigned OpIdx2) const {
   MachineFunction &MF = *MI.getParent()->getParent();
void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   const MCInstrDesc &MCID = get(Opc);
   if (MCID.getNumOperands() == 3)
     BuildMI(MBB, I, DL, MCID, DestReg)
       .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
   else
     BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
 }
 
-// This function returns true if a CR spill is necessary and false otherwise.
-bool
-PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
-                                  unsigned SrcReg, bool isKill,
-                                  int FrameIdx,
-                                  const TargetRegisterClass *RC,
-                                  SmallVectorImpl<MachineInstr*> &NewMIs,
-                                  bool &NonRI, bool &SpillsVRS) const{
-  // Note: If additional store instructions are added here,
-  // update isStoreToStackSlot.
+unsigned PPCInstrInfo::getOpcodeForSpill(unsigned Reg,
+                                         const TargetRegisterClass *RC) const {
+  const unsigned *OpcodesForSpill =
+      getOpcodesForSpillArray(Subtarget.hasP9Vector());
+  int OpcodeIndex = 0;
 
-  DebugLoc DL;
+  if (RC != nullptr) {
     if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
         PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
-                                       .addReg(SrcReg,
-                                               getKillRegState(isKill)),
-                                       FrameIdx));
+      OpcodeIndex = PPC_STW;
     } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
                PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
-                                       .addReg(SrcReg,
-                                               getKillRegState(isKill)),
-                                       FrameIdx));
+      OpcodeIndex = PPC_STD;
     } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
-                                       .addReg(SrcReg,
-                                               getKillRegState(isKill)),
-                                       FrameIdx));
+      OpcodeIndex = PPC_STFD;
     } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
-                                       .addReg(SrcReg,
-                                               getKillRegState(isKill)),
-                                       FrameIdx));
+      OpcodeIndex = PPC_STFS;
     } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
-                                       .addReg(SrcReg,
-                                               getKillRegState(isKill)),
-                                       FrameIdx));
-    return true;
+      OpcodeIndex = PPC_SPILL_CR;
     } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
-                                       .addReg(SrcReg,
-                                               getKillRegState(isKill)),
-                                       FrameIdx));
-    return true;
+      OpcodeIndex = PPC_SPILL_CRBIT;
     } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
-                                       .addReg(SrcReg,
-                                               getKillRegState(isKill)),
-                                       FrameIdx));
-    NonRI = true;
+      OpcodeIndex = PPC_STVX;
     } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
-    unsigned Op = Subtarget.hasP9Vector() ? PPC::STXV : PPC::STXVD2X;
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op))
-                                       .addReg(SrcReg,
-                                               getKillRegState(isKill)),
-                                       FrameIdx));
-    NonRI = true;
+      OpcodeIndex = PPC_STXVD2X;
     } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
-    unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf64 : PPC::STXSDX;
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc))
-                                       .addReg(SrcReg,
-                                               getKillRegState(isKill)),
-                                       FrameIdx));
-    NonRI = true;
+      OpcodeIndex = PPC_STXSDX;
     } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
-    unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf32 : PPC::STXSSPX;
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc))
-                                       .addReg(SrcReg,
-                                               getKillRegState(isKill)),
-                                       FrameIdx));
-    NonRI = true;
+      OpcodeIndex = PPC_STXSSPX;
     } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
-    assert(Subtarget.isDarwin() &&
-           "VRSAVE only needs spill/restore on Darwin");
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
-                                       .addReg(SrcReg,
-                                               getKillRegState(isKill)),
-                                       FrameIdx));
-    SpillsVRS = true;
+      OpcodeIndex = PPC_SPILL_VRSAVE;
     } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX))
-                                       .addReg(SrcReg,
-                                               getKillRegState(isKill)),
-                                       FrameIdx));
-    NonRI = true;
+      OpcodeIndex = PPC_QVSTFDX;
     } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs))
-                                       .addReg(SrcReg,
-                                               getKillRegState(isKill)),
-                                       FrameIdx));
-    NonRI = true;
+      OpcodeIndex = PPC_QVSTFSXs;
     } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb))
-                                       .addReg(SrcReg,
-                                               getKillRegState(isKill)),
-                                       FrameIdx));
-    NonRI = true;
+      OpcodeIndex = PPC_QVSTFDXb;
     } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
-    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILLTOVSR_ST))
-                                       .addReg(SrcReg,
-                                               getKillRegState(isKill)),
-                                       FrameIdx));
+      OpcodeIndex = PPC_SPILLTOVSR_ST;
+    } else {
+      llvm_unreachable("Unknown regclass!");
+    }
+  } else {
+    if (PPC::GPRCRegClass.contains(Reg) ||
+        PPC::GPRC_NOR0RegClass.contains(Reg)) {
+      OpcodeIndex = PPC_STW;
+    } else if (PPC::G8RCRegClass.contains(Reg) ||
+               PPC::G8RC_NOX0RegClass.contains(Reg)) {
+      OpcodeIndex = PPC_STD;
+    } else if (PPC::F8RCRegClass.contains(Reg)) {
+      OpcodeIndex = PPC_STFD;
+    } else if (PPC::F4RCRegClass.contains(Reg)) {
+      OpcodeIndex = PPC_STFS;
+    } else if (PPC::CRRCRegClass.contains(Reg)) {
+      OpcodeIndex = PPC_SPILL_CR;
+    } else if (PPC::CRBITRCRegClass.contains(Reg)) {
+      OpcodeIndex = PPC_SPILL_CRBIT;
+    } else if (PPC::VRRCRegClass.contains(Reg)) {
+      OpcodeIndex = PPC_STVX;
+    } else if (PPC::VSRCRegClass.contains(Reg)) {
+      OpcodeIndex = PPC_STXVD2X;
+    } else if (PPC::VSFRCRegClass.contains(Reg)) {
+      OpcodeIndex = PPC_STXSDX;
+    } else if (PPC::VSSRCRegClass.contains(Reg)) {
+      OpcodeIndex = PPC_STXSSPX;
+    } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
+      OpcodeIndex = PPC_SPILL_VRSAVE;
+    } else if (PPC::QFRCRegClass.contains(Reg)) {
+      OpcodeIndex = PPC_QVSTFDX;
+    } else if (PPC::QSRCRegClass.contains(Reg)) {
+      OpcodeIndex = PPC_QVSTFSXs;
+    } else if (PPC::QBRCRegClass.contains(Reg)) {
+      OpcodeIndex = PPC_QVSTFDXb;
+    } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
+      OpcodeIndex = PPC_SPILLTOVSR_ST;
     } else {
       llvm_unreachable("Unknown regclass!");
     }
+  }
+  return OpcodesForSpill[OpcodeIndex];
+}
 
-  return false;
+void PPCInstrInfo::StoreRegToStackSlot(
+    MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
+    const TargetRegisterClass *RC,
+    SmallVectorImpl<MachineInstr *> &NewMIs) const {
+  unsigned Opcode = getOpcodeForSpill(0, RC);
+  DebugLoc DL;
+
+  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
+  FuncInfo->setHasSpills();
+
+  NewMIs.push_back(addFrameReference(
+      BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
+      FrameIdx));
+
+  if (Opcode == PPC::SPILL_CR || Opcode == PPC::SPILL_CRBIT)
+    FuncInfo->setSpillsCR();
+
+  if (Opcode == PPC::SPILL_VRSAVE)
+    FuncInfo->setSpillsVRSAVE();
+
+  if (Opcode == PPC::STVX || Opcode == PPC::STXV || Opcode == PPC::STXVD2X ||
+      Opcode == PPC::DFSTOREf64 || Opcode == PPC::STXSDX ||
+      Opcode == PPC::DFSTOREf32 || Opcode == PPC::STXSSPX ||
+      Opcode == PPC::QVSTFDX || Opcode == PPC::QVSTFSXs ||
+      Opcode == PPC::QVSTFDXb)
+    FuncInfo->setHasNonRISpills();
 }
 
-void
-PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
+void PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MI,
-                                  unsigned SrcReg, bool isKill, int FrameIdx,
+                                       unsigned SrcReg, bool isKill,
+                                       int FrameIdx,
                                        const TargetRegisterClass *RC,
                                        const TargetRegisterInfo *TRI) const {
   MachineFunction &MF = *MBB.getParent();
-  SmallVector<MachineInstr*, 4> NewMIs;
+  SmallVector<MachineInstr *, 4> NewMIs;
 
-  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
-  FuncInfo->setHasSpills();
-
   // We need to avoid a situation in which the value from a VRRC register is
   // spilled using an Altivec instruction and reloaded into a VSRC register
   // using a VSX instruction. The issue with this is that the VSX
   // load/store instructions swap the doublewords in the vector and the Altivec
   // ones don't. The register classes on the spill/reload may be different if
   // the register is defined using an Altivec instruction and is then used by a
   // VSX instruction.
   RC = updatedRC(RC);
 
-  bool NonRI = false, SpillsVRS = false;
-  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
-                          NonRI, SpillsVRS))
-    FuncInfo->setSpillsCR();
-
-  if (SpillsVRS)
-    FuncInfo->setSpillsVRSAVE();
-
-  if (NonRI)
-    FuncInfo->setHasNonRISpills();
+  StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
 
   for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
     MBB.insert(MI, NewMIs[i]);
 
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   MachineMemOperand *MMO = MF.getMachineMemOperand(
       MachinePointerInfo::getFixedStack(MF, FrameIdx),
       MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
             SeenIntermediateUse = true;
         }
       }
     }
   }
   return ConstOp == ~0U ? nullptr : DefMI;
 }
 
+
+const unsigned *PPCInstrInfo::getOpcodesForSpillArray(bool ArchPower9) const {
+  static const unsigned OpcodesForSpill[2][PPC_LAST_OPCODE_SPILL] = {
+    // Power 8
+    {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT,
+     PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, PPC::SPILL_VRSAVE,
+     PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb, PPC::SPILLTOVSR_ST},
+    // Power 9
+    {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT,
+     PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, PPC::SPILL_VRSAVE,
+     PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb, PPC::SPILLTOVSR_ST}};
+
+  return OpcodesForSpill[ArchPower9];
+}
+
 // If this instruction has an immediate form and one of its operands is a
 // result of a load-immediate, convert it to the immediate form if the constant
 // is in range.
 bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
                                           MachineInstr **KilledDef) const {
   MachineFunction *MF = MI.getParent()->getParent();
   MachineRegisterInfo *MRI = &MF->getRegInfo();
   bool PostRA = !MRI->isSSA();