AMDGPU: Support target triple OS component cuda

[yaxunl]

Summary

This patch allows AMDGPU backend consumes IR generated by clang for CUDA.

Patch by Greg Rodgers.

[arsenm]

You're using this just as an alias for AMDHSAOS. We shouldn't add something that behaves exactly the same

lib/Target/AMDGPU/SIISelLowering.cpp

5797

Dead code

[b-sumner]

In D42711#992503, @arsenm wrote:

You're using this just as an alias for AMDHSAOS. We shouldn't add something that behaves exactly the same

I agree. The IR should just get the right OS to start with.

[yaxunl]

I think the purpose of this patch is to get a similar usage of clang as nvptx when compiling CUDA, i.e., using cuda as OS instead of using amdhsa as OS and amdgiz as environment. This is more convenient for CUDA application developers since they just need to swap nvptx with amdgcn.

[b-sumner]

As I understand it, the option users pass to clang++ is --cuda-gpu-arch=<Arch>. Can't we arrange to generate the right triple if they use gfx900 or some other AMD target name for <Arch>?

[arsenm]

In D42711#992517, @yaxunl wrote:

I think the purpose of this patch is to get a similar usage of clang as nvptx when compiling CUDA, i.e., using cuda as OS instead of using amdhsa as OS and amdgiz as environment. This is more convenient for CUDA application developers since they just need to swap nvptx with amdgcn.

This is a frontend driver question at most. The backend shouldn't need to be aware of this

[yaxunl]

In D42711#992555, @arsenm wrote:

In D42711#992517, @yaxunl wrote:

I think the purpose of this patch is to get a similar usage of clang as nvptx when compiling CUDA, i.e., using cuda as OS instead of using amdhsa as OS and amdgiz as environment. This is more convenient for CUDA application developers since they just need to swap nvptx with amdgcn.

This is a frontend driver question at most. The backend shouldn't need to be aware of this

There are various places in clang where selection is done based on OS==CUDA. If we don't use that OS, we need more complex logic in clang for such choices. I can try making changes to clang to make it work, but I suspect there may be places using OS==CUDA is necessary since it may be needed before parsing the language options.

[b-sumner]

In D42711#993438, @yaxunl wrote:

In D42711#992555, @arsenm wrote:

In D42711#992517, @yaxunl wrote:

I think the purpose of this patch is to get a similar usage of clang as nvptx when compiling CUDA, i.e., using cuda as OS instead of using amdhsa as OS and amdgiz as environment. This is more convenient for CUDA application developers since they just need to swap nvptx with amdgcn.

This is a frontend driver question at most. The backend shouldn't need to be aware of this

There are various places in clang where selection is done based on OS==CUDA. If we don't use that OS, we need more complex logic in clang for such choices. I can try making changes to clang to make it work, but I suspect there may be places using OS==CUDA is necessary since it may be needed before parsing the language options.

Changing those selections make sense to me since was are adding support for a completely new and different target.

[jlebar]

In D42711#993457, @b-sumner wrote:

Changing those selections make sense to me since was are adding support for a completely new and different target.

As one of the CUDA maintainers, this also makes sense to me, although we're going to need tests and (to the extent possible) wrapper functions so that it doesn't break.

[yaxunl]

In D42711#993470, @jlebar wrote:

In D42711#993457, @b-sumner wrote:

Changing those selections make sense to me since was are adding support for a completely new and different target.

As one of the CUDA maintainers, this also makes sense to me, although we're going to need tests and (to the extent possible) wrapper functions so that it doesn't break.

There is another concern. If we need to identify IR originated from CUDA in AMDHSA OS, what should we do? Introduce CUDA again as an environment component?

[arsenm]

In D42711#993511, @yaxunl wrote:

In D42711#993470, @jlebar wrote:

In D42711#993457, @b-sumner wrote:

Changing those selections make sense to me since was are adding support for a completely new and different target.

As one of the CUDA maintainers, this also makes sense to me, although we're going to need tests and (to the extent possible) wrapper functions so that it doesn't break.

There is another concern. If we need to identify IR originated from CUDA in AMDHSA OS, what should we do? Introduce CUDA again as an environment component?

There shouldn't be any reason to do this. The IR shouldn't really care what the source was.

[yaxunl]

In D42711#993524, @arsenm wrote:

In D42711#993511, @yaxunl wrote:

In D42711#993470, @jlebar wrote:

In D42711#993457, @b-sumner wrote:

Changing those selections make sense to me since was are adding support for a completely new and different target.

As one of the CUDA maintainers, this also makes sense to me, although we're going to need tests and (to the extent possible) wrapper functions so that it doesn't break.

There is another concern. If we need to identify IR originated from CUDA in AMDHSA OS, what should we do? Introduce CUDA again as an environment component?

There shouldn't be any reason to do this. The IR shouldn't really care what the source was.

Then why do we need opencl environment component in the triple?

[arsenm]

In D42711#993538, @yaxunl wrote:

In D42711#993524, @arsenm wrote:

In D42711#993511, @yaxunl wrote:

In D42711#993470, @jlebar wrote:

In D42711#993457, @b-sumner wrote:

Changing those selections make sense to me since was are adding support for a completely new and different target.

As one of the CUDA maintainers, this also makes sense to me, although we're going to need tests and (to the extent possible) wrapper functions so that it doesn't break.

There is another concern. If we need to identify IR originated from CUDA in AMDHSA OS, what should we do? Introduce CUDA again as an environment component?

There shouldn't be any reason to do this. The IR shouldn't really care what the source was.

Then why do we need opencl environment component in the triple?

This specifies the ABI change for the entry point

[yaxunl]

no longer needed

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const {
   return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
 }
 
 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
   if (TM.getTargetTriple().getArch() != Triple::amdgcn)
     return;
 
   if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
+      TM.getTargetTriple().getOS() != Triple::CUDA &&
       TM.getTargetTriple().getOS() != Triple::AMDPAL)
     return;
 
-  if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
+  if (TM.getTargetTriple().getOS() == Triple::AMDHSA ||
+      TM.getTargetTriple().getOS() == Triple::CUDA)
     HSAMetadataStream.begin(M);
 
   if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
     readPALMetadata(M);
 
   // Deprecated notes are not emitted for code object v3.
   if (IsaInfo::hasCodeObjectV3(getSTI()->getFeatureBits()))
     return;
 
   // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
-  if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
+  if (TM.getTargetTriple().getOS() == Triple::AMDHSA ||
+      TM.getTargetTriple().getOS() == Triple::CUDA)
     getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1);
 
   // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
   IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
   getTargetStreamer()->EmitDirectiveHSACodeObjectISA(
       ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
 }
 
 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
   if (TM.getTargetTriple().getArch() != Triple::amdgcn)
     return;
 
   // Following code requires TargetStreamer to be present.
   if (!getTargetStreamer())
     return;
 
   // Emit ISA Version (NT_AMD_AMDGPU_ISA).
   std::string ISAVersionString;
   raw_string_ostream ISAVersionStream(ISAVersionString);
   IsaInfo::streamIsaVersion(getSTI(), ISAVersionStream);
   getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
 
   // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
-  if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
+  if (TM.getTargetTriple().getOS() == Triple::AMDHSA ||
+      TM.getTargetTriple().getOS() == Triple::CUDA) {
     HSAMetadataStream.end();
     getTargetStreamer()->EmitHSAMetadata(HSAMetadataStream.getHSAMetadata());
   }
 
   // Emit PAL Metadata (NT_AMD_AMDGPU_PAL_METADATA).
   if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
     // Copy the PAL metadata from the map where we collected it into a vector,
     // then write it as a .note.
void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
   amd_kernel_code_t KernelCode;
   if (STM.isAmdCodeObjectV2(*MF)) {
     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
 
     OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
     getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
   }
 
-  if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
+  if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
+      TM.getTargetTriple().getOS() != Triple::CUDA)
     return;
 
   HSAMetadataStream.emitKernel(MF->getFunction(),
                                getHSACodeProps(*MF, CurrentProgramInfo),
                                getHSADebugProps(*MF, CurrentProgramInfo));
 }
 
 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {

lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp

bool AMDGPUPromoteAlloca::runOnFunction(Function &F) {
 
   if (auto *TPC = getAnalysisIfAvailable<TargetPassConfig>())
     TM = &TPC->getTM<TargetMachine>();
   else
     return false;
 
   const Triple &TT = TM->getTargetTriple();
   IsAMDGCN = TT.getArch() == Triple::amdgcn;
-  IsAMDHSA = TT.getOS() == Triple::AMDHSA;
+  IsAMDHSA = (TT.getOS() == Triple::AMDHSA || TT.getOS() == Triple::CUDA);
 
   const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(F);
   if (!ST.isPromoteAllocaEnabled())
     return false;
 
   AS = AMDGPU::getAMDGPUAS(*F.getParent());
 
   bool SufficientLDS = hasSufficientLocalMem(F);

lib/Target/AMDGPU/AMDGPUSubtarget.h

public:
   // Nothing implemented, just prevent crashes on use.
   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
 
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
   bool isAmdHsaOS() const {
-    return TargetTriple.getOS() == Triple::AMDHSA;
+    return (TargetTriple.getOS() == Triple::AMDHSA ||
+            TargetTriple.getOS() == Triple::CUDA);
   }
 
   bool isMesa3DOS() const {
     return TargetTriple.getOS() == Triple::Mesa3D;
   }
 
   bool isOpenCLEnv() const {
     return TargetTriple.getEnvironment() == Triple::OpenCL ||

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

if (TT.getEnvironmentName() == "amdgiz" ||
       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
             "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
   }
 
   // 32-bit private, local, and region pointers. 64-bit global, constant and
   // flat.
-  if (TT.getEnvironmentName() == "amdgiz" ||
+  if (TT.getOS() == Triple::CUDA || TT.getEnvironmentName() == "amdgiz" ||
       TT.getEnvironmentName() == "amdgizcl")
     return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
       "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
       "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
 }

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

 
   getTargetStreamer().EmitISAVersion(ISAVersionStreamFromSTI.str());
   Lex();
 
   return false;
 }
 
 bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() {
-  if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA) {
+  if ((getSTI().getTargetTriple().getOS() != Triple::AMDHSA) &&
+      (getSTI().getTargetTriple().getOS() != Triple::CUDA)) {
     return Error(getParser().getTok().getLoc(),
                  (Twine(HSAMD::AssemblerDirectiveBegin) + Twine(" directive is "
                  "not available on non-amdhsa OSes")).str());
   }
 
   std::string HSAMetadataString;
   raw_string_ostream YamlStream(HSAMetadataString);
 

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

 namespace {
 
 class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
   bool Is64Bit;
   bool HasRelocationAddend;
   uint8_t OSABI = ELF::ELFOSABI_NONE;
 
 public:
-  ELFAMDGPUAsmBackend(const Target &T, const Triple &TT) :
-      AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn),
-      HasRelocationAddend(TT.getOS() == Triple::AMDHSA) {
+  ELFAMDGPUAsmBackend(const Target &T, const Triple &TT)
+      : AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn),
+        HasRelocationAddend((TT.getOS() == Triple::AMDHSA) ||
+                            (TT.getOS() == Triple::CUDA)) {
     switch (TT.getOS()) {
     case Triple::AMDHSA:
+    case Triple::CUDA:
       OSABI = ELF::ELFOSABI_AMDGPU_HSA;
       break;
     case Triple::AMDPAL:
       OSABI = ELF::ELFOSABI_AMDGPU_PAL;
       break;
     case Triple::Mesa3D:
       OSABI = ELF::ELFOSABI_AMDGPU_MESA3D;
       break;

lib/Target/AMDGPU/SIISelLowering.cpp

 
     if (NumElements == 2)
       return Op;
 
     // If properly aligned, if we split we might be able to use ds_write_b64.
     return SplitVectorStore(Op, DAG);
   } else {
     llvm_unreachable("unhandled address space");
+    printf("------> unhandled address space %d\n", AS);
   }
 }
 
 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
   SDLoc DL(Op);
   EVT VT = Op.getValueType();
   SDValue Arg = Op.getOperand(0);
   // TODO: Should this propagate fast-math-flags?

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

bool isGlobalSegment(const GlobalValue *GV) {
   return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
 }
 
 bool isReadOnlySegment(const GlobalValue *GV) {
   return GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS;
 }
 
 bool shouldEmitConstantsToTextSection(const Triple &TT) {
-  return TT.getOS() != Triple::AMDHSA;
+  return (TT.getOS() != Triple::AMDHSA && TT.getOS() != Triple::CUDA);
 }
 
 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
   Attribute A = F.getFnAttribute(Name);
   int Result = Default;
 
   if (A.isStringAttribute()) {
     StringRef Str = A.getValueAsString();

 } // end namespace llvm
 
 namespace llvm {
 namespace AMDGPU {
 
 AMDGPUAS getAMDGPUAS(Triple T) {
   auto Env = T.getEnvironmentName();
   AMDGPUAS AS;
-  if (Env == "amdgiz" || Env == "amdgizcl") {
+  if (Env == "amdgiz" || Env == "amdgizcl" || (T.getOS() == Triple::CUDA)) {
     AS.FLAT_ADDRESS     = 0;
     AS.PRIVATE_ADDRESS  = 5;
     AS.REGION_ADDRESS   = 4;
   }
   else {
     AS.FLAT_ADDRESS     = 4;
     AS.PRIVATE_ADDRESS  = 0;
     AS.REGION_ADDRESS   = 5;