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[RISCV] Implement support for the BranchRelaxation pass
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Authored by asb on Dec 5 2017, 2:52 AM.

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Summary

Branch relaxation is needed to support branch displacements that overflow the instruction's immediate field.

This is the last non-trivial patch required for a 100% pass rate of the GCC torture suite targeting RV32I.

The churn in bswap-ctlz-cttz-ctpop.ll and jumptable.ll seems unfortunate, but I don't think it's caused by lib/Target/RISCV logic.

Diff Detail

Repository
rL LLVM

Event Timeline

asb created this revision.Dec 5 2017, 2:52 AM
asb updated this revision to Diff 126358.Dec 11 2017, 6:51 AM

Refresh patch.

asb updated this revision to Diff 127107.Dec 15 2017, 4:57 AM

Rebase patch (changes only to tests, following the printing of instruction aliases by default).

LGTM with minor nitpick

lib/Target/RISCV/RISCVInstrInfo.cpp
332 ↗(On Diff #126358)

Add some vertical whitespace around here somewhere, the code is quite dense

This looks fine except for the indentation issue mentioned in lib/Target/RISCV/RISCVInstrInfo.cpp.

apazos accepted this revision.Jan 8 2018, 12:41 PM
This revision is now accepted and ready to land.Jan 8 2018, 12:41 PM
This revision was automatically updated to reflect the committed changes.