[AArch64][SVE] Asm: Add ZIP1/ZIP2 instructions (predicate/data vectors)

[sdesmalen]

Summary

Patch [2/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions.

[rengolin]

There are too many redundant tests. I'd keep one for each size/type on both boundaries (0, 31) and add negative tests to check that you can't zip predicate registers with data registers, register numbers out of bounds, different number of registers (2, 4), etc.

[sdesmalen]

Removed redundancy from the assembler/disassembler tests and added new negative tests to zip(1|2)-diagnostics.s

[fhahn]

LGTM, thanks for reducing the test cases as Renato suggested.

lib/Target/AArch64/AArch64SVEInstrInfo.td

 //=- AArch64SVEInstrInfo.td -  AArch64 SVE Instructions -*- tablegen -*-----=//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // AArch64 Scalable Vector Extension (SVE) Instruction definitions.
 //
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasSVE] in {
   defm ADD_ZZZ   : sve_int_bin_cons_arit_0<0b000, "add">;
   defm SUB_ZZZ   : sve_int_bin_cons_arit_0<0b001, "sub">;
+
+  defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">;
+  defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">;
+
+  defm ZIP1_PPP : sve_int_perm_bin_perm_pp<0b000, "zip1">;
+  defm ZIP2_PPP : sve_int_perm_bin_perm_pp<0b001, "zip2">;
 }

lib/Target/AArch64/SVEInstrFormats.td

 }
 
 multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm> {
   def _B : sve_int_bin_cons_arit_0<0b00, opc, asm, ZPR8>;
   def _H : sve_int_bin_cons_arit_0<0b01, opc, asm, ZPR16>;
   def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>;
   def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>;
 }
+
+//===----------------------------------------------------------------------===//
+// SVE Permute - In Lane Group
+//===----------------------------------------------------------------------===//
+
+class sve_int_perm_bin_perm_zz<bits<3> opc, bits<2> sz8_64, string asm,
+                               ZPRRegOp zprty>
+: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
+  asm, "\t$Zd, $Zn, $Zm",
+  "",
+  []>, Sched<[]> {
+  bits<5> Zd;
+  bits<5> Zm;
+  bits<5> Zn;
+  let Inst{31-24} = 0b00000101;
+  let Inst{23-22} = sz8_64;
+  let Inst{21}    = 0b1;
+  let Inst{20-16} = Zm;
+  let Inst{15-13} = 0b011;
+  let Inst{12-10} = opc;
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Zd;
+}
+
+multiclass sve_int_perm_bin_perm_zz<bits<3> opc, string asm> {
+  def _B : sve_int_perm_bin_perm_zz<opc, 0b00, asm, ZPR8>;
+  def _H : sve_int_perm_bin_perm_zz<opc, 0b01, asm, ZPR16>;
+  def _S : sve_int_perm_bin_perm_zz<opc, 0b10, asm, ZPR32>;
+  def _D : sve_int_perm_bin_perm_zz<opc, 0b11, asm, ZPR64>;
+}
+
+//===----------------------------------------------------------------------===//
+// SVE Permute - Predicates Group
+//===----------------------------------------------------------------------===//
+
+class sve_int_perm_bin_perm_pp<bits<3> opc, bits<2> sz8_64, string asm,
+                               PPRRegOp pprty>
+: I<(outs pprty:$Pd), (ins pprty:$Pn, pprty:$Pm),
+  asm, "\t$Pd, $Pn, $Pm",
+  "",
+  []>, Sched<[]> {
+  bits<4> Pd;
+  bits<4> Pm;
+  bits<4> Pn;
+  let Inst{31-24} = 0b00000101;
+  let Inst{23-22} = sz8_64;
+  let Inst{21-20} = 0b10;
+  let Inst{19-16} = Pm;
+  let Inst{15-13} = 0b010;
+  let Inst{12-10} = opc;
+  let Inst{9}     = 0b0;
+  let Inst{8-5}   = Pn;
+  let Inst{4}     = 0b0;
+  let Inst{3-0}   = Pd;
+}
+
+multiclass sve_int_perm_bin_perm_pp<bits<3> opc, string asm> {
+  def _B : sve_int_perm_bin_perm_pp<opc, 0b00, asm, PPR8>;
+  def _H : sve_int_perm_bin_perm_pp<opc, 0b01, asm, PPR16>;
+  def _S : sve_int_perm_bin_perm_pp<opc, 0b10, asm, PPR32>;
+  def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>;
+}
 No newline at end of file

test/MC/AArch64/SVE/zip1-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// Invalid element kind.
+zip1 z10.h, z22.h, z31.x
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
+// CHECK-NEXT: zip1 z10.h, z22.h, z31.x
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element size specifiers should match.
+zip1 z10.h, z3.h, z15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: zip1 z10.h, z3.h, z15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Too few operands
+zip1 z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
+// CHECK-NEXT: zip1 z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// z32 is not a valid SVE data register
+zip1 z1.s, z2.s, z32.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: zip1 z1.s, z2.s, z32.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// p16 is not a valid SVE predicate register
+zip1 p1.s, p2.s, p16.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: zip1 p1.s, p2.s, p16.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining data and predicate registers as operands
+zip1 z1.s, z2.s, p3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: zip1 z1.s, z2.s, p3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining predicate and data registers as operands
+zip1 p1.s, p2.s, z3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: zip1 p1.s, p2.s, z3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/zip1.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+zip1    z0.b, z0.b, z0.b
+// CHECK-INST: zip1    z0.b, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0x60,0x20,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 60 20 05 <unknown>
+
+zip1    z0.h, z0.h, z0.h
+// CHECK-INST: zip1    z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x60,0x60,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 60 60 05 <unknown>
+
+zip1    z0.s, z0.s, z0.s
+// CHECK-INST: zip1    z0.s, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0x60,0xa0,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 60 a0 05 <unknown>
+
+zip1    z0.d, z0.d, z0.d
+// CHECK-INST: zip1    z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x60,0xe0,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 60 e0 05 <unknown>
+
+zip1    z31.b, z31.b, z31.b
+// CHECK-INST: zip1    z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x63,0x3f,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ff 63 3f 05 <unknown>
+
+zip1    z31.h, z31.h, z31.h
+// CHECK-INST: zip1    z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x63,0x7f,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ff 63 7f 05 <unknown>
+
+zip1    z31.s, z31.s, z31.s
+// CHECK-INST: zip1    z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x63,0xbf,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ff 63 bf 05 <unknown>
+
+zip1    z31.d, z31.d, z31.d
+// CHECK-INST: zip1    z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x63,0xff,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ff 63 ff 05 <unknown>
+
+zip1    p0.b, p0.b, p0.b
+// CHECK-INST: zip1    p0.b, p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x20,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 40 20 05 <unknown>
+
+zip1    p0.h, p0.h, p0.h
+// CHECK-INST: zip1    p0.h, p0.h, p0.h
+// CHECK-ENCODING: [0x00,0x40,0x60,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 40 60 05 <unknown>
+
+zip1    p0.s, p0.s, p0.s
+// CHECK-INST: zip1    p0.s, p0.s, p0.s
+// CHECK-ENCODING: [0x00,0x40,0xa0,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 40 a0 05 <unknown>
+
+zip1    p0.d, p0.d, p0.d
+// CHECK-INST: zip1    p0.d, p0.d, p0.d
+// CHECK-ENCODING: [0x00,0x40,0xe0,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 40 e0 05 <unknown>
+
+zip1    p15.b, p15.b, p15.b
+// CHECK-INST: zip1    p15.b, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x41,0x2f,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ef 41 2f 05 <unknown>
+
+zip1    p15.s, p15.s, p15.s
+// CHECK-INST: zip1    p15.s, p15.s, p15.s
+// CHECK-ENCODING: [0xef,0x41,0xaf,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ef 41 af 05 <unknown>
+
+zip1    p15.h, p15.h, p15.h
+// CHECK-INST: zip1    p15.h, p15.h, p15.h
+// CHECK-ENCODING: [0xef,0x41,0x6f,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ef 41 6f 05 <unknown>
+
+zip1    p15.d, p15.d, p15.d
+// CHECK-INST: zip1    p15.d, p15.d, p15.d
+// CHECK-ENCODING: [0xef,0x41,0xef,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ef 41 ef 05 <unknown>

test/MC/AArch64/SVE/zip2-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// Invalid element kind.
+zip2 z6.h, z23.h, z31.x
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
+// CHECK-NEXT: zip2 z6.h, z23.h, z31.x
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element size specifiers should match.
+zip2 z0.h, z30.h, z24.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: zip2 z0.h, z30.h, z24.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Too few operands
+zip2 z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
+// CHECK-NEXT: zip2 z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// z32 is not a valid SVE data register
+zip2 z1.s, z2.s, z32.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: zip2 z1.s, z2.s, z32.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// p16 is not a valid SVE predicate register
+zip2 p1.s, p2.s, p16.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: zip2 p1.s, p2.s, p16.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining data and predicate registers as operands
+zip2 z1.s, z2.s, p3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: zip2 z1.s, z2.s, p3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining predicate and data registers as operands
+zip2 p1.s, p2.s, z3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: zip2 p1.s, p2.s, z3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/zip2.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+zip2    z0.b, z0.b, z0.b
+// CHECK-INST: zip2    z0.b, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0x64,0x20,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 64 20 05 <unknown>
+
+zip2    z0.h, z0.h, z0.h
+// CHECK-INST: zip2    z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x64,0x60,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 64 60 05 <unknown>
+
+zip2    z0.s, z0.s, z0.s
+// CHECK-INST: zip2    z0.s, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0x64,0xa0,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 64 a0 05 <unknown>
+
+zip2    z0.d, z0.d, z0.d
+// CHECK-INST: zip2    z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x64,0xe0,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 64 e0 05 <unknown>
+
+zip2    z31.b, z31.b, z31.b
+// CHECK-INST: zip2    z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x67,0x3f,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ff 67 3f 05 <unknown>
+
+zip2    z31.h, z31.h, z31.h
+// CHECK-INST: zip2    z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x67,0x7f,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ff 67 7f 05 <unknown>
+
+zip2    z31.s, z31.s, z31.s
+// CHECK-INST: zip2    z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x67,0xbf,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ff 67 bf 05 <unknown>
+
+zip2    z31.d, z31.d, z31.d
+// CHECK-INST: zip2    z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x67,0xff,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ff 67 ff 05 <unknown>
+
+zip2    p0.b, p0.b, p0.b
+// CHECK-INST: zip2    p0.b, p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x44,0x20,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 44 20 05 <unknown>
+
+zip2    p0.h, p0.h, p0.h
+// CHECK-INST: zip2    p0.h, p0.h, p0.h
+// CHECK-ENCODING: [0x00,0x44,0x60,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 44 60 05 <unknown>
+
+zip2    p0.s, p0.s, p0.s
+// CHECK-INST: zip2    p0.s, p0.s, p0.s
+// CHECK-ENCODING: [0x00,0x44,0xa0,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 44 a0 05 <unknown>
+
+zip2    p0.d, p0.d, p0.d
+// CHECK-INST: zip2    p0.d, p0.d, p0.d
+// CHECK-ENCODING: [0x00,0x44,0xe0,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: 00 44 e0 05 <unknown>
+
+zip2    p15.b, p15.b, p15.b
+// CHECK-INST: zip2    p15.b, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x45,0x2f,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ef 45 2f 05 <unknown>
+
+zip2    p15.h, p15.h, p15.h
+// CHECK-INST: zip2    p15.h, p15.h, p15.h
+// CHECK-ENCODING: [0xef,0x45,0x6f,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ef 45 6f 05 <unknown>
+
+zip2    p15.s, p15.s, p15.s
+// CHECK-INST: zip2    p15.s, p15.s, p15.s
+// CHECK-ENCODING: [0xef,0x45,0xaf,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ef 45 af 05 <unknown>
+
+zip2    p15.d, p15.d, p15.d
+// CHECK-INST: zip2    p15.d, p15.d, p15.d
+// CHECK-ENCODING: [0xef,0x45,0xef,0x05]
+// CHECK-ERROR: invalid predicate register
+// CHECK-UNKNOWN: ef 45 ef 05 <unknown>